2 * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved.
4 * Author: Tony Li <tony.li@freescale.com>
5 * Jason Jin <Jason.jin@freescale.com>
7 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2 of the
15 #include <linux/irq.h>
16 #include <linux/bootmem.h>
17 #include <linux/msi.h>
18 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/of_platform.h>
21 #include <sysdev/fsl_soc.h>
23 #include <asm/hw_irq.h>
24 #include <asm/ppc-pci.h>
27 struct fsl_msi_feature {
32 static struct fsl_msi *fsl_msi;
34 static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
36 return in_be32(base + (reg >> 2));
40 * We do not need this actually. The MSIR register has been read once
41 * in the cascade interrupt. So, this MSI interrupt has been acked
43 static void fsl_msi_end_irq(unsigned int virq)
47 static struct irq_chip fsl_msi_chip = {
49 .unmask = unmask_msi_irq,
50 .ack = fsl_msi_end_irq,
54 static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
57 struct irq_chip *chip = &fsl_msi_chip;
59 irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;
61 set_irq_chip_and_handler(virq, chip, handle_edge_irq);
66 static struct irq_host_ops fsl_msi_host_ops = {
67 .map = fsl_msi_host_map,
70 static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
74 rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
75 msi_data->irqhost->of_node);
79 rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
81 msi_bitmap_free(&msi_data->bitmap);
88 static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
90 if (type == PCI_CAP_ID_MSIX)
91 pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
96 static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
98 struct msi_desc *entry;
99 struct fsl_msi *msi_data = fsl_msi;
101 list_for_each_entry(entry, &pdev->msi_list, list) {
102 if (entry->irq == NO_IRQ)
104 set_irq_msi(entry->irq, NULL);
105 msi_bitmap_free_hwirqs(&msi_data->bitmap,
106 virq_to_hw(entry->irq), 1);
107 irq_dispose_mapping(entry->irq);
113 static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
116 struct fsl_msi *msi_data = fsl_msi;
117 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
120 pci_bus_read_config_dword(hose->bus,
121 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
123 msg->address_lo = msi_data->msi_addr_lo + base;
124 msg->address_hi = msi_data->msi_addr_hi;
127 pr_debug("%s: allocated srs: %d, ibs: %d\n",
128 __func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
131 static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
135 struct msi_desc *entry;
137 struct fsl_msi *msi_data = fsl_msi;
139 list_for_each_entry(entry, &pdev->msi_list, list) {
140 hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
143 pr_debug("%s: fail allocating msi interrupt\n",
148 virq = irq_create_mapping(msi_data->irqhost, hwirq);
150 if (virq == NO_IRQ) {
151 pr_debug("%s: fail mapping hwirq 0x%x\n",
153 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
157 set_irq_msi(virq, entry);
159 fsl_compose_msi_msg(pdev, hwirq, &msg);
160 write_msi_msg(virq, &msg);
168 static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
170 unsigned int cascade_irq;
171 struct fsl_msi *msi_data = fsl_msi;
177 raw_spin_lock(&desc->lock);
178 if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
179 if (desc->chip->mask_ack)
180 desc->chip->mask_ack(irq);
182 desc->chip->mask(irq);
183 desc->chip->ack(irq);
187 if (unlikely(desc->status & IRQ_INPROGRESS))
190 msir_index = (int)desc->handler_data;
192 if (msir_index >= NR_MSI_REG)
193 cascade_irq = NO_IRQ;
195 desc->status |= IRQ_INPROGRESS;
196 switch (fsl_msi->feature & FSL_PIC_IP_MASK) {
197 case FSL_PIC_IP_MPIC:
198 msir_value = fsl_msi_read(msi_data->msi_regs,
201 case FSL_PIC_IP_IPIC:
202 msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
207 intr_index = ffs(msir_value) - 1;
209 cascade_irq = irq_linear_revmap(msi_data->irqhost,
210 msir_index * IRQS_PER_MSI_REG +
211 intr_index + have_shift);
212 if (cascade_irq != NO_IRQ)
213 generic_handle_irq(cascade_irq);
214 have_shift += intr_index + 1;
215 msir_value = msir_value >> (intr_index + 1);
217 desc->status &= ~IRQ_INPROGRESS;
219 switch (msi_data->feature & FSL_PIC_IP_MASK) {
220 case FSL_PIC_IP_MPIC:
221 desc->chip->eoi(irq);
223 case FSL_PIC_IP_IPIC:
224 if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
225 desc->chip->unmask(irq);
229 raw_spin_unlock(&desc->lock);
232 static int __devinit fsl_of_msi_probe(struct of_device *dev,
233 const struct of_device_id *match)
241 struct fsl_msi_feature *features = match->data;
243 printk(KERN_DEBUG "Setting up Freescale MSI support\n");
245 msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
247 dev_err(&dev->dev, "No memory for MSI structure\n");
252 msi->irqhost = irq_alloc_host(dev->node, IRQ_HOST_MAP_LINEAR,
253 NR_MSI_IRQS, &fsl_msi_host_ops, 0);
255 if (msi->irqhost == NULL) {
256 dev_err(&dev->dev, "No memory for MSI irqhost\n");
261 /* Get the MSI reg base */
262 err = of_address_to_resource(dev->node, 0, &res);
264 dev_err(&dev->dev, "%s resource error!\n",
265 dev->node->full_name);
269 msi->msi_regs = ioremap(res.start, res.end - res.start + 1);
270 if (!msi->msi_regs) {
271 dev_err(&dev->dev, "ioremap problem failed\n");
275 msi->feature = features->fsl_pic_ip;
277 msi->irqhost->host_data = msi;
279 msi->msi_addr_hi = 0x0;
280 msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff);
282 rc = fsl_msi_init_allocator(msi);
284 dev_err(&dev->dev, "Error allocating MSI bitmap\n");
288 p = of_get_property(dev->node, "interrupts", &count);
290 dev_err(&dev->dev, "no interrupts property found on %s\n",
291 dev->node->full_name);
295 if (count % 8 != 0) {
296 dev_err(&dev->dev, "Malformed interrupts property on %s\n",
297 dev->node->full_name);
302 count /= sizeof(u32);
303 for (i = 0; i < count / 2; i++) {
306 virt_msir = irq_of_parse_and_map(dev->node, i);
307 if (virt_msir != NO_IRQ) {
308 set_irq_data(virt_msir, (void *)i);
309 set_irq_chained_handler(virt_msir, fsl_msi_cascade);
315 WARN_ON(ppc_md.setup_msi_irqs);
316 ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
317 ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
318 ppc_md.msi_check_device = fsl_msi_check_device;
325 static const struct fsl_msi_feature mpic_msi_feature = {
326 .fsl_pic_ip = FSL_PIC_IP_MPIC,
327 .msiir_offset = 0x140,
330 static const struct fsl_msi_feature ipic_msi_feature = {
331 .fsl_pic_ip = FSL_PIC_IP_IPIC,
332 .msiir_offset = 0x38,
335 static const struct of_device_id fsl_of_msi_ids[] = {
337 .compatible = "fsl,mpic-msi",
338 .data = (void *)&mpic_msi_feature,
341 .compatible = "fsl,ipic-msi",
342 .data = (void *)&ipic_msi_feature,
347 static struct of_platform_driver fsl_of_msi_driver = {
349 .match_table = fsl_of_msi_ids,
350 .probe = fsl_of_msi_probe,
353 static __init int fsl_of_msi_init(void)
355 return of_register_platform_driver(&fsl_of_msi_driver);
358 subsys_initcall(fsl_of_msi_init);