arch/powerpc/sysdev/commproc.c

   1 /*
   2  * General Purpose functions for the global management of the
   3  * Communication Processor Module.
   4  * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
   5  *
   6  * In addition to the individual control of the communication
   7  * channels, there are a few functions that globally affect the
   8  * communication processor.
   9  *
  10  * Buffer descriptors must be allocated from the dual ported memory
  11  * space.  The allocator for that is here.  When the communication
  12  * process is reset, we reclaim the memory available.  There is
  13  * currently no deallocator for this memory.
  14  * The amount of space available is platform dependent.  On the
  15  * MBX, the EPPC software loads additional microcode into the
  16  * communication processor, and uses some of the DP ram for this
  17  * purpose.  Current, the first 512 bytes and the last 256 bytes of
  18  * memory are used.  Right now I am conservative and only use the
  19  * memory that can never be used for microcode.  If there are
  20  * applications that require more DP ram, we can expand the boundaries
  21  * but then we have to be careful of any downloaded microcode.
  22  */
  23 #include <linux/errno.h>
  24 #include <linux/sched.h>
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/param.h>
  28 #include <linux/string.h>
  29 #include <linux/mm.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/irq.h>
  32 #include <linux/module.h>
  33 #include <asm/mpc8xx.h>
  34 #include <asm/page.h>
  35 #include <asm/pgtable.h>
  36 #include <asm/8xx_immap.h>
  37 #include <asm/commproc.h>
  38 #include <asm/io.h>
  39 #include <asm/tlbflush.h>
  40 #include <asm/rheap.h>
  41 #include <asm/prom.h>
  42 #include <asm/cpm.h>
  43
  44 #include <asm/fs_pd.h>
  45
  46 #define CPM_MAP_SIZE    (0x4000)
  47
  48 #ifndef CONFIG_PPC_CPM_NEW_BINDING
  49 static void m8xx_cpm_dpinit(void);
  50 #endif
  51 static uint host_buffer; /* One page of host buffer */
  52 static uint host_end;    /* end + 1 */
  53 cpm8xx_t __iomem *cpmp;  /* Pointer to comm processor space */
  54 immap_t __iomem *mpc8xx_immr;
  55 static cpic8xx_t __iomem *cpic_reg;
  56
  57 static struct irq_host *cpm_pic_host;
  58
  59 static void cpm_mask_irq(unsigned int irq)
  60 {
  61         unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
  62
  63         clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
  64 }
  65
  66 static void cpm_unmask_irq(unsigned int irq)
  67 {
  68         unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
  69
  70         setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
  71 }
  72
  73 static void cpm_end_irq(unsigned int irq)
  74 {
  75         unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
  76
  77         out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
  78 }
  79
  80 static struct irq_chip cpm_pic = {
  81         .typename = " CPM PIC ",
  82         .mask = cpm_mask_irq,
  83         .unmask = cpm_unmask_irq,
  84         .eoi = cpm_end_irq,
  85 };
  86
  87 int cpm_get_irq(void)
  88 {
  89         int cpm_vec;
  90
  91         /* Get the vector by setting the ACK bit and then reading
  92          * the register.
  93          */
  94         out_be16(&cpic_reg->cpic_civr, 1);
  95         cpm_vec = in_be16(&cpic_reg->cpic_civr);
  96         cpm_vec >>= 11;
  97
  98         return irq_linear_revmap(cpm_pic_host, cpm_vec);
  99 }
 100
 101 static int cpm_pic_host_map(struct irq_host *h, unsigned int virq,
 102                           irq_hw_number_t hw)
 103 {
 104         pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
 105
 106         get_irq_desc(virq)->status |= IRQ_LEVEL;
 107         set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
 108         return 0;
 109 }
 110
 111 /* The CPM can generate the error interrupt when there is a race condition
 112  * between generating and masking interrupts.  All we have to do is ACK it
 113  * and return.  This is a no-op function so we don't need any special
 114  * tests in the interrupt handler.
 115  */
 116 static irqreturn_t cpm_error_interrupt(int irq, void *dev)
 117 {
 118         return IRQ_HANDLED;
 119 }
 120
 121 static struct irqaction cpm_error_irqaction = {
 122         .handler = cpm_error_interrupt,
 123         .mask = CPU_MASK_NONE,
 124         .name = "error",
 125 };
 126
 127 static struct irq_host_ops cpm_pic_host_ops = {
 128         .map = cpm_pic_host_map,
 129 };
 130
 131 unsigned int cpm_pic_init(void)
 132 {
 133         struct device_node *np = NULL;
 134         struct resource res;
 135         unsigned int sirq = NO_IRQ, hwirq, eirq;
 136         int ret;
 137
 138         pr_debug("cpm_pic_init\n");
 139
 140         np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic");
 141         if (np == NULL)
 142                 np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
 143         if (np == NULL) {
 144                 printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
 145                 return sirq;
 146         }
 147
 148         ret = of_address_to_resource(np, 0, &res);
 149         if (ret)
 150                 goto end;
 151
 152         cpic_reg = ioremap(res.start, res.end - res.start + 1);
 153         if (cpic_reg == NULL)
 154                 goto end;
 155
 156         sirq = irq_of_parse_and_map(np, 0);
 157         if (sirq == NO_IRQ)
 158                 goto end;
 159
 160         /* Initialize the CPM interrupt controller. */
 161         hwirq = (unsigned int)irq_map[sirq].hwirq;
 162         out_be32(&cpic_reg->cpic_cicr,
 163             (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
 164                 ((hwirq/2) << 13) | CICR_HP_MASK);
 165
 166         out_be32(&cpic_reg->cpic_cimr, 0);
 167
 168         cpm_pic_host = irq_alloc_host(of_node_get(np), IRQ_HOST_MAP_LINEAR,
 169                                       64, &cpm_pic_host_ops, 64);
 170         if (cpm_pic_host == NULL) {
 171                 printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
 172                 sirq = NO_IRQ;
 173                 goto end;
 174         }
 175
 176         /* Install our own error handler. */
 177         np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
 178         if (np == NULL)
 179                 np = of_find_node_by_type(NULL, "cpm");
 180         if (np == NULL) {
 181                 printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
 182                 goto end;
 183         }
 184
 185         eirq = irq_of_parse_and_map(np, 0);
 186         if (eirq == NO_IRQ)
 187                 goto end;
 188
 189         if (setup_irq(eirq, &cpm_error_irqaction))
 190                 printk(KERN_ERR "Could not allocate CPM error IRQ!");
 191
 192         setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
 193
 194 end:
 195         of_node_put(np);
 196         return sirq;
 197 }
 198
 199 void __init cpm_reset(void)
 200 {
 201         sysconf8xx_t __iomem *siu_conf;
 202
 203         mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
 204         if (!mpc8xx_immr) {
 205                 printk(KERN_CRIT "Could not map IMMR\n");
 206                 return;
 207         }
 208
 209         cpmp = &mpc8xx_immr->im_cpm;
 210
 211 #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
 212         /* Perform a reset.
 213         */
 214         out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
 215
 216         /* Wait for it.
 217         */
 218         while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
 219 #endif
 220
 221 #ifdef CONFIG_UCODE_PATCH
 222         cpm_load_patch(cpmp);
 223 #endif
 224
 225         /* Set SDMA Bus Request priority 5.
 226          * On 860T, this also enables FEC priority 6.  I am not sure
 227          * this is what we realy want for some applications, but the
 228          * manual recommends it.
 229          * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
 230          */
 231         siu_conf = immr_map(im_siu_conf);
 232         out_be32(&siu_conf->sc_sdcr, 1);
 233         immr_unmap(siu_conf);
 234
 235 #ifdef CONFIG_PPC_CPM_NEW_BINDING
 236         cpm_muram_init();
 237 #else
 238         /* Reclaim the DP memory for our use. */
 239         m8xx_cpm_dpinit();
 240 #endif
 241 }
 242
 243 static DEFINE_SPINLOCK(cmd_lock);
 244
 245 #define MAX_CR_CMD_LOOPS        10000
 246
 247 int cpm_command(u32 command, u8 opcode)
 248 {
 249         int i, ret;
 250         unsigned long flags;
 251
 252         if (command & 0xffffff0f)
 253                 return -EINVAL;
 254
 255         spin_lock_irqsave(&cmd_lock, flags);
 256
 257         ret = 0;
 258         out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8));
 259         for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
 260                 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
 261                         goto out;
 262
 263         printk(KERN_ERR "%s(): Not able to issue CPM command\n", __FUNCTION__);
 264         ret = -EIO;
 265 out:
 266         spin_unlock_irqrestore(&cmd_lock, flags);
 267         return ret;
 268 }
 269 EXPORT_SYMBOL(cpm_command);
 270
 271 /* We used to do this earlier, but have to postpone as long as possible
 272  * to ensure the kernel VM is now running.
 273  */
 274 static void
 275 alloc_host_memory(void)
 276 {
 277         dma_addr_t      physaddr;
 278
 279         /* Set the host page for allocation.
 280         */
 281         host_buffer = (uint)dma_alloc_coherent(NULL, PAGE_SIZE, &physaddr,
 282                         GFP_KERNEL);
 283         host_end = host_buffer + PAGE_SIZE;
 284 }
 285
 286 /* We also own one page of host buffer space for the allocation of
 287  * UART "fifos" and the like.
 288  */
 289 uint
 290 m8xx_cpm_hostalloc(uint size)
 291 {
 292         uint    retloc;
 293
 294         if (host_buffer == 0)
 295                 alloc_host_memory();
 296
 297         if ((host_buffer + size) >= host_end)
 298                 return(0);
 299
 300         retloc = host_buffer;
 301         host_buffer += size;
 302
 303         return(retloc);
 304 }
 305
 306 /* Set a baud rate generator.  This needs lots of work.  There are
 307  * four BRGs, any of which can be wired to any channel.
 308  * The internal baud rate clock is the system clock divided by 16.
 309  * This assumes the baudrate is 16x oversampled by the uart.
 310  */
 311 #define BRG_INT_CLK             (get_brgfreq())
 312 #define BRG_UART_CLK            (BRG_INT_CLK/16)
 313 #define BRG_UART_CLK_DIV16      (BRG_UART_CLK/16)
 314
 315 void
 316 cpm_setbrg(uint brg, uint rate)
 317 {
 318         u32 __iomem *bp;
 319
 320         /* This is good enough to get SMCs running.....
 321         */
 322         bp = &cpmp->cp_brgc1;
 323         bp += brg;
 324         /* The BRG has a 12-bit counter.  For really slow baud rates (or
 325          * really fast processors), we may have to further divide by 16.
 326          */
 327         if (((BRG_UART_CLK / rate) - 1) < 4096)
 328                 out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
 329         else
 330                 out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
 331                              CPM_BRG_EN | CPM_BRG_DIV16);
 332 }
 333
 334 #ifndef CONFIG_PPC_CPM_NEW_BINDING
 335 /*
 336  * dpalloc / dpfree bits.
 337  */
 338 static spinlock_t cpm_dpmem_lock;
 339 /*
 340  * 16 blocks should be enough to satisfy all requests
 341  * until the memory subsystem goes up...
 342  */
 343 static rh_block_t cpm_boot_dpmem_rh_block[16];
 344 static rh_info_t cpm_dpmem_info;
 345
 346 #define CPM_DPMEM_ALIGNMENT     8
 347 static u8 __iomem *dpram_vbase;
 348 static phys_addr_t dpram_pbase;
 349
 350 static void m8xx_cpm_dpinit(void)
 351 {
 352         spin_lock_init(&cpm_dpmem_lock);
 353
 354         dpram_vbase = cpmp->cp_dpmem;
 355         dpram_pbase = get_immrbase() + offsetof(immap_t, im_cpm.cp_dpmem);
 356
 357         /* Initialize the info header */
 358         rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT,
 359                         sizeof(cpm_boot_dpmem_rh_block) /
 360                         sizeof(cpm_boot_dpmem_rh_block[0]),
 361                         cpm_boot_dpmem_rh_block);
 362
 363         /*
 364          * Attach the usable dpmem area.
 365          * XXX: This is actually crap.  CPM_DATAONLY_BASE and
 366          * CPM_DATAONLY_SIZE are a subset of the available dparm.  It varies
 367          * with the processor and the microcode patches applied / activated.
 368          * But the following should be at least safe.
 369          */
 370         rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
 371 }
 372
 373 /*
 374  * Allocate the requested size worth of DP memory.
 375  * This function returns an offset into the DPRAM area.
 376  * Use cpm_dpram_addr() to get the virtual address of the area.
 377  */
 378 unsigned long cpm_dpalloc(uint size, uint align)
 379 {
 380         unsigned long start;
 381         unsigned long flags;
 382
 383         spin_lock_irqsave(&cpm_dpmem_lock, flags);
 384         cpm_dpmem_info.alignment = align;
 385         start = rh_alloc(&cpm_dpmem_info, size, "commproc");
 386         spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
 387
 388         return (uint)start;
 389 }
 390 EXPORT_SYMBOL(cpm_dpalloc);
 391
 392 int cpm_dpfree(unsigned long offset)
 393 {
 394         int ret;
 395         unsigned long flags;
 396
 397         spin_lock_irqsave(&cpm_dpmem_lock, flags);
 398         ret = rh_free(&cpm_dpmem_info, offset);
 399         spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
 400
 401         return ret;
 402 }
 403 EXPORT_SYMBOL(cpm_dpfree);
 404
 405 unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
 406 {
 407         unsigned long start;
 408         unsigned long flags;
 409
 410         spin_lock_irqsave(&cpm_dpmem_lock, flags);
 411         cpm_dpmem_info.alignment = align;
 412         start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
 413         spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
 414
 415         return start;
 416 }
 417 EXPORT_SYMBOL(cpm_dpalloc_fixed);
 418
 419 void cpm_dpdump(void)
 420 {
 421         rh_dump(&cpm_dpmem_info);
 422 }
 423 EXPORT_SYMBOL(cpm_dpdump);
 424
 425 void *cpm_dpram_addr(unsigned long offset)
 426 {
 427         return (void *)(dpram_vbase + offset);
 428 }
 429 EXPORT_SYMBOL(cpm_dpram_addr);
 430
 431 uint cpm_dpram_phys(u8 *addr)
 432 {
 433         return (dpram_pbase + (uint)(addr - dpram_vbase));
 434 }
 435 EXPORT_SYMBOL(cpm_dpram_phys);
 436 #endif /* !CONFIG_PPC_CPM_NEW_BINDING */
 437
 438 struct cpm_ioport16 {
 439         __be16 dir, par, odr_sor, dat, intr;
 440         __be16 res[3];
 441 };
 442
 443 struct cpm_ioport32 {
 444         __be32 dir, par, sor;
 445 };
 446
 447 static void cpm1_set_pin32(int port, int pin, int flags)
 448 {
 449         struct cpm_ioport32 __iomem *iop;
 450         pin = 1 << (31 - pin);
 451
 452         if (port == CPM_PORTB)
 453                 iop = (struct cpm_ioport32 __iomem *)
 454                       &mpc8xx_immr->im_cpm.cp_pbdir;
 455         else
 456                 iop = (struct cpm_ioport32 __iomem *)
 457                       &mpc8xx_immr->im_cpm.cp_pedir;
 458
 459         if (flags & CPM_PIN_OUTPUT)
 460                 setbits32(&iop->dir, pin);
 461         else
 462                 clrbits32(&iop->dir, pin);
 463
 464         if (!(flags & CPM_PIN_GPIO))
 465                 setbits32(&iop->par, pin);
 466         else
 467                 clrbits32(&iop->par, pin);
 468
 469         if (port == CPM_PORTB) {
 470                 if (flags & CPM_PIN_OPENDRAIN)
 471                         setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
 472                 else
 473                         clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
 474         }
 475
 476         if (port == CPM_PORTE) {
 477                 if (flags & CPM_PIN_SECONDARY)
 478                         setbits32(&iop->sor, pin);
 479                 else
 480                         clrbits32(&iop->sor, pin);
 481
 482                 if (flags & CPM_PIN_OPENDRAIN)
 483                         setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
 484                 else
 485                         clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
 486         }
 487 }
 488
 489 static void cpm1_set_pin16(int port, int pin, int flags)
 490 {
 491         struct cpm_ioport16 __iomem *iop =
 492                 (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
 493
 494         pin = 1 << (15 - pin);
 495
 496         if (port != 0)
 497                 iop += port - 1;
 498
 499         if (flags & CPM_PIN_OUTPUT)
 500                 setbits16(&iop->dir, pin);
 501         else
 502                 clrbits16(&iop->dir, pin);
 503
 504         if (!(flags & CPM_PIN_GPIO))
 505                 setbits16(&iop->par, pin);
 506         else
 507                 clrbits16(&iop->par, pin);
 508
 509         if (port == CPM_PORTA) {
 510                 if (flags & CPM_PIN_OPENDRAIN)
 511                         setbits16(&iop->odr_sor, pin);
 512                 else
 513                         clrbits16(&iop->odr_sor, pin);
 514         }
 515         if (port == CPM_PORTC) {
 516                 if (flags & CPM_PIN_SECONDARY)
 517                         setbits16(&iop->odr_sor, pin);
 518                 else
 519                         clrbits16(&iop->odr_sor, pin);
 520         }
 521 }
 522
 523 void cpm1_set_pin(enum cpm_port port, int pin, int flags)
 524 {
 525         if (port == CPM_PORTB || port == CPM_PORTE)
 526                 cpm1_set_pin32(port, pin, flags);
 527         else
 528                 cpm1_set_pin16(port, pin, flags);
 529 }
 530
 531 int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
 532 {
 533         int shift;
 534         int i, bits = 0;
 535         u32 __iomem *reg;
 536         u32 mask = 7;
 537
 538         u8 clk_map[][3] = {
 539                 {CPM_CLK_SCC1, CPM_BRG1, 0},
 540                 {CPM_CLK_SCC1, CPM_BRG2, 1},
 541                 {CPM_CLK_SCC1, CPM_BRG3, 2},
 542                 {CPM_CLK_SCC1, CPM_BRG4, 3},
 543                 {CPM_CLK_SCC1, CPM_CLK1, 4},
 544                 {CPM_CLK_SCC1, CPM_CLK2, 5},
 545                 {CPM_CLK_SCC1, CPM_CLK3, 6},
 546                 {CPM_CLK_SCC1, CPM_CLK4, 7},
 547
 548                 {CPM_CLK_SCC2, CPM_BRG1, 0},
 549                 {CPM_CLK_SCC2, CPM_BRG2, 1},
 550                 {CPM_CLK_SCC2, CPM_BRG3, 2},
 551                 {CPM_CLK_SCC2, CPM_BRG4, 3},
 552                 {CPM_CLK_SCC2, CPM_CLK1, 4},
 553                 {CPM_CLK_SCC2, CPM_CLK2, 5},
 554                 {CPM_CLK_SCC2, CPM_CLK3, 6},
 555                 {CPM_CLK_SCC2, CPM_CLK4, 7},
 556
 557                 {CPM_CLK_SCC3, CPM_BRG1, 0},
 558                 {CPM_CLK_SCC3, CPM_BRG2, 1},
 559                 {CPM_CLK_SCC3, CPM_BRG3, 2},
 560                 {CPM_CLK_SCC3, CPM_BRG4, 3},
 561                 {CPM_CLK_SCC3, CPM_CLK5, 4},
 562                 {CPM_CLK_SCC3, CPM_CLK6, 5},
 563                 {CPM_CLK_SCC3, CPM_CLK7, 6},
 564                 {CPM_CLK_SCC3, CPM_CLK8, 7},
 565
 566                 {CPM_CLK_SCC4, CPM_BRG1, 0},
 567                 {CPM_CLK_SCC4, CPM_BRG2, 1},
 568                 {CPM_CLK_SCC4, CPM_BRG3, 2},
 569                 {CPM_CLK_SCC4, CPM_BRG4, 3},
 570                 {CPM_CLK_SCC4, CPM_CLK5, 4},
 571                 {CPM_CLK_SCC4, CPM_CLK6, 5},
 572                 {CPM_CLK_SCC4, CPM_CLK7, 6},
 573                 {CPM_CLK_SCC4, CPM_CLK8, 7},
 574
 575                 {CPM_CLK_SMC1, CPM_BRG1, 0},
 576                 {CPM_CLK_SMC1, CPM_BRG2, 1},
 577                 {CPM_CLK_SMC1, CPM_BRG3, 2},
 578                 {CPM_CLK_SMC1, CPM_BRG4, 3},
 579                 {CPM_CLK_SMC1, CPM_CLK1, 4},
 580                 {CPM_CLK_SMC1, CPM_CLK2, 5},
 581                 {CPM_CLK_SMC1, CPM_CLK3, 6},
 582                 {CPM_CLK_SMC1, CPM_CLK4, 7},
 583
 584                 {CPM_CLK_SMC2, CPM_BRG1, 0},
 585                 {CPM_CLK_SMC2, CPM_BRG2, 1},
 586                 {CPM_CLK_SMC2, CPM_BRG3, 2},
 587                 {CPM_CLK_SMC2, CPM_BRG4, 3},
 588                 {CPM_CLK_SMC2, CPM_CLK5, 4},
 589                 {CPM_CLK_SMC2, CPM_CLK6, 5},
 590                 {CPM_CLK_SMC2, CPM_CLK7, 6},
 591                 {CPM_CLK_SMC2, CPM_CLK8, 7},
 592         };
 593
 594         switch (target) {
 595         case CPM_CLK_SCC1:
 596                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 597                 shift = 0;
 598                 break;
 599
 600         case CPM_CLK_SCC2:
 601                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 602                 shift = 8;
 603                 break;
 604
 605         case CPM_CLK_SCC3:
 606                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 607                 shift = 16;
 608                 break;
 609
 610         case CPM_CLK_SCC4:
 611                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 612                 shift = 24;
 613                 break;
 614
 615         case CPM_CLK_SMC1:
 616                 reg = &mpc8xx_immr->im_cpm.cp_simode;
 617                 shift = 12;
 618                 break;
 619
 620         case CPM_CLK_SMC2:
 621                 reg = &mpc8xx_immr->im_cpm.cp_simode;
 622                 shift = 28;
 623                 break;
 624
 625         default:
 626                 printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n");
 627                 return -EINVAL;
 628         }
 629
 630         if (reg == &mpc8xx_immr->im_cpm.cp_sicr && mode == CPM_CLK_RX)
 631                 shift += 3;
 632
 633         for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
 634                 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
 635                         bits = clk_map[i][2];
 636                         break;
 637                 }
 638         }
 639
 640         if (i == ARRAY_SIZE(clk_map)) {
 641                 printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n");
 642                 return -EINVAL;
 643         }
 644
 645         bits <<= shift;
 646         mask <<= shift;
 647         out_be32(reg, (in_be32(reg) & ~mask) | bits);
 648
 649         return 0;
 650 }