arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/crash_dump.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/delay.h>
  19 #include <linux/string.h>
  20 #include <linux/init.h>
  21 #include <linux/bootmem.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/msi.h>
  25 #include <linux/memblock.h>
  26 #include <linux/iommu.h>
  27 #include <linux/rculist.h>
  28 #include <linux/sizes.h>
  29
  30 #include <asm/sections.h>
  31 #include <asm/io.h>
  32 #include <asm/prom.h>
  33 #include <asm/pci-bridge.h>
  34 #include <asm/machdep.h>
  35 #include <asm/msi_bitmap.h>
  36 #include <asm/ppc-pci.h>
  37 #include <asm/opal.h>
  38 #include <asm/iommu.h>
  39 #include <asm/tce.h>
  40 #include <asm/xics.h>
  41 #include <asm/debug.h>
  42 #include <asm/firmware.h>
  43 #include <asm/pnv-pci.h>
  44 #include <asm/mmzone.h>
  45
  46 #include <misc/cxl-base.h>
  47
  48 #include "powernv.h"
  49 #include "pci.h"
  50
  51 /* 256M DMA window, 4K TCE pages, 8 bytes TCE */
  52 #define TCE32_TABLE_SIZE        ((0x10000000 / 0x1000) * 8)
  53
  54 #define POWERNV_IOMMU_DEFAULT_LEVELS    1
  55 #define POWERNV_IOMMU_MAX_LEVELS        5
  56
  57 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
  58
  59 static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
  60                             const char *fmt, ...)
  61 {
  62         struct va_format vaf;
  63         va_list args;
  64         char pfix[32];
  65
  66         va_start(args, fmt);
  67
  68         vaf.fmt = fmt;
  69         vaf.va = &args;
  70
  71         if (pe->flags & PNV_IODA_PE_DEV)
  72                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
  73         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
  74                 sprintf(pfix, "%04x:%02x     ",
  75                         pci_domain_nr(pe->pbus), pe->pbus->number);
  76 #ifdef CONFIG_PCI_IOV
  77         else if (pe->flags & PNV_IODA_PE_VF)
  78                 sprintf(pfix, "%04x:%02x:%2x.%d",
  79                         pci_domain_nr(pe->parent_dev->bus),
  80                         (pe->rid & 0xff00) >> 8,
  81                         PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
  82 #endif /* CONFIG_PCI_IOV*/
  83
  84         printk("%spci %s: [PE# %.3d] %pV",
  85                level, pfix, pe->pe_number, &vaf);
  86
  87         va_end(args);
  88 }
  89
  90 #define pe_err(pe, fmt, ...)                                    \
  91         pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
  92 #define pe_warn(pe, fmt, ...)                                   \
  93         pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
  94 #define pe_info(pe, fmt, ...)                                   \
  95         pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
  96
  97 static bool pnv_iommu_bypass_disabled __read_mostly;
  98
  99 static int __init iommu_setup(char *str)
 100 {
 101         if (!str)
 102                 return -EINVAL;
 103
 104         while (*str) {
 105                 if (!strncmp(str, "nobypass", 8)) {
 106                         pnv_iommu_bypass_disabled = true;
 107                         pr_info("PowerNV: IOMMU bypass window disabled.\n");
 108                         break;
 109                 }
 110                 str += strcspn(str, ",");
 111                 if (*str == ',')
 112                         str++;
 113         }
 114
 115         return 0;
 116 }
 117 early_param("iommu", iommu_setup);
 118
 119 /*
 120  * stdcix is only supposed to be used in hypervisor real mode as per
 121  * the architecture spec
 122  */
 123 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
 124 {
 125         __asm__ __volatile__("stdcix %0,0,%1"
 126                 : : "r" (val), "r" (paddr) : "memory");
 127 }
 128
 129 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags)
 130 {
 131         return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) ==
 132                 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH));
 133 }
 134
 135 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
 136 {
 137         if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) {
 138                 pr_warn("%s: Invalid PE %d on PHB#%x\n",
 139                         __func__, pe_no, phb->hose->global_number);
 140                 return;
 141         }
 142
 143         if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) {
 144                 pr_warn("%s: PE %d was assigned on PHB#%x\n",
 145                         __func__, pe_no, phb->hose->global_number);
 146                 return;
 147         }
 148
 149         phb->ioda.pe_array[pe_no].phb = phb;
 150         phb->ioda.pe_array[pe_no].pe_number = pe_no;
 151 }
 152
 153 static int pnv_ioda_alloc_pe(struct pnv_phb *phb)
 154 {
 155         unsigned long pe;
 156
 157         do {
 158                 pe = find_next_zero_bit(phb->ioda.pe_alloc,
 159                                         phb->ioda.total_pe, 0);
 160                 if (pe >= phb->ioda.total_pe)
 161                         return IODA_INVALID_PE;
 162         } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
 163
 164         phb->ioda.pe_array[pe].phb = phb;
 165         phb->ioda.pe_array[pe].pe_number = pe;
 166         return pe;
 167 }
 168
 169 static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
 170 {
 171         WARN_ON(phb->ioda.pe_array[pe].pdev);
 172
 173         memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
 174         clear_bit(pe, phb->ioda.pe_alloc);
 175 }
 176
 177 /* The default M64 BAR is shared by all PEs */
 178 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
 179 {
 180         const char *desc;
 181         struct resource *r;
 182         s64 rc;
 183
 184         /* Configure the default M64 BAR */
 185         rc = opal_pci_set_phb_mem_window(phb->opal_id,
 186                                          OPAL_M64_WINDOW_TYPE,
 187                                          phb->ioda.m64_bar_idx,
 188                                          phb->ioda.m64_base,
 189                                          0, /* unused */
 190                                          phb->ioda.m64_size);
 191         if (rc != OPAL_SUCCESS) {
 192                 desc = "configuring";
 193                 goto fail;
 194         }
 195
 196         /* Enable the default M64 BAR */
 197         rc = opal_pci_phb_mmio_enable(phb->opal_id,
 198                                       OPAL_M64_WINDOW_TYPE,
 199                                       phb->ioda.m64_bar_idx,
 200                                       OPAL_ENABLE_M64_SPLIT);
 201         if (rc != OPAL_SUCCESS) {
 202                 desc = "enabling";
 203                 goto fail;
 204         }
 205
 206         /* Mark the M64 BAR assigned */
 207         set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc);
 208
 209         /*
 210          * Strip off the segment used by the reserved PE, which is
 211          * expected to be 0 or last one of PE capabicity.
 212          */
 213         r = &phb->hose->mem_resources[1];
 214         if (phb->ioda.reserved_pe == 0)
 215                 r->start += phb->ioda.m64_segsize;
 216         else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1))
 217                 r->end -= phb->ioda.m64_segsize;
 218         else
 219                 pr_warn("  Cannot strip M64 segment for reserved PE#%d\n",
 220                         phb->ioda.reserved_pe);
 221
 222         return 0;
 223
 224 fail:
 225         pr_warn("  Failure %lld %s M64 BAR#%d\n",
 226                 rc, desc, phb->ioda.m64_bar_idx);
 227         opal_pci_phb_mmio_enable(phb->opal_id,
 228                                  OPAL_M64_WINDOW_TYPE,
 229                                  phb->ioda.m64_bar_idx,
 230                                  OPAL_DISABLE_M64);
 231         return -EIO;
 232 }
 233
 234 static void pnv_ioda2_reserve_m64_pe(struct pnv_phb *phb)
 235 {
 236         resource_size_t sgsz = phb->ioda.m64_segsize;
 237         struct pci_dev *pdev;
 238         struct resource *r;
 239         int base, step, i;
 240
 241         /*
 242          * Root bus always has full M64 range and root port has
 243          * M64 range used in reality. So we're checking root port
 244          * instead of root bus.
 245          */
 246         list_for_each_entry(pdev, &phb->hose->bus->devices, bus_list) {
 247                 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
 248                         r = &pdev->resource[PCI_BRIDGE_RESOURCES + i];
 249                         if (!r->parent ||
 250                             !pnv_pci_is_mem_pref_64(r->flags))
 251                                 continue;
 252
 253                         base = (r->start - phb->ioda.m64_base) / sgsz;
 254                         for (step = 0; step < resource_size(r) / sgsz; step++)
 255                                 pnv_ioda_reserve_pe(phb, base + step);
 256                 }
 257         }
 258 }
 259
 260 static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb,
 261                                  struct pci_bus *bus, int all)
 262 {
 263         resource_size_t segsz = phb->ioda.m64_segsize;
 264         struct pci_dev *pdev;
 265         struct resource *r;
 266         struct pnv_ioda_pe *master_pe, *pe;
 267         unsigned long size, *pe_alloc;
 268         bool found;
 269         int start, i, j;
 270
 271         /* Root bus shouldn't use M64 */
 272         if (pci_is_root_bus(bus))
 273                 return IODA_INVALID_PE;
 274
 275         /* We support only one M64 window on each bus */
 276         found = false;
 277         pci_bus_for_each_resource(bus, r, i) {
 278                 if (r && r->parent &&
 279                     pnv_pci_is_mem_pref_64(r->flags)) {
 280                         found = true;
 281                         break;
 282                 }
 283         }
 284
 285         /* No M64 window found ? */
 286         if (!found)
 287                 return IODA_INVALID_PE;
 288
 289         /* Allocate bitmap */
 290         size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
 291         pe_alloc = kzalloc(size, GFP_KERNEL);
 292         if (!pe_alloc) {
 293                 pr_warn("%s: Out of memory !\n",
 294                         __func__);
 295                 return IODA_INVALID_PE;
 296         }
 297
 298         /*
 299          * Figure out reserved PE numbers by the PE
 300          * the its child PEs.
 301          */
 302         start = (r->start - phb->ioda.m64_base) / segsz;
 303         for (i = 0; i < resource_size(r) / segsz; i++)
 304                 set_bit(start + i, pe_alloc);
 305
 306         if (all)
 307                 goto done;
 308
 309         /*
 310          * If the PE doesn't cover all subordinate buses,
 311          * we need subtract from reserved PEs for children.
 312          */
 313         list_for_each_entry(pdev, &bus->devices, bus_list) {
 314                 if (!pdev->subordinate)
 315                         continue;
 316
 317                 pci_bus_for_each_resource(pdev->subordinate, r, i) {
 318                         if (!r || !r->parent ||
 319                             !pnv_pci_is_mem_pref_64(r->flags))
 320                                 continue;
 321
 322                         start = (r->start - phb->ioda.m64_base) / segsz;
 323                         for (j = 0; j < resource_size(r) / segsz ; j++)
 324                                 clear_bit(start + j, pe_alloc);
 325                 }
 326         }
 327
 328         /*
 329          * the current bus might not own M64 window and that's all
 330          * contributed by its child buses. For the case, we needn't
 331          * pick M64 dependent PE#.
 332          */
 333         if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) {
 334                 kfree(pe_alloc);
 335                 return IODA_INVALID_PE;
 336         }
 337
 338         /*
 339          * Figure out the master PE and put all slave PEs to master
 340          * PE's list to form compound PE.
 341          */
 342 done:
 343         master_pe = NULL;
 344         i = -1;
 345         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) <
 346                 phb->ioda.total_pe) {
 347                 pe = &phb->ioda.pe_array[i];
 348
 349                 if (!master_pe) {
 350                         pe->flags |= PNV_IODA_PE_MASTER;
 351                         INIT_LIST_HEAD(&pe->slaves);
 352                         master_pe = pe;
 353                 } else {
 354                         pe->flags |= PNV_IODA_PE_SLAVE;
 355                         pe->master = master_pe;
 356                         list_add_tail(&pe->list, &master_pe->slaves);
 357                 }
 358         }
 359
 360         kfree(pe_alloc);
 361         return master_pe->pe_number;
 362 }
 363
 364 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
 365 {
 366         struct pci_controller *hose = phb->hose;
 367         struct device_node *dn = hose->dn;
 368         struct resource *res;
 369         const u32 *r;
 370         u64 pci_addr;
 371
 372         /* FIXME: Support M64 for P7IOC */
 373         if (phb->type != PNV_PHB_IODA2) {
 374                 pr_info("  Not support M64 window\n");
 375                 return;
 376         }
 377
 378         if (!firmware_has_feature(FW_FEATURE_OPALv3)) {
 379                 pr_info("  Firmware too old to support M64 window\n");
 380                 return;
 381         }
 382
 383         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
 384         if (!r) {
 385                 pr_info("  No <ibm,opal-m64-window> on %s\n",
 386                         dn->full_name);
 387                 return;
 388         }
 389
 390         res = &hose->mem_resources[1];
 391         res->start = of_translate_address(dn, r + 2);
 392         res->end = res->start + of_read_number(r + 4, 2) - 1;
 393         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 394         pci_addr = of_read_number(r, 2);
 395         hose->mem_offset[1] = res->start - pci_addr;
 396
 397         phb->ioda.m64_size = resource_size(res);
 398         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe;
 399         phb->ioda.m64_base = pci_addr;
 400
 401         pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
 402                         res->start, res->end, pci_addr);
 403
 404         /* Use last M64 BAR to cover M64 window */
 405         phb->ioda.m64_bar_idx = 15;
 406         phb->init_m64 = pnv_ioda2_init_m64;
 407         phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe;
 408         phb->pick_m64_pe = pnv_ioda2_pick_m64_pe;
 409 }
 410
 411 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
 412 {
 413         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
 414         struct pnv_ioda_pe *slave;
 415         s64 rc;
 416
 417         /* Fetch master PE */
 418         if (pe->flags & PNV_IODA_PE_SLAVE) {
 419                 pe = pe->master;
 420                 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
 421                         return;
 422
 423                 pe_no = pe->pe_number;
 424         }
 425
 426         /* Freeze master PE */
 427         rc = opal_pci_eeh_freeze_set(phb->opal_id,
 428                                      pe_no,
 429                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
 430         if (rc != OPAL_SUCCESS) {
 431                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 432                         __func__, rc, phb->hose->global_number, pe_no);
 433                 return;
 434         }
 435
 436         /* Freeze slave PEs */
 437         if (!(pe->flags & PNV_IODA_PE_MASTER))
 438                 return;
 439
 440         list_for_each_entry(slave, &pe->slaves, list) {
 441                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
 442                                              slave->pe_number,
 443                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
 444                 if (rc != OPAL_SUCCESS)
 445                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 446                                 __func__, rc, phb->hose->global_number,
 447                                 slave->pe_number);
 448         }
 449 }
 450
 451 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
 452 {
 453         struct pnv_ioda_pe *pe, *slave;
 454         s64 rc;
 455
 456         /* Find master PE */
 457         pe = &phb->ioda.pe_array[pe_no];
 458         if (pe->flags & PNV_IODA_PE_SLAVE) {
 459                 pe = pe->master;
 460                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 461                 pe_no = pe->pe_number;
 462         }
 463
 464         /* Clear frozen state for master PE */
 465         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
 466         if (rc != OPAL_SUCCESS) {
 467                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 468                         __func__, rc, opt, phb->hose->global_number, pe_no);
 469                 return -EIO;
 470         }
 471
 472         if (!(pe->flags & PNV_IODA_PE_MASTER))
 473                 return 0;
 474
 475         /* Clear frozen state for slave PEs */
 476         list_for_each_entry(slave, &pe->slaves, list) {
 477                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
 478                                              slave->pe_number,
 479                                              opt);
 480                 if (rc != OPAL_SUCCESS) {
 481                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 482                                 __func__, rc, opt, phb->hose->global_number,
 483                                 slave->pe_number);
 484                         return -EIO;
 485                 }
 486         }
 487
 488         return 0;
 489 }
 490
 491 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
 492 {
 493         struct pnv_ioda_pe *slave, *pe;
 494         u8 fstate, state;
 495         __be16 pcierr;
 496         s64 rc;
 497
 498         /* Sanity check on PE number */
 499         if (pe_no < 0 || pe_no >= phb->ioda.total_pe)
 500                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
 501
 502         /*
 503          * Fetch the master PE and the PE instance might be
 504          * not initialized yet.
 505          */
 506         pe = &phb->ioda.pe_array[pe_no];
 507         if (pe->flags & PNV_IODA_PE_SLAVE) {
 508                 pe = pe->master;
 509                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 510                 pe_no = pe->pe_number;
 511         }
 512
 513         /* Check the master PE */
 514         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 515                                         &state, &pcierr, NULL);
 516         if (rc != OPAL_SUCCESS) {
 517                 pr_warn("%s: Failure %lld getting "
 518                         "PHB#%x-PE#%x state\n",
 519                         __func__, rc,
 520                         phb->hose->global_number, pe_no);
 521                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 522         }
 523
 524         /* Check the slave PE */
 525         if (!(pe->flags & PNV_IODA_PE_MASTER))
 526                 return state;
 527
 528         list_for_each_entry(slave, &pe->slaves, list) {
 529                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 530                                                 slave->pe_number,
 531                                                 &fstate,
 532                                                 &pcierr,
 533                                                 NULL);
 534                 if (rc != OPAL_SUCCESS) {
 535                         pr_warn("%s: Failure %lld getting "
 536                                 "PHB#%x-PE#%x state\n",
 537                                 __func__, rc,
 538                                 phb->hose->global_number, slave->pe_number);
 539                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 540                 }
 541
 542                 /*
 543                  * Override the result based on the ascending
 544                  * priority.
 545                  */
 546                 if (fstate > state)
 547                         state = fstate;
 548         }
 549
 550         return state;
 551 }
 552
 553 /* Currently those 2 are only used when MSIs are enabled, this will change
 554  * but in the meantime, we need to protect them to avoid warnings
 555  */
 556 #ifdef CONFIG_PCI_MSI
 557 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 558 {
 559         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 560         struct pnv_phb *phb = hose->private_data;
 561         struct pci_dn *pdn = pci_get_pdn(dev);
 562
 563         if (!pdn)
 564                 return NULL;
 565         if (pdn->pe_number == IODA_INVALID_PE)
 566                 return NULL;
 567         return &phb->ioda.pe_array[pdn->pe_number];
 568 }
 569 #endif /* CONFIG_PCI_MSI */
 570
 571 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
 572                                   struct pnv_ioda_pe *parent,
 573                                   struct pnv_ioda_pe *child,
 574                                   bool is_add)
 575 {
 576         const char *desc = is_add ? "adding" : "removing";
 577         uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
 578                               OPAL_REMOVE_PE_FROM_DOMAIN;
 579         struct pnv_ioda_pe *slave;
 580         long rc;
 581
 582         /* Parent PE affects child PE */
 583         rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 584                                 child->pe_number, op);
 585         if (rc != OPAL_SUCCESS) {
 586                 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
 587                         rc, desc);
 588                 return -ENXIO;
 589         }
 590
 591         if (!(child->flags & PNV_IODA_PE_MASTER))
 592                 return 0;
 593
 594         /* Compound case: parent PE affects slave PEs */
 595         list_for_each_entry(slave, &child->slaves, list) {
 596                 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 597                                         slave->pe_number, op);
 598                 if (rc != OPAL_SUCCESS) {
 599                         pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
 600                                 rc, desc);
 601                         return -ENXIO;
 602                 }
 603         }
 604
 605         return 0;
 606 }
 607
 608 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
 609                               struct pnv_ioda_pe *pe,
 610                               bool is_add)
 611 {
 612         struct pnv_ioda_pe *slave;
 613         struct pci_dev *pdev = NULL;
 614         int ret;
 615
 616         /*
 617          * Clear PE frozen state. If it's master PE, we need
 618          * clear slave PE frozen state as well.
 619          */
 620         if (is_add) {
 621                 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 622                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 623                 if (pe->flags & PNV_IODA_PE_MASTER) {
 624                         list_for_each_entry(slave, &pe->slaves, list)
 625                                 opal_pci_eeh_freeze_clear(phb->opal_id,
 626                                                           slave->pe_number,
 627                                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 628                 }
 629         }
 630
 631         /*
 632          * Associate PE in PELT. We need add the PE into the
 633          * corresponding PELT-V as well. Otherwise, the error
 634          * originated from the PE might contribute to other
 635          * PEs.
 636          */
 637         ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
 638         if (ret)
 639                 return ret;
 640
 641         /* For compound PEs, any one affects all of them */
 642         if (pe->flags & PNV_IODA_PE_MASTER) {
 643                 list_for_each_entry(slave, &pe->slaves, list) {
 644                         ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
 645                         if (ret)
 646                                 return ret;
 647                 }
 648         }
 649
 650         if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
 651                 pdev = pe->pbus->self;
 652         else if (pe->flags & PNV_IODA_PE_DEV)
 653                 pdev = pe->pdev->bus->self;
 654 #ifdef CONFIG_PCI_IOV
 655         else if (pe->flags & PNV_IODA_PE_VF)
 656                 pdev = pe->parent_dev->bus->self;
 657 #endif /* CONFIG_PCI_IOV */
 658         while (pdev) {
 659                 struct pci_dn *pdn = pci_get_pdn(pdev);
 660                 struct pnv_ioda_pe *parent;
 661
 662                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 663                         parent = &phb->ioda.pe_array[pdn->pe_number];
 664                         ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
 665                         if (ret)
 666                                 return ret;
 667                 }
 668
 669                 pdev = pdev->bus->self;
 670         }
 671
 672         return 0;
 673 }
 674
 675 #ifdef CONFIG_PCI_IOV
 676 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 677 {
 678         struct pci_dev *parent;
 679         uint8_t bcomp, dcomp, fcomp;
 680         int64_t rc;
 681         long rid_end, rid;
 682
 683         /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
 684         if (pe->pbus) {
 685                 int count;
 686
 687                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 688                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 689                 parent = pe->pbus->self;
 690                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 691                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 692                 else
 693                         count = 1;
 694
 695                 switch(count) {
 696                 case  1: bcomp = OpalPciBusAll;         break;
 697                 case  2: bcomp = OpalPciBus7Bits;       break;
 698                 case  4: bcomp = OpalPciBus6Bits;       break;
 699                 case  8: bcomp = OpalPciBus5Bits;       break;
 700                 case 16: bcomp = OpalPciBus4Bits;       break;
 701                 case 32: bcomp = OpalPciBus3Bits;       break;
 702                 default:
 703                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 704                                 count);
 705                         /* Do an exact match only */
 706                         bcomp = OpalPciBusAll;
 707                 }
 708                 rid_end = pe->rid + (count << 8);
 709         } else {
 710                 if (pe->flags & PNV_IODA_PE_VF)
 711                         parent = pe->parent_dev;
 712                 else
 713                         parent = pe->pdev->bus->self;
 714                 bcomp = OpalPciBusAll;
 715                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 716                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 717                 rid_end = pe->rid + 1;
 718         }
 719
 720         /* Clear the reverse map */
 721         for (rid = pe->rid; rid < rid_end; rid++)
 722                 phb->ioda.pe_rmap[rid] = 0;
 723
 724         /* Release from all parents PELT-V */
 725         while (parent) {
 726                 struct pci_dn *pdn = pci_get_pdn(parent);
 727                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 728                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 729                                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 730                         /* XXX What to do in case of error ? */
 731                 }
 732                 parent = parent->bus->self;
 733         }
 734
 735         opal_pci_eeh_freeze_set(phb->opal_id, pe->pe_number,
 736                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 737
 738         /* Disassociate PE in PELT */
 739         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 740                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 741         if (rc)
 742                 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
 743         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 744                              bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
 745         if (rc)
 746                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 747
 748         pe->pbus = NULL;
 749         pe->pdev = NULL;
 750         pe->parent_dev = NULL;
 751
 752         return 0;
 753 }
 754 #endif /* CONFIG_PCI_IOV */
 755
 756 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 757 {
 758         struct pci_dev *parent;
 759         uint8_t bcomp, dcomp, fcomp;
 760         long rc, rid_end, rid;
 761
 762         /* Bus validation ? */
 763         if (pe->pbus) {
 764                 int count;
 765
 766                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 767                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 768                 parent = pe->pbus->self;
 769                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 770                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 771                 else
 772                         count = 1;
 773
 774                 switch(count) {
 775                 case  1: bcomp = OpalPciBusAll;         break;
 776                 case  2: bcomp = OpalPciBus7Bits;       break;
 777                 case  4: bcomp = OpalPciBus6Bits;       break;
 778                 case  8: bcomp = OpalPciBus5Bits;       break;
 779                 case 16: bcomp = OpalPciBus4Bits;       break;
 780                 case 32: bcomp = OpalPciBus3Bits;       break;
 781                 default:
 782                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 783                                 count);
 784                         /* Do an exact match only */
 785                         bcomp = OpalPciBusAll;
 786                 }
 787                 rid_end = pe->rid + (count << 8);
 788         } else {
 789 #ifdef CONFIG_PCI_IOV
 790                 if (pe->flags & PNV_IODA_PE_VF)
 791                         parent = pe->parent_dev;
 792                 else
 793 #endif /* CONFIG_PCI_IOV */
 794                         parent = pe->pdev->bus->self;
 795                 bcomp = OpalPciBusAll;
 796                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 797                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 798                 rid_end = pe->rid + 1;
 799         }
 800
 801         /*
 802          * Associate PE in PELT. We need add the PE into the
 803          * corresponding PELT-V as well. Otherwise, the error
 804          * originated from the PE might contribute to other
 805          * PEs.
 806          */
 807         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 808                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 809         if (rc) {
 810                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 811                 return -ENXIO;
 812         }
 813
 814         /* Configure PELTV */
 815         pnv_ioda_set_peltv(phb, pe, true);
 816
 817         /* Setup reverse map */
 818         for (rid = pe->rid; rid < rid_end; rid++)
 819                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 820
 821         /* Setup one MVTs on IODA1 */
 822         if (phb->type != PNV_PHB_IODA1) {
 823                 pe->mve_number = 0;
 824                 goto out;
 825         }
 826
 827         pe->mve_number = pe->pe_number;
 828         rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
 829         if (rc != OPAL_SUCCESS) {
 830                 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
 831                        rc, pe->mve_number);
 832                 pe->mve_number = -1;
 833         } else {
 834                 rc = opal_pci_set_mve_enable(phb->opal_id,
 835                                              pe->mve_number, OPAL_ENABLE_MVE);
 836                 if (rc) {
 837                         pe_err(pe, "OPAL error %ld enabling MVE %d\n",
 838                                rc, pe->mve_number);
 839                         pe->mve_number = -1;
 840                 }
 841         }
 842
 843 out:
 844         return 0;
 845 }
 846
 847 static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
 848                                        struct pnv_ioda_pe *pe)
 849 {
 850         struct pnv_ioda_pe *lpe;
 851
 852         list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) {
 853                 if (lpe->dma_weight < pe->dma_weight) {
 854                         list_add_tail(&pe->dma_link, &lpe->dma_link);
 855                         return;
 856                 }
 857         }
 858         list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list);
 859 }
 860
 861 static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
 862 {
 863         /* This is quite simplistic. The "base" weight of a device
 864          * is 10. 0 means no DMA is to be accounted for it.
 865          */
 866
 867         /* If it's a bridge, no DMA */
 868         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
 869                 return 0;
 870
 871         /* Reduce the weight of slow USB controllers */
 872         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
 873             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
 874             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
 875                 return 3;
 876
 877         /* Increase the weight of RAID (includes Obsidian) */
 878         if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
 879                 return 15;
 880
 881         /* Default */
 882         return 10;
 883 }
 884
 885 #ifdef CONFIG_PCI_IOV
 886 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
 887 {
 888         struct pci_dn *pdn = pci_get_pdn(dev);
 889         int i;
 890         struct resource *res, res2;
 891         resource_size_t size;
 892         u16 num_vfs;
 893
 894         if (!dev->is_physfn)
 895                 return -EINVAL;
 896
 897         /*
 898          * "offset" is in VFs.  The M64 windows are sized so that when they
 899          * are segmented, each segment is the same size as the IOV BAR.
 900          * Each segment is in a separate PE, and the high order bits of the
 901          * address are the PE number.  Therefore, each VF's BAR is in a
 902          * separate PE, and changing the IOV BAR start address changes the
 903          * range of PEs the VFs are in.
 904          */
 905         num_vfs = pdn->num_vfs;
 906         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 907                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 908                 if (!res->flags || !res->parent)
 909                         continue;
 910
 911                 if (!pnv_pci_is_mem_pref_64(res->flags))
 912                         continue;
 913
 914                 /*
 915                  * The actual IOV BAR range is determined by the start address
 916                  * and the actual size for num_vfs VFs BAR.  This check is to
 917                  * make sure that after shifting, the range will not overlap
 918                  * with another device.
 919                  */
 920                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 921                 res2.flags = res->flags;
 922                 res2.start = res->start + (size * offset);
 923                 res2.end = res2.start + (size * num_vfs) - 1;
 924
 925                 if (res2.end > res->end) {
 926                         dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
 927                                 i, &res2, res, num_vfs, offset);
 928                         return -EBUSY;
 929                 }
 930         }
 931
 932         /*
 933          * After doing so, there would be a "hole" in the /proc/iomem when
 934          * offset is a positive value. It looks like the device return some
 935          * mmio back to the system, which actually no one could use it.
 936          */
 937         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 938                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 939                 if (!res->flags || !res->parent)
 940                         continue;
 941
 942                 if (!pnv_pci_is_mem_pref_64(res->flags))
 943                         continue;
 944
 945                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 946                 res2 = *res;
 947                 res->start += size * offset;
 948
 949                 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (enabling %d VFs shifted by %d)\n",
 950                          i, &res2, res, num_vfs, offset);
 951                 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
 952         }
 953         return 0;
 954 }
 955 #endif /* CONFIG_PCI_IOV */
 956
 957 #if 0
 958 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
 959 {
 960         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 961         struct pnv_phb *phb = hose->private_data;
 962         struct pci_dn *pdn = pci_get_pdn(dev);
 963         struct pnv_ioda_pe *pe;
 964         int pe_num;
 965
 966         if (!pdn) {
 967                 pr_err("%s: Device tree node not associated properly\n",
 968                            pci_name(dev));
 969                 return NULL;
 970         }
 971         if (pdn->pe_number != IODA_INVALID_PE)
 972                 return NULL;
 973
 974         /* PE#0 has been pre-set */
 975         if (dev->bus->number == 0)
 976                 pe_num = 0;
 977         else
 978                 pe_num = pnv_ioda_alloc_pe(phb);
 979         if (pe_num == IODA_INVALID_PE) {
 980                 pr_warning("%s: Not enough PE# available, disabling device\n",
 981                            pci_name(dev));
 982                 return NULL;
 983         }
 984
 985         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
 986          * pointer in the PE data structure, both should be destroyed at the
 987          * same time. However, this needs to be looked at more closely again
 988          * once we actually start removing things (Hotplug, SR-IOV, ...)
 989          *
 990          * At some point we want to remove the PDN completely anyways
 991          */
 992         pe = &phb->ioda.pe_array[pe_num];
 993         pci_dev_get(dev);
 994         pdn->pcidev = dev;
 995         pdn->pe_number = pe_num;
 996         pe->pdev = dev;
 997         pe->pbus = NULL;
 998         pe->tce32_seg = -1;
 999         pe->mve_number = -1;
1000         pe->rid = dev->bus->number << 8 | pdn->devfn;
1001
1002         pe_info(pe, "Associated device to PE\n");
1003
1004         if (pnv_ioda_configure_pe(phb, pe)) {
1005                 /* XXX What do we do here ? */
1006                 if (pe_num)
1007                         pnv_ioda_free_pe(phb, pe_num);
1008                 pdn->pe_number = IODA_INVALID_PE;
1009                 pe->pdev = NULL;
1010                 pci_dev_put(dev);
1011                 return NULL;
1012         }
1013
1014         /* Assign a DMA weight to the device */
1015         pe->dma_weight = pnv_ioda_dma_weight(dev);
1016         if (pe->dma_weight != 0) {
1017                 phb->ioda.dma_weight += pe->dma_weight;
1018                 phb->ioda.dma_pe_count++;
1019         }
1020
1021         /* Link the PE */
1022         pnv_ioda_link_pe_by_weight(phb, pe);
1023
1024         return pe;
1025 }
1026 #endif /* Useful for SRIOV case */
1027
1028 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1029 {
1030         struct pci_dev *dev;
1031
1032         list_for_each_entry(dev, &bus->devices, bus_list) {
1033                 struct pci_dn *pdn = pci_get_pdn(dev);
1034
1035                 if (pdn == NULL) {
1036                         pr_warn("%s: No device node associated with device !\n",
1037                                 pci_name(dev));
1038                         continue;
1039                 }
1040                 pdn->pe_number = pe->pe_number;
1041                 pe->dma_weight += pnv_ioda_dma_weight(dev);
1042                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1043                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
1044         }
1045 }
1046
1047 /*
1048  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1049  * single PCI bus. Another one that contains the primary PCI bus and its
1050  * subordinate PCI devices and buses. The second type of PE is normally
1051  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1052  */
1053 static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all)
1054 {
1055         struct pci_controller *hose = pci_bus_to_host(bus);
1056         struct pnv_phb *phb = hose->private_data;
1057         struct pnv_ioda_pe *pe;
1058         int pe_num = IODA_INVALID_PE;
1059
1060         /* Check if PE is determined by M64 */
1061         if (phb->pick_m64_pe)
1062                 pe_num = phb->pick_m64_pe(phb, bus, all);
1063
1064         /* The PE number isn't pinned by M64 */
1065         if (pe_num == IODA_INVALID_PE)
1066                 pe_num = pnv_ioda_alloc_pe(phb);
1067
1068         if (pe_num == IODA_INVALID_PE) {
1069                 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1070                         __func__, pci_domain_nr(bus), bus->number);
1071                 return;
1072         }
1073
1074         pe = &phb->ioda.pe_array[pe_num];
1075         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1076         pe->pbus = bus;
1077         pe->pdev = NULL;
1078         pe->tce32_seg = -1;
1079         pe->mve_number = -1;
1080         pe->rid = bus->busn_res.start << 8;
1081         pe->dma_weight = 0;
1082
1083         if (all)
1084                 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1085                         bus->busn_res.start, bus->busn_res.end, pe_num);
1086         else
1087                 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1088                         bus->busn_res.start, pe_num);
1089
1090         if (pnv_ioda_configure_pe(phb, pe)) {
1091                 /* XXX What do we do here ? */
1092                 if (pe_num)
1093                         pnv_ioda_free_pe(phb, pe_num);
1094                 pe->pbus = NULL;
1095                 return;
1096         }
1097
1098         /* Associate it with all child devices */
1099         pnv_ioda_setup_same_PE(bus, pe);
1100
1101         /* Put PE to the list */
1102         list_add_tail(&pe->list, &phb->ioda.pe_list);
1103
1104         /* Account for one DMA PE if at least one DMA capable device exist
1105          * below the bridge
1106          */
1107         if (pe->dma_weight != 0) {
1108                 phb->ioda.dma_weight += pe->dma_weight;
1109                 phb->ioda.dma_pe_count++;
1110         }
1111
1112         /* Link the PE */
1113         pnv_ioda_link_pe_by_weight(phb, pe);
1114 }
1115
1116 static void pnv_ioda_setup_PEs(struct pci_bus *bus)
1117 {
1118         struct pci_dev *dev;
1119
1120         pnv_ioda_setup_bus_PE(bus, 0);
1121
1122         list_for_each_entry(dev, &bus->devices, bus_list) {
1123                 if (dev->subordinate) {
1124                         if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
1125                                 pnv_ioda_setup_bus_PE(dev->subordinate, 1);
1126                         else
1127                                 pnv_ioda_setup_PEs(dev->subordinate);
1128                 }
1129         }
1130 }
1131
1132 /*
1133  * Configure PEs so that the downstream PCI buses and devices
1134  * could have their associated PE#. Unfortunately, we didn't
1135  * figure out the way to identify the PLX bridge yet. So we
1136  * simply put the PCI bus and the subordinate behind the root
1137  * port to PE# here. The game rule here is expected to be changed
1138  * as soon as we can detected PLX bridge correctly.
1139  */
1140 static void pnv_pci_ioda_setup_PEs(void)
1141 {
1142         struct pci_controller *hose, *tmp;
1143         struct pnv_phb *phb;
1144
1145         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1146                 phb = hose->private_data;
1147
1148                 /* M64 layout might affect PE allocation */
1149                 if (phb->reserve_m64_pe)
1150                         phb->reserve_m64_pe(phb);
1151
1152                 pnv_ioda_setup_PEs(hose->bus);
1153         }
1154 }
1155
1156 #ifdef CONFIG_PCI_IOV
1157 static int pnv_pci_vf_release_m64(struct pci_dev *pdev)
1158 {
1159         struct pci_bus        *bus;
1160         struct pci_controller *hose;
1161         struct pnv_phb        *phb;
1162         struct pci_dn         *pdn;
1163         int                    i, j;
1164
1165         bus = pdev->bus;
1166         hose = pci_bus_to_host(bus);
1167         phb = hose->private_data;
1168         pdn = pci_get_pdn(pdev);
1169
1170         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1171                 for (j = 0; j < M64_PER_IOV; j++) {
1172                         if (pdn->m64_wins[i][j] == IODA_INVALID_M64)
1173                                 continue;
1174                         opal_pci_phb_mmio_enable(phb->opal_id,
1175                                 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 0);
1176                         clear_bit(pdn->m64_wins[i][j], &phb->ioda.m64_bar_alloc);
1177                         pdn->m64_wins[i][j] = IODA_INVALID_M64;
1178                 }
1179
1180         return 0;
1181 }
1182
1183 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1184 {
1185         struct pci_bus        *bus;
1186         struct pci_controller *hose;
1187         struct pnv_phb        *phb;
1188         struct pci_dn         *pdn;
1189         unsigned int           win;
1190         struct resource       *res;
1191         int                    i, j;
1192         int64_t                rc;
1193         int                    total_vfs;
1194         resource_size_t        size, start;
1195         int                    pe_num;
1196         int                    vf_groups;
1197         int                    vf_per_group;
1198
1199         bus = pdev->bus;
1200         hose = pci_bus_to_host(bus);
1201         phb = hose->private_data;
1202         pdn = pci_get_pdn(pdev);
1203         total_vfs = pci_sriov_get_totalvfs(pdev);
1204
1205         /* Initialize the m64_wins to IODA_INVALID_M64 */
1206         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1207                 for (j = 0; j < M64_PER_IOV; j++)
1208                         pdn->m64_wins[i][j] = IODA_INVALID_M64;
1209
1210         if (pdn->m64_per_iov == M64_PER_IOV) {
1211                 vf_groups = (num_vfs <= M64_PER_IOV) ? num_vfs: M64_PER_IOV;
1212                 vf_per_group = (num_vfs <= M64_PER_IOV)? 1:
1213                         roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1214         } else {
1215                 vf_groups = 1;
1216                 vf_per_group = 1;
1217         }
1218
1219         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1220                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1221                 if (!res->flags || !res->parent)
1222                         continue;
1223
1224                 if (!pnv_pci_is_mem_pref_64(res->flags))
1225                         continue;
1226
1227                 for (j = 0; j < vf_groups; j++) {
1228                         do {
1229                                 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1230                                                 phb->ioda.m64_bar_idx + 1, 0);
1231
1232                                 if (win >= phb->ioda.m64_bar_idx + 1)
1233                                         goto m64_failed;
1234                         } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1235
1236                         pdn->m64_wins[i][j] = win;
1237
1238                         if (pdn->m64_per_iov == M64_PER_IOV) {
1239                                 size = pci_iov_resource_size(pdev,
1240                                                         PCI_IOV_RESOURCES + i);
1241                                 size = size * vf_per_group;
1242                                 start = res->start + size * j;
1243                         } else {
1244                                 size = resource_size(res);
1245                                 start = res->start;
1246                         }
1247
1248                         /* Map the M64 here */
1249                         if (pdn->m64_per_iov == M64_PER_IOV) {
1250                                 pe_num = pdn->offset + j;
1251                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1252                                                 pe_num, OPAL_M64_WINDOW_TYPE,
1253                                                 pdn->m64_wins[i][j], 0);
1254                         }
1255
1256                         rc = opal_pci_set_phb_mem_window(phb->opal_id,
1257                                                  OPAL_M64_WINDOW_TYPE,
1258                                                  pdn->m64_wins[i][j],
1259                                                  start,
1260                                                  0, /* unused */
1261                                                  size);
1262
1263
1264                         if (rc != OPAL_SUCCESS) {
1265                                 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1266                                         win, rc);
1267                                 goto m64_failed;
1268                         }
1269
1270                         if (pdn->m64_per_iov == M64_PER_IOV)
1271                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1272                                      OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 2);
1273                         else
1274                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1275                                      OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 1);
1276
1277                         if (rc != OPAL_SUCCESS) {
1278                                 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1279                                         win, rc);
1280                                 goto m64_failed;
1281                         }
1282                 }
1283         }
1284         return 0;
1285
1286 m64_failed:
1287         pnv_pci_vf_release_m64(pdev);
1288         return -EBUSY;
1289 }
1290
1291 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1292 {
1293         struct pci_bus        *bus;
1294         struct pci_controller *hose;
1295         struct pnv_phb        *phb;
1296         struct iommu_table    *tbl;
1297         unsigned long         addr;
1298         int64_t               rc;
1299
1300         bus = dev->bus;
1301         hose = pci_bus_to_host(bus);
1302         phb = hose->private_data;
1303         tbl = pe->table_group.tables[0];
1304         addr = tbl->it_base;
1305
1306         opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
1307                                    pe->pe_number << 1, 1, __pa(addr),
1308                                    0, 0x1000);
1309
1310         rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1311                                         pe->pe_number,
1312                                         (pe->pe_number << 1) + 1,
1313                                         pe->tce_bypass_base,
1314                                         0);
1315         if (rc)
1316                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1317
1318         pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
1319         if (pe->table_group.group) {
1320                 iommu_group_put(pe->table_group.group);
1321                 BUG_ON(pe->table_group.group);
1322         }
1323         pnv_pci_ioda2_table_free_pages(tbl);
1324         iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
1325 }
1326
1327 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1328 {
1329         struct pci_bus        *bus;
1330         struct pci_controller *hose;
1331         struct pnv_phb        *phb;
1332         struct pnv_ioda_pe    *pe, *pe_n;
1333         struct pci_dn         *pdn;
1334         u16                    vf_index;
1335         int64_t                rc;
1336
1337         bus = pdev->bus;
1338         hose = pci_bus_to_host(bus);
1339         phb = hose->private_data;
1340         pdn = pci_get_pdn(pdev);
1341
1342         if (!pdev->is_physfn)
1343                 return;
1344
1345         if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) {
1346                 int   vf_group;
1347                 int   vf_per_group;
1348                 int   vf_index1;
1349
1350                 vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1351
1352                 for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++)
1353                         for (vf_index = vf_group * vf_per_group;
1354                                 vf_index < (vf_group + 1) * vf_per_group &&
1355                                 vf_index < num_vfs;
1356                                 vf_index++)
1357                                 for (vf_index1 = vf_group * vf_per_group;
1358                                         vf_index1 < (vf_group + 1) * vf_per_group &&
1359                                         vf_index1 < num_vfs;
1360                                         vf_index1++){
1361
1362                                         rc = opal_pci_set_peltv(phb->opal_id,
1363                                                 pdn->offset + vf_index,
1364                                                 pdn->offset + vf_index1,
1365                                                 OPAL_REMOVE_PE_FROM_DOMAIN);
1366
1367                                         if (rc)
1368                                             dev_warn(&pdev->dev, "%s: Failed to unlink same group PE#%d(%lld)\n",
1369                                                 __func__,
1370                                                 pdn->offset + vf_index1, rc);
1371                                 }
1372         }
1373
1374         list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1375                 if (pe->parent_dev != pdev)
1376                         continue;
1377
1378                 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1379
1380                 /* Remove from list */
1381                 mutex_lock(&phb->ioda.pe_list_mutex);
1382                 list_del(&pe->list);
1383                 mutex_unlock(&phb->ioda.pe_list_mutex);
1384
1385                 pnv_ioda_deconfigure_pe(phb, pe);
1386
1387                 pnv_ioda_free_pe(phb, pe->pe_number);
1388         }
1389 }
1390
1391 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1392 {
1393         struct pci_bus        *bus;
1394         struct pci_controller *hose;
1395         struct pnv_phb        *phb;
1396         struct pci_dn         *pdn;
1397         struct pci_sriov      *iov;
1398         u16 num_vfs;
1399
1400         bus = pdev->bus;
1401         hose = pci_bus_to_host(bus);
1402         phb = hose->private_data;
1403         pdn = pci_get_pdn(pdev);
1404         iov = pdev->sriov;
1405         num_vfs = pdn->num_vfs;
1406
1407         /* Release VF PEs */
1408         pnv_ioda_release_vf_PE(pdev, num_vfs);
1409
1410         if (phb->type == PNV_PHB_IODA2) {
1411                 if (pdn->m64_per_iov == 1)
1412                         pnv_pci_vf_resource_shift(pdev, -pdn->offset);
1413
1414                 /* Release M64 windows */
1415                 pnv_pci_vf_release_m64(pdev);
1416
1417                 /* Release PE numbers */
1418                 bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1419                 pdn->offset = 0;
1420         }
1421 }
1422
1423 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1424                                        struct pnv_ioda_pe *pe);
1425 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1426 {
1427         struct pci_bus        *bus;
1428         struct pci_controller *hose;
1429         struct pnv_phb        *phb;
1430         struct pnv_ioda_pe    *pe;
1431         int                    pe_num;
1432         u16                    vf_index;
1433         struct pci_dn         *pdn;
1434         int64_t                rc;
1435
1436         bus = pdev->bus;
1437         hose = pci_bus_to_host(bus);
1438         phb = hose->private_data;
1439         pdn = pci_get_pdn(pdev);
1440
1441         if (!pdev->is_physfn)
1442                 return;
1443
1444         /* Reserve PE for each VF */
1445         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1446                 pe_num = pdn->offset + vf_index;
1447
1448                 pe = &phb->ioda.pe_array[pe_num];
1449                 pe->pe_number = pe_num;
1450                 pe->phb = phb;
1451                 pe->flags = PNV_IODA_PE_VF;
1452                 pe->pbus = NULL;
1453                 pe->parent_dev = pdev;
1454                 pe->tce32_seg = -1;
1455                 pe->mve_number = -1;
1456                 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1457                            pci_iov_virtfn_devfn(pdev, vf_index);
1458
1459                 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1460                         hose->global_number, pdev->bus->number,
1461                         PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1462                         PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1463
1464                 if (pnv_ioda_configure_pe(phb, pe)) {
1465                         /* XXX What do we do here ? */
1466                         if (pe_num)
1467                                 pnv_ioda_free_pe(phb, pe_num);
1468                         pe->pdev = NULL;
1469                         continue;
1470                 }
1471
1472                 /* Put PE to the list */
1473                 mutex_lock(&phb->ioda.pe_list_mutex);
1474                 list_add_tail(&pe->list, &phb->ioda.pe_list);
1475                 mutex_unlock(&phb->ioda.pe_list_mutex);
1476
1477                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1478         }
1479
1480         if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) {
1481                 int   vf_group;
1482                 int   vf_per_group;
1483                 int   vf_index1;
1484
1485                 vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1486
1487                 for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) {
1488                         for (vf_index = vf_group * vf_per_group;
1489                              vf_index < (vf_group + 1) * vf_per_group &&
1490                              vf_index < num_vfs;
1491                              vf_index++) {
1492                                 for (vf_index1 = vf_group * vf_per_group;
1493                                      vf_index1 < (vf_group + 1) * vf_per_group &&
1494                                      vf_index1 < num_vfs;
1495                                      vf_index1++) {
1496
1497                                         rc = opal_pci_set_peltv(phb->opal_id,
1498                                                 pdn->offset + vf_index,
1499                                                 pdn->offset + vf_index1,
1500                                                 OPAL_ADD_PE_TO_DOMAIN);
1501
1502                                         if (rc)
1503                                             dev_warn(&pdev->dev, "%s: Failed to link same group PE#%d(%lld)\n",
1504                                                 __func__,
1505                                                 pdn->offset + vf_index1, rc);
1506                                 }
1507                         }
1508                 }
1509         }
1510 }
1511
1512 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1513 {
1514         struct pci_bus        *bus;
1515         struct pci_controller *hose;
1516         struct pnv_phb        *phb;
1517         struct pci_dn         *pdn;
1518         int                    ret;
1519
1520         bus = pdev->bus;
1521         hose = pci_bus_to_host(bus);
1522         phb = hose->private_data;
1523         pdn = pci_get_pdn(pdev);
1524
1525         if (phb->type == PNV_PHB_IODA2) {
1526                 /* Calculate available PE for required VFs */
1527                 mutex_lock(&phb->ioda.pe_alloc_mutex);
1528                 pdn->offset = bitmap_find_next_zero_area(
1529                         phb->ioda.pe_alloc, phb->ioda.total_pe,
1530                         0, num_vfs, 0);
1531                 if (pdn->offset >= phb->ioda.total_pe) {
1532                         mutex_unlock(&phb->ioda.pe_alloc_mutex);
1533                         dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1534                         pdn->offset = 0;
1535                         return -EBUSY;
1536                 }
1537                 bitmap_set(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1538                 pdn->num_vfs = num_vfs;
1539                 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1540
1541                 /* Assign M64 window accordingly */
1542                 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1543                 if (ret) {
1544                         dev_info(&pdev->dev, "Not enough M64 window resources\n");
1545                         goto m64_failed;
1546                 }
1547
1548                 /*
1549                  * When using one M64 BAR to map one IOV BAR, we need to shift
1550                  * the IOV BAR according to the PE# allocated to the VFs.
1551                  * Otherwise, the PE# for the VF will conflict with others.
1552                  */
1553                 if (pdn->m64_per_iov == 1) {
1554                         ret = pnv_pci_vf_resource_shift(pdev, pdn->offset);
1555                         if (ret)
1556                                 goto m64_failed;
1557                 }
1558         }
1559
1560         /* Setup VF PEs */
1561         pnv_ioda_setup_vf_PE(pdev, num_vfs);
1562
1563         return 0;
1564
1565 m64_failed:
1566         bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1567         pdn->offset = 0;
1568
1569         return ret;
1570 }
1571
1572 int pcibios_sriov_disable(struct pci_dev *pdev)
1573 {
1574         pnv_pci_sriov_disable(pdev);
1575
1576         /* Release PCI data */
1577         remove_dev_pci_data(pdev);
1578         return 0;
1579 }
1580
1581 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1582 {
1583         /* Allocate PCI data */
1584         add_dev_pci_data(pdev);
1585
1586         pnv_pci_sriov_enable(pdev, num_vfs);
1587         return 0;
1588 }
1589 #endif /* CONFIG_PCI_IOV */
1590
1591 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1592 {
1593         struct pci_dn *pdn = pci_get_pdn(pdev);
1594         struct pnv_ioda_pe *pe;
1595
1596         /*
1597          * The function can be called while the PE#
1598          * hasn't been assigned. Do nothing for the
1599          * case.
1600          */
1601         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1602                 return;
1603
1604         pe = &phb->ioda.pe_array[pdn->pe_number];
1605         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1606         set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1607         /*
1608          * Note: iommu_add_device() will fail here as
1609          * for physical PE: the device is already added by now;
1610          * for virtual PE: sysfs entries are not ready yet and
1611          * tce_iommu_bus_notifier will add the device to a group later.
1612          */
1613 }
1614
1615 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1616 {
1617         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1618         struct pnv_phb *phb = hose->private_data;
1619         struct pci_dn *pdn = pci_get_pdn(pdev);
1620         struct pnv_ioda_pe *pe;
1621         uint64_t top;
1622         bool bypass = false;
1623
1624         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1625                 return -ENODEV;;
1626
1627         pe = &phb->ioda.pe_array[pdn->pe_number];
1628         if (pe->tce_bypass_enabled) {
1629                 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1630                 bypass = (dma_mask >= top);
1631         }
1632
1633         if (bypass) {
1634                 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1635                 set_dma_ops(&pdev->dev, &dma_direct_ops);
1636                 set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1637         } else {
1638                 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1639                 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1640                 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1641         }
1642         *pdev->dev.dma_mask = dma_mask;
1643         return 0;
1644 }
1645
1646 static u64 pnv_pci_ioda_dma_get_required_mask(struct pnv_phb *phb,
1647                                               struct pci_dev *pdev)
1648 {
1649         struct pci_dn *pdn = pci_get_pdn(pdev);
1650         struct pnv_ioda_pe *pe;
1651         u64 end, mask;
1652
1653         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1654                 return 0;
1655
1656         pe = &phb->ioda.pe_array[pdn->pe_number];
1657         if (!pe->tce_bypass_enabled)
1658                 return __dma_get_required_mask(&pdev->dev);
1659
1660
1661         end = pe->tce_bypass_base + memblock_end_of_DRAM();
1662         mask = 1ULL << (fls64(end) - 1);
1663         mask += mask - 1;
1664
1665         return mask;
1666 }
1667
1668 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1669                                    struct pci_bus *bus)
1670 {
1671         struct pci_dev *dev;
1672
1673         list_for_each_entry(dev, &bus->devices, bus_list) {
1674                 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1675                 iommu_add_device(&dev->dev);
1676
1677                 if (dev->subordinate)
1678                         pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1679         }
1680 }
1681
1682 static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
1683                 unsigned long index, unsigned long npages, bool rm)
1684 {
1685         struct iommu_table_group_link *tgl = list_first_entry_or_null(
1686                         &tbl->it_group_list, struct iommu_table_group_link,
1687                         next);
1688         struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1689                         struct pnv_ioda_pe, table_group);
1690         __be64 __iomem *invalidate = rm ?
1691                 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1692                 pe->phb->ioda.tce_inval_reg;
1693         unsigned long start, end, inc;
1694         const unsigned shift = tbl->it_page_shift;
1695
1696         start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1697         end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1698                         npages - 1);
1699
1700         /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
1701         if (tbl->it_busno) {
1702                 start <<= shift;
1703                 end <<= shift;
1704                 inc = 128ull << shift;
1705                 start |= tbl->it_busno;
1706                 end |= tbl->it_busno;
1707         } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
1708                 /* p7ioc-style invalidation, 2 TCEs per write */
1709                 start |= (1ull << 63);
1710                 end |= (1ull << 63);
1711                 inc = 16;
1712         } else {
1713                 /* Default (older HW) */
1714                 inc = 128;
1715         }
1716
1717         end |= inc - 1; /* round up end to be different than start */
1718
1719         mb(); /* Ensure above stores are visible */
1720         while (start <= end) {
1721                 if (rm)
1722                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1723                 else
1724                         __raw_writeq(cpu_to_be64(start), invalidate);
1725                 start += inc;
1726         }
1727
1728         /*
1729          * The iommu layer will do another mb() for us on build()
1730          * and we don't care on free()
1731          */
1732 }
1733
1734 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1735                 long npages, unsigned long uaddr,
1736                 enum dma_data_direction direction,
1737                 struct dma_attrs *attrs)
1738 {
1739         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1740                         attrs);
1741
1742         if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1743                 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1744
1745         return ret;
1746 }
1747
1748 #ifdef CONFIG_IOMMU_API
1749 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1750                 unsigned long *hpa, enum dma_data_direction *direction)
1751 {
1752         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1753
1754         if (!ret && (tbl->it_type &
1755                         (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1756                 pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false);
1757
1758         return ret;
1759 }
1760 #endif
1761
1762 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1763                 long npages)
1764 {
1765         pnv_tce_free(tbl, index, npages);
1766
1767         if (tbl->it_type & TCE_PCI_SWINV_FREE)
1768                 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1769 }
1770
1771 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1772         .set = pnv_ioda1_tce_build,
1773 #ifdef CONFIG_IOMMU_API
1774         .exchange = pnv_ioda1_tce_xchg,
1775 #endif
1776         .clear = pnv_ioda1_tce_free,
1777         .get = pnv_tce_get,
1778 };
1779
1780 static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe)
1781 {
1782         /* 01xb - invalidate TCEs that match the specified PE# */
1783         unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF);
1784         struct pnv_phb *phb = pe->phb;
1785
1786         if (!phb->ioda.tce_inval_reg)
1787                 return;
1788
1789         mb(); /* Ensure above stores are visible */
1790         __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
1791 }
1792
1793 static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm,
1794                 __be64 __iomem *invalidate, unsigned shift,
1795                 unsigned long index, unsigned long npages)
1796 {
1797         unsigned long start, end, inc;
1798
1799         /* We'll invalidate DMA address in PE scope */
1800         start = 0x2ull << 60;
1801         start |= (pe_number & 0xFF);
1802         end = start;
1803
1804         /* Figure out the start, end and step */
1805         start |= (index << shift);
1806         end |= ((index + npages - 1) << shift);
1807         inc = (0x1ull << shift);
1808         mb();
1809
1810         while (start <= end) {
1811                 if (rm)
1812                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1813                 else
1814                         __raw_writeq(cpu_to_be64(start), invalidate);
1815                 start += inc;
1816         }
1817 }
1818
1819 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1820                 unsigned long index, unsigned long npages, bool rm)
1821 {
1822         struct iommu_table_group_link *tgl;
1823
1824         list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
1825                 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1826                                 struct pnv_ioda_pe, table_group);
1827                 __be64 __iomem *invalidate = rm ?
1828                         (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1829                         pe->phb->ioda.tce_inval_reg;
1830
1831                 pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm,
1832                         invalidate, tbl->it_page_shift,
1833                         index, npages);
1834         }
1835 }
1836
1837 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1838                 long npages, unsigned long uaddr,
1839                 enum dma_data_direction direction,
1840                 struct dma_attrs *attrs)
1841 {
1842         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1843                         attrs);
1844
1845         if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1846                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1847
1848         return ret;
1849 }
1850
1851 #ifdef CONFIG_IOMMU_API
1852 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
1853                 unsigned long *hpa, enum dma_data_direction *direction)
1854 {
1855         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1856
1857         if (!ret && (tbl->it_type &
1858                         (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1859                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
1860
1861         return ret;
1862 }
1863 #endif
1864
1865 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1866                 long npages)
1867 {
1868         pnv_tce_free(tbl, index, npages);
1869
1870         if (tbl->it_type & TCE_PCI_SWINV_FREE)
1871                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1872 }
1873
1874 static void pnv_ioda2_table_free(struct iommu_table *tbl)
1875 {
1876         pnv_pci_ioda2_table_free_pages(tbl);
1877         iommu_free_table(tbl, "pnv");
1878 }
1879
1880 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
1881         .set = pnv_ioda2_tce_build,
1882 #ifdef CONFIG_IOMMU_API
1883         .exchange = pnv_ioda2_tce_xchg,
1884 #endif
1885         .clear = pnv_ioda2_tce_free,
1886         .get = pnv_tce_get,
1887         .free = pnv_ioda2_table_free,
1888 };
1889
1890 static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
1891                                       struct pnv_ioda_pe *pe, unsigned int base,
1892                                       unsigned int segs)
1893 {
1894
1895         struct page *tce_mem = NULL;
1896         struct iommu_table *tbl;
1897         unsigned int i;
1898         int64_t rc;
1899         void *addr;
1900
1901         /* XXX FIXME: Handle 64-bit only DMA devices */
1902         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
1903         /* XXX FIXME: Allocate multi-level tables on PHB3 */
1904
1905         /* We shouldn't already have a 32-bit DMA associated */
1906         if (WARN_ON(pe->tce32_seg >= 0))
1907                 return;
1908
1909         tbl = pnv_pci_table_alloc(phb->hose->node);
1910         iommu_register_group(&pe->table_group, phb->hose->global_number,
1911                         pe->pe_number);
1912         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
1913
1914         /* Grab a 32-bit TCE table */
1915         pe->tce32_seg = base;
1916         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
1917                 (base << 28), ((base + segs) << 28) - 1);
1918
1919         /* XXX Currently, we allocate one big contiguous table for the
1920          * TCEs. We only really need one chunk per 256M of TCE space
1921          * (ie per segment) but that's an optimization for later, it
1922          * requires some added smarts with our get/put_tce implementation
1923          */
1924         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
1925                                    get_order(TCE32_TABLE_SIZE * segs));
1926         if (!tce_mem) {
1927                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
1928                 goto fail;
1929         }
1930         addr = page_address(tce_mem);
1931         memset(addr, 0, TCE32_TABLE_SIZE * segs);
1932
1933         /* Configure HW */
1934         for (i = 0; i < segs; i++) {
1935                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
1936                                               pe->pe_number,
1937                                               base + i, 1,
1938                                               __pa(addr) + TCE32_TABLE_SIZE * i,
1939                                               TCE32_TABLE_SIZE, 0x1000);
1940                 if (rc) {
1941                         pe_err(pe, " Failed to configure 32-bit TCE table,"
1942                                " err %ld\n", rc);
1943                         goto fail;
1944                 }
1945         }
1946
1947         /* Setup linux iommu table */
1948         pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
1949                                   base << 28, IOMMU_PAGE_SHIFT_4K);
1950
1951         /* OPAL variant of P7IOC SW invalidated TCEs */
1952         if (phb->ioda.tce_inval_reg)
1953                 tbl->it_type |= (TCE_PCI_SWINV_CREATE |
1954                                  TCE_PCI_SWINV_FREE   |
1955                                  TCE_PCI_SWINV_PAIR);
1956
1957         tbl->it_ops = &pnv_ioda1_iommu_ops;
1958         pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
1959         pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
1960         iommu_init_table(tbl, phb->hose->node);
1961
1962         if (pe->flags & PNV_IODA_PE_DEV) {
1963                 /*
1964                  * Setting table base here only for carrying iommu_group
1965                  * further down to let iommu_add_device() do the job.
1966                  * pnv_pci_ioda_dma_dev_setup will override it later anyway.
1967                  */
1968                 set_iommu_table_base(&pe->pdev->dev, tbl);
1969                 iommu_add_device(&pe->pdev->dev);
1970         } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
1971                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
1972
1973         return;
1974  fail:
1975         /* XXX Failure: Try to fallback to 64-bit only ? */
1976         if (pe->tce32_seg >= 0)
1977                 pe->tce32_seg = -1;
1978         if (tce_mem)
1979                 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
1980         if (tbl) {
1981                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
1982                 iommu_free_table(tbl, "pnv");
1983         }
1984 }
1985
1986 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
1987                 int num, struct iommu_table *tbl)
1988 {
1989         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1990                         table_group);
1991         struct pnv_phb *phb = pe->phb;
1992         int64_t rc;
1993         const unsigned long size = tbl->it_indirect_levels ?
1994                         tbl->it_level_size : tbl->it_size;
1995         const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
1996         const __u64 win_size = tbl->it_size << tbl->it_page_shift;
1997
1998         pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
1999                         start_addr, start_addr + win_size - 1,
2000                         IOMMU_PAGE_SIZE(tbl));
2001
2002         /*
2003          * Map TCE table through TVT. The TVE index is the PE number
2004          * shifted by 1 bit for 32-bits DMA space.
2005          */
2006         rc = opal_pci_map_pe_dma_window(phb->opal_id,
2007                         pe->pe_number,
2008                         (pe->pe_number << 1) + num,
2009                         tbl->it_indirect_levels + 1,
2010                         __pa(tbl->it_base),
2011                         size << 3,
2012                         IOMMU_PAGE_SIZE(tbl));
2013         if (rc) {
2014                 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2015                 return rc;
2016         }
2017
2018         pnv_pci_link_table_and_group(phb->hose->node, num,
2019                         tbl, &pe->table_group);
2020         pnv_pci_ioda2_tce_invalidate_entire(pe);
2021
2022         return 0;
2023 }
2024
2025 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2026 {
2027         uint16_t window_id = (pe->pe_number << 1 ) + 1;
2028         int64_t rc;
2029
2030         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2031         if (enable) {
2032                 phys_addr_t top = memblock_end_of_DRAM();
2033
2034                 top = roundup_pow_of_two(top);
2035                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2036                                                      pe->pe_number,
2037                                                      window_id,
2038                                                      pe->tce_bypass_base,
2039                                                      top);
2040         } else {
2041                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2042                                                      pe->pe_number,
2043                                                      window_id,
2044                                                      pe->tce_bypass_base,
2045                                                      0);
2046         }
2047         if (rc)
2048                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2049         else
2050                 pe->tce_bypass_enabled = enable;
2051 }
2052
2053 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2054                 __u32 page_shift, __u64 window_size, __u32 levels,
2055                 struct iommu_table *tbl);
2056
2057 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2058                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2059                 struct iommu_table **ptbl)
2060 {
2061         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2062                         table_group);
2063         int nid = pe->phb->hose->node;
2064         __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2065         long ret;
2066         struct iommu_table *tbl;
2067
2068         tbl = pnv_pci_table_alloc(nid);
2069         if (!tbl)
2070                 return -ENOMEM;
2071
2072         ret = pnv_pci_ioda2_table_alloc_pages(nid,
2073                         bus_offset, page_shift, window_size,
2074                         levels, tbl);
2075         if (ret) {
2076                 iommu_free_table(tbl, "pnv");
2077                 return ret;
2078         }
2079
2080         tbl->it_ops = &pnv_ioda2_iommu_ops;
2081         if (pe->phb->ioda.tce_inval_reg)
2082                 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2083
2084         *ptbl = tbl;
2085
2086         return 0;
2087 }
2088
2089 #ifdef CONFIG_IOMMU_API
2090 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2091                 int num)
2092 {
2093         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2094                         table_group);
2095         struct pnv_phb *phb = pe->phb;
2096         long ret;
2097
2098         pe_info(pe, "Removing DMA window #%d\n", num);
2099
2100         ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2101                         (pe->pe_number << 1) + num,
2102                         0/* levels */, 0/* table address */,
2103                         0/* table size */, 0/* page size */);
2104         if (ret)
2105                 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2106         else
2107                 pnv_pci_ioda2_tce_invalidate_entire(pe);
2108
2109         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2110
2111         return ret;
2112 }
2113
2114 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2115 {
2116         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2117                                                 table_group);
2118
2119         iommu_take_ownership(table_group->tables[0]);
2120         pnv_pci_ioda2_set_bypass(pe, false);
2121 }
2122
2123 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2124 {
2125         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2126                                                 table_group);
2127
2128         iommu_release_ownership(table_group->tables[0]);
2129         pnv_pci_ioda2_set_bypass(pe, true);
2130 }
2131
2132 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2133         .create_table = pnv_pci_ioda2_create_table,
2134         .set_window = pnv_pci_ioda2_set_window,
2135         .unset_window = pnv_pci_ioda2_unset_window,
2136         .take_ownership = pnv_ioda2_take_ownership,
2137         .release_ownership = pnv_ioda2_release_ownership,
2138 };
2139 #endif
2140
2141 static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb)
2142 {
2143         const __be64 *swinvp;
2144
2145         /* OPAL variant of PHB3 invalidated TCEs */
2146         swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
2147         if (!swinvp)
2148                 return;
2149
2150         phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp);
2151         phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8);
2152 }
2153
2154 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2155                 unsigned levels, unsigned long limit,
2156                 unsigned long *current_offset)
2157 {
2158         struct page *tce_mem = NULL;
2159         __be64 *addr, *tmp;
2160         unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2161         unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2162         unsigned entries = 1UL << (shift - 3);
2163         long i;
2164
2165         tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2166         if (!tce_mem) {
2167                 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2168                 return NULL;
2169         }
2170         addr = page_address(tce_mem);
2171         memset(addr, 0, allocated);
2172
2173         --levels;
2174         if (!levels) {
2175                 *current_offset += allocated;
2176                 return addr;
2177         }
2178
2179         for (i = 0; i < entries; ++i) {
2180                 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2181                                 levels, limit, current_offset);
2182                 if (!tmp)
2183                         break;
2184
2185                 addr[i] = cpu_to_be64(__pa(tmp) |
2186                                 TCE_PCI_READ | TCE_PCI_WRITE);
2187
2188                 if (*current_offset >= limit)
2189                         break;
2190         }
2191
2192         return addr;
2193 }
2194
2195 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2196                 unsigned long size, unsigned level);
2197
2198 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2199                 __u32 page_shift, __u64 window_size, __u32 levels,
2200                 struct iommu_table *tbl)
2201 {
2202         void *addr;
2203         unsigned long offset = 0, level_shift;
2204         const unsigned window_shift = ilog2(window_size);
2205         unsigned entries_shift = window_shift - page_shift;
2206         unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2207         const unsigned long tce_table_size = 1UL << table_shift;
2208
2209         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2210                 return -EINVAL;
2211
2212         if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2213                 return -EINVAL;
2214
2215         /* Adjust direct table size from window_size and levels */
2216         entries_shift = (entries_shift + levels - 1) / levels;
2217         level_shift = entries_shift + 3;
2218         level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2219
2220         /* Allocate TCE table */
2221         addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2222                         levels, tce_table_size, &offset);
2223
2224         /* addr==NULL means that the first level allocation failed */
2225         if (!addr)
2226                 return -ENOMEM;
2227
2228         /*
2229          * First level was allocated but some lower level failed as
2230          * we did not allocate as much as we wanted,
2231          * release partially allocated table.
2232          */
2233         if (offset < tce_table_size) {
2234                 pnv_pci_ioda2_table_do_free_pages(addr,
2235                                 1ULL << (level_shift - 3), levels - 1);
2236                 return -ENOMEM;
2237         }
2238
2239         /* Setup linux iommu table */
2240         pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2241                         page_shift);
2242         tbl->it_level_size = 1ULL << (level_shift - 3);
2243         tbl->it_indirect_levels = levels - 1;
2244
2245         pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2246                         window_size, tce_table_size, bus_offset);
2247
2248         return 0;
2249 }
2250
2251 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2252                 unsigned long size, unsigned level)
2253 {
2254         const unsigned long addr_ul = (unsigned long) addr &
2255                         ~(TCE_PCI_READ | TCE_PCI_WRITE);
2256
2257         if (level) {
2258                 long i;
2259                 u64 *tmp = (u64 *) addr_ul;
2260
2261                 for (i = 0; i < size; ++i) {
2262                         unsigned long hpa = be64_to_cpu(tmp[i]);
2263
2264                         if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2265                                 continue;
2266
2267                         pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2268                                         level - 1);
2269                 }
2270         }
2271
2272         free_pages(addr_ul, get_order(size << 3));
2273 }
2274
2275 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2276 {
2277         const unsigned long size = tbl->it_indirect_levels ?
2278                         tbl->it_level_size : tbl->it_size;
2279
2280         if (!tbl->it_size)
2281                 return;
2282
2283         pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2284                         tbl->it_indirect_levels);
2285 }
2286
2287 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2288                                        struct pnv_ioda_pe *pe)
2289 {
2290         struct iommu_table *tbl = NULL;
2291         int64_t rc;
2292
2293         /* We shouldn't already have a 32-bit DMA associated */
2294         if (WARN_ON(pe->tce32_seg >= 0))
2295                 return;
2296
2297         /* TVE #1 is selected by PCI address bit 59 */
2298         pe->tce_bypass_base = 1ull << 59;
2299
2300         iommu_register_group(&pe->table_group, phb->hose->global_number,
2301                         pe->pe_number);
2302
2303         /* The PE will reserve all possible 32-bits space */
2304         pe->tce32_seg = 0;
2305         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2306                 phb->ioda.m32_pci_base);
2307
2308         /* Setup linux iommu table */
2309         pe->table_group.tce32_start = 0;
2310         pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2311         pe->table_group.max_dynamic_windows_supported =
2312                         IOMMU_TABLE_GROUP_MAX_TABLES;
2313         pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2314         pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2315
2316         rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2317                         IOMMU_PAGE_SHIFT_4K,
2318                         pe->table_group.tce32_size,
2319                         POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2320         if (rc) {
2321                 pe_err(pe, "Failed to create 32-bit TCE table, err %ld", rc);
2322                 goto fail;
2323         }
2324         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2325
2326         tbl->it_ops = &pnv_ioda2_iommu_ops;
2327         iommu_init_table(tbl, phb->hose->node);
2328 #ifdef CONFIG_IOMMU_API
2329         pe->table_group.ops = &pnv_pci_ioda2_ops;
2330 #endif
2331
2332         rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2333         if (rc) {
2334                 pe_err(pe, "Failed to configure 32-bit TCE table,"
2335                        " err %ld\n", rc);
2336                 goto fail;
2337         }
2338
2339         /* OPAL variant of PHB3 invalidated TCEs */
2340         if (phb->ioda.tce_inval_reg)
2341                 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2342
2343         if (pe->flags & PNV_IODA_PE_DEV) {
2344                 /*
2345                  * Setting table base here only for carrying iommu_group
2346                  * further down to let iommu_add_device() do the job.
2347                  * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2348                  */
2349                 set_iommu_table_base(&pe->pdev->dev, tbl);
2350                 iommu_add_device(&pe->pdev->dev);
2351         } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2352                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2353
2354         /* Also create a bypass window */
2355         if (!pnv_iommu_bypass_disabled)
2356                 pnv_pci_ioda2_set_bypass(pe, true);
2357
2358         return;
2359 fail:
2360         if (pe->tce32_seg >= 0)
2361                 pe->tce32_seg = -1;
2362         if (tbl) {
2363                 pnv_pci_ioda2_table_free_pages(tbl);
2364                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2365                 iommu_free_table(tbl, "pnv");
2366         }
2367 }
2368
2369 static void pnv_ioda_setup_dma(struct pnv_phb *phb)
2370 {
2371         struct pci_controller *hose = phb->hose;
2372         unsigned int residual, remaining, segs, tw, base;
2373         struct pnv_ioda_pe *pe;
2374
2375         /* If we have more PE# than segments available, hand out one
2376          * per PE until we run out and let the rest fail. If not,
2377          * then we assign at least one segment per PE, plus more based
2378          * on the amount of devices under that PE
2379          */
2380         if (phb->ioda.dma_pe_count > phb->ioda.tce32_count)
2381                 residual = 0;
2382         else
2383                 residual = phb->ioda.tce32_count -
2384                         phb->ioda.dma_pe_count;
2385
2386         pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
2387                 hose->global_number, phb->ioda.tce32_count);
2388         pr_info("PCI: %d PE# for a total weight of %d\n",
2389                 phb->ioda.dma_pe_count, phb->ioda.dma_weight);
2390
2391         pnv_pci_ioda_setup_opal_tce_kill(phb);
2392
2393         /* Walk our PE list and configure their DMA segments, hand them
2394          * out one base segment plus any residual segments based on
2395          * weight
2396          */
2397         remaining = phb->ioda.tce32_count;
2398         tw = phb->ioda.dma_weight;
2399         base = 0;
2400         list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
2401                 if (!pe->dma_weight)
2402                         continue;
2403                 if (!remaining) {
2404                         pe_warn(pe, "No DMA32 resources available\n");
2405                         continue;
2406                 }
2407                 segs = 1;
2408                 if (residual) {
2409                         segs += ((pe->dma_weight * residual)  + (tw / 2)) / tw;
2410                         if (segs > remaining)
2411                                 segs = remaining;
2412                 }
2413
2414                 /*
2415                  * For IODA2 compliant PHB3, we needn't care about the weight.
2416                  * The all available 32-bits DMA space will be assigned to
2417                  * the specific PE.
2418                  */
2419                 if (phb->type == PNV_PHB_IODA1) {
2420                         pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
2421                                 pe->dma_weight, segs);
2422                         pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
2423                 } else {
2424                         pe_info(pe, "Assign DMA32 space\n");
2425                         segs = 0;
2426                         pnv_pci_ioda2_setup_dma_pe(phb, pe);
2427                 }
2428
2429                 remaining -= segs;
2430                 base += segs;
2431         }
2432 }
2433
2434 #ifdef CONFIG_PCI_MSI
2435 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2436 {
2437         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2438         struct irq_chip *chip = irq_data_get_irq_chip(d);
2439         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2440                                            ioda.irq_chip);
2441         int64_t rc;
2442
2443         rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
2444         WARN_ON_ONCE(rc);
2445
2446         icp_native_eoi(d);
2447 }
2448
2449
2450 static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2451 {
2452         struct irq_data *idata;
2453         struct irq_chip *ichip;
2454
2455         if (phb->type != PNV_PHB_IODA2)
2456                 return;
2457
2458         if (!phb->ioda.irq_chip_init) {
2459                 /*
2460                  * First time we setup an MSI IRQ, we need to setup the
2461                  * corresponding IRQ chip to route correctly.
2462                  */
2463                 idata = irq_get_irq_data(virq);
2464                 ichip = irq_data_get_irq_chip(idata);
2465                 phb->ioda.irq_chip_init = 1;
2466                 phb->ioda.irq_chip = *ichip;
2467                 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2468         }
2469         irq_set_chip(virq, &phb->ioda.irq_chip);
2470 }
2471
2472 #ifdef CONFIG_CXL_BASE
2473
2474 struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev)
2475 {
2476         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2477
2478         return of_node_get(hose->dn);
2479 }
2480 EXPORT_SYMBOL(pnv_pci_get_phb_node);
2481
2482 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
2483 {
2484         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2485         struct pnv_phb *phb = hose->private_data;
2486         struct pnv_ioda_pe *pe;
2487         int rc;
2488
2489         pe = pnv_ioda_get_pe(dev);
2490         if (!pe)
2491                 return -ENODEV;
2492
2493         pe_info(pe, "Switching PHB to CXL\n");
2494
2495         rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
2496         if (rc)
2497                 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
2498
2499         return rc;
2500 }
2501 EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
2502
2503 /* Find PHB for cxl dev and allocate MSI hwirqs?
2504  * Returns the absolute hardware IRQ number
2505  */
2506 int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
2507 {
2508         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2509         struct pnv_phb *phb = hose->private_data;
2510         int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
2511
2512         if (hwirq < 0) {
2513                 dev_warn(&dev->dev, "Failed to find a free MSI\n");
2514                 return -ENOSPC;
2515         }
2516
2517         return phb->msi_base + hwirq;
2518 }
2519 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
2520
2521 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
2522 {
2523         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2524         struct pnv_phb *phb = hose->private_data;
2525
2526         msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
2527 }
2528 EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
2529
2530 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
2531                                   struct pci_dev *dev)
2532 {
2533         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2534         struct pnv_phb *phb = hose->private_data;
2535         int i, hwirq;
2536
2537         for (i = 1; i < CXL_IRQ_RANGES; i++) {
2538                 if (!irqs->range[i])
2539                         continue;
2540                 pr_devel("cxl release irq range 0x%x: offset: 0x%lx  limit: %ld\n",
2541                          i, irqs->offset[i],
2542                          irqs->range[i]);
2543                 hwirq = irqs->offset[i] - phb->msi_base;
2544                 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
2545                                        irqs->range[i]);
2546         }
2547 }
2548 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
2549
2550 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
2551                                struct pci_dev *dev, int num)
2552 {
2553         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2554         struct pnv_phb *phb = hose->private_data;
2555         int i, hwirq, try;
2556
2557         memset(irqs, 0, sizeof(struct cxl_irq_ranges));
2558
2559         /* 0 is reserved for the multiplexed PSL DSI interrupt */
2560         for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
2561                 try = num;
2562                 while (try) {
2563                         hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
2564                         if (hwirq >= 0)
2565                                 break;
2566                         try /= 2;
2567                 }
2568                 if (!try)
2569                         goto fail;
2570
2571                 irqs->offset[i] = phb->msi_base + hwirq;
2572                 irqs->range[i] = try;
2573                 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx  limit: %li\n",
2574                          i, irqs->offset[i], irqs->range[i]);
2575                 num -= try;
2576         }
2577         if (num)
2578                 goto fail;
2579
2580         return 0;
2581 fail:
2582         pnv_cxl_release_hwirq_ranges(irqs, dev);
2583         return -ENOSPC;
2584 }
2585 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
2586
2587 int pnv_cxl_get_irq_count(struct pci_dev *dev)
2588 {
2589         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2590         struct pnv_phb *phb = hose->private_data;
2591
2592         return phb->msi_bmp.irq_count;
2593 }
2594 EXPORT_SYMBOL(pnv_cxl_get_irq_count);
2595
2596 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
2597                            unsigned int virq)
2598 {
2599         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2600         struct pnv_phb *phb = hose->private_data;
2601         unsigned int xive_num = hwirq - phb->msi_base;
2602         struct pnv_ioda_pe *pe;
2603         int rc;
2604
2605         if (!(pe = pnv_ioda_get_pe(dev)))
2606                 return -ENODEV;
2607
2608         /* Assign XIVE to PE */
2609         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2610         if (rc) {
2611                 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
2612                         "hwirq 0x%x XIVE 0x%x PE\n",
2613                         pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
2614                 return -EIO;
2615         }
2616         set_msi_irq_chip(phb, virq);
2617
2618         return 0;
2619 }
2620 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
2621 #endif
2622
2623 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2624                                   unsigned int hwirq, unsigned int virq,
2625                                   unsigned int is_64, struct msi_msg *msg)
2626 {
2627         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2628         unsigned int xive_num = hwirq - phb->msi_base;
2629         __be32 data;
2630         int rc;
2631
2632         /* No PE assigned ? bail out ... no MSI for you ! */
2633         if (pe == NULL)
2634                 return -ENXIO;
2635
2636         /* Check if we have an MVE */
2637         if (pe->mve_number < 0)
2638                 return -ENXIO;
2639
2640         /* Force 32-bit MSI on some broken devices */
2641         if (dev->no_64bit_msi)
2642                 is_64 = 0;
2643
2644         /* Assign XIVE to PE */
2645         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2646         if (rc) {
2647                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2648                         pci_name(dev), rc, xive_num);
2649                 return -EIO;
2650         }
2651
2652         if (is_64) {
2653                 __be64 addr64;
2654
2655                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2656                                      &addr64, &data);
2657                 if (rc) {
2658                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2659                                 pci_name(dev), rc);
2660                         return -EIO;
2661                 }
2662                 msg->address_hi = be64_to_cpu(addr64) >> 32;
2663                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2664         } else {
2665                 __be32 addr32;
2666
2667                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2668                                      &addr32, &data);
2669                 if (rc) {
2670                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2671                                 pci_name(dev), rc);
2672                         return -EIO;
2673                 }
2674                 msg->address_hi = 0;
2675                 msg->address_lo = be32_to_cpu(addr32);
2676         }
2677         msg->data = be32_to_cpu(data);
2678
2679         set_msi_irq_chip(phb, virq);
2680
2681         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2682                  " address=%x_%08x data=%x PE# %d\n",
2683                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2684                  msg->address_hi, msg->address_lo, data, pe->pe_number);
2685
2686         return 0;
2687 }
2688
2689 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2690 {
2691         unsigned int count;
2692         const __be32 *prop = of_get_property(phb->hose->dn,
2693                                              "ibm,opal-msi-ranges", NULL);
2694         if (!prop) {
2695                 /* BML Fallback */
2696                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2697         }
2698         if (!prop)
2699                 return;
2700
2701         phb->msi_base = be32_to_cpup(prop);
2702         count = be32_to_cpup(prop + 1);
2703         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2704                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2705                        phb->hose->global_number);
2706                 return;
2707         }
2708
2709         phb->msi_setup = pnv_pci_ioda_msi_setup;
2710         phb->msi32_support = 1;
2711         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2712                 count, phb->msi_base);
2713 }
2714 #else
2715 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2716 #endif /* CONFIG_PCI_MSI */
2717
2718 #ifdef CONFIG_PCI_IOV
2719 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2720 {
2721         struct pci_controller *hose;
2722         struct pnv_phb *phb;
2723         struct resource *res;
2724         int i;
2725         resource_size_t size;
2726         struct pci_dn *pdn;
2727         int mul, total_vfs;
2728
2729         if (!pdev->is_physfn || pdev->is_added)
2730                 return;
2731
2732         hose = pci_bus_to_host(pdev->bus);
2733         phb = hose->private_data;
2734
2735         pdn = pci_get_pdn(pdev);
2736         pdn->vfs_expanded = 0;
2737
2738         total_vfs = pci_sriov_get_totalvfs(pdev);
2739         pdn->m64_per_iov = 1;
2740         mul = phb->ioda.total_pe;
2741
2742         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2743                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2744                 if (!res->flags || res->parent)
2745                         continue;
2746                 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2747                         dev_warn(&pdev->dev, " non M64 VF BAR%d: %pR\n",
2748                                  i, res);
2749                         continue;
2750                 }
2751
2752                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2753
2754                 /* bigger than 64M */
2755                 if (size > (1 << 26)) {
2756                         dev_info(&pdev->dev, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n",
2757                                  i, res);
2758                         pdn->m64_per_iov = M64_PER_IOV;
2759                         mul = roundup_pow_of_two(total_vfs);
2760                         break;
2761                 }
2762         }
2763
2764         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2765                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2766                 if (!res->flags || res->parent)
2767                         continue;
2768                 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2769                         dev_warn(&pdev->dev, "Skipping expanding VF BAR%d: %pR\n",
2770                                  i, res);
2771                         continue;
2772                 }
2773
2774                 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2775                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2776                 res->end = res->start + size * mul - 1;
2777                 dev_dbg(&pdev->dev, "                       %pR\n", res);
2778                 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2779                          i, res, mul);
2780         }
2781         pdn->vfs_expanded = mul;
2782 }
2783 #endif /* CONFIG_PCI_IOV */
2784
2785 /*
2786  * This function is supposed to be called on basis of PE from top
2787  * to bottom style. So the the I/O or MMIO segment assigned to
2788  * parent PE could be overrided by its child PEs if necessary.
2789  */
2790 static void pnv_ioda_setup_pe_seg(struct pci_controller *hose,
2791                                   struct pnv_ioda_pe *pe)
2792 {
2793         struct pnv_phb *phb = hose->private_data;
2794         struct pci_bus_region region;
2795         struct resource *res;
2796         int i, index;
2797         int rc;
2798
2799         /*
2800          * NOTE: We only care PCI bus based PE for now. For PCI
2801          * device based PE, for example SRIOV sensitive VF should
2802          * be figured out later.
2803          */
2804         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
2805
2806         pci_bus_for_each_resource(pe->pbus, res, i) {
2807                 if (!res || !res->flags ||
2808                     res->start > res->end)
2809                         continue;
2810
2811                 if (res->flags & IORESOURCE_IO) {
2812                         region.start = res->start - phb->ioda.io_pci_base;
2813                         region.end   = res->end - phb->ioda.io_pci_base;
2814                         index = region.start / phb->ioda.io_segsize;
2815
2816                         while (index < phb->ioda.total_pe &&
2817                                region.start <= region.end) {
2818                                 phb->ioda.io_segmap[index] = pe->pe_number;
2819                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2820                                         pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2821                                 if (rc != OPAL_SUCCESS) {
2822                                         pr_err("%s: OPAL error %d when mapping IO "
2823                                                "segment #%d to PE#%d\n",
2824                                                __func__, rc, index, pe->pe_number);
2825                                         break;
2826                                 }
2827
2828                                 region.start += phb->ioda.io_segsize;
2829                                 index++;
2830                         }
2831                 } else if ((res->flags & IORESOURCE_MEM) &&
2832                            !pnv_pci_is_mem_pref_64(res->flags)) {
2833                         region.start = res->start -
2834                                        hose->mem_offset[0] -
2835                                        phb->ioda.m32_pci_base;
2836                         region.end   = res->end -
2837                                        hose->mem_offset[0] -
2838                                        phb->ioda.m32_pci_base;
2839                         index = region.start / phb->ioda.m32_segsize;
2840
2841                         while (index < phb->ioda.total_pe &&
2842                                region.start <= region.end) {
2843                                 phb->ioda.m32_segmap[index] = pe->pe_number;
2844                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2845                                         pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
2846                                 if (rc != OPAL_SUCCESS) {
2847                                         pr_err("%s: OPAL error %d when mapping M32 "
2848                                                "segment#%d to PE#%d",
2849                                                __func__, rc, index, pe->pe_number);
2850                                         break;
2851                                 }
2852
2853                                 region.start += phb->ioda.m32_segsize;
2854                                 index++;
2855                         }
2856                 }
2857         }
2858 }
2859
2860 static void pnv_pci_ioda_setup_seg(void)
2861 {
2862         struct pci_controller *tmp, *hose;
2863         struct pnv_phb *phb;
2864         struct pnv_ioda_pe *pe;
2865
2866         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2867                 phb = hose->private_data;
2868                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2869                         pnv_ioda_setup_pe_seg(hose, pe);
2870                 }
2871         }
2872 }
2873
2874 static void pnv_pci_ioda_setup_DMA(void)
2875 {
2876         struct pci_controller *hose, *tmp;
2877         struct pnv_phb *phb;
2878
2879         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2880                 pnv_ioda_setup_dma(hose->private_data);
2881
2882                 /* Mark the PHB initialization done */
2883                 phb = hose->private_data;
2884                 phb->initialized = 1;
2885         }
2886 }
2887
2888 static void pnv_pci_ioda_create_dbgfs(void)
2889 {
2890 #ifdef CONFIG_DEBUG_FS
2891         struct pci_controller *hose, *tmp;
2892         struct pnv_phb *phb;
2893         char name[16];
2894
2895         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2896                 phb = hose->private_data;
2897
2898                 sprintf(name, "PCI%04x", hose->global_number);
2899                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
2900                 if (!phb->dbgfs)
2901                         pr_warning("%s: Error on creating debugfs on PHB#%x\n",
2902                                 __func__, hose->global_number);
2903         }
2904 #endif /* CONFIG_DEBUG_FS */
2905 }
2906
2907 static void pnv_pci_ioda_fixup(void)
2908 {
2909         pnv_pci_ioda_setup_PEs();
2910         pnv_pci_ioda_setup_seg();
2911         pnv_pci_ioda_setup_DMA();
2912
2913         pnv_pci_ioda_create_dbgfs();
2914
2915 #ifdef CONFIG_EEH
2916         eeh_init();
2917         eeh_addr_cache_build();
2918 #endif
2919 }
2920
2921 /*
2922  * Returns the alignment for I/O or memory windows for P2P
2923  * bridges. That actually depends on how PEs are segmented.
2924  * For now, we return I/O or M32 segment size for PE sensitive
2925  * P2P bridges. Otherwise, the default values (4KiB for I/O,
2926  * 1MiB for memory) will be returned.
2927  *
2928  * The current PCI bus might be put into one PE, which was
2929  * create against the parent PCI bridge. For that case, we
2930  * needn't enlarge the alignment so that we can save some
2931  * resources.
2932  */
2933 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
2934                                                 unsigned long type)
2935 {
2936         struct pci_dev *bridge;
2937         struct pci_controller *hose = pci_bus_to_host(bus);
2938         struct pnv_phb *phb = hose->private_data;
2939         int num_pci_bridges = 0;
2940
2941         bridge = bus->self;
2942         while (bridge) {
2943                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
2944                         num_pci_bridges++;
2945                         if (num_pci_bridges >= 2)
2946                                 return 1;
2947                 }
2948
2949                 bridge = bridge->bus->self;
2950         }
2951
2952         /* We fail back to M32 if M64 isn't supported */
2953         if (phb->ioda.m64_segsize &&
2954             pnv_pci_is_mem_pref_64(type))
2955                 return phb->ioda.m64_segsize;
2956         if (type & IORESOURCE_MEM)
2957                 return phb->ioda.m32_segsize;
2958
2959         return phb->ioda.io_segsize;
2960 }
2961
2962 #ifdef CONFIG_PCI_IOV
2963 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
2964                                                       int resno)
2965 {
2966         struct pci_dn *pdn = pci_get_pdn(pdev);
2967         resource_size_t align, iov_align;
2968
2969         iov_align = resource_size(&pdev->resource[resno]);
2970         if (iov_align)
2971                 return iov_align;
2972
2973         align = pci_iov_resource_size(pdev, resno);
2974         if (pdn->vfs_expanded)
2975                 return pdn->vfs_expanded * align;
2976
2977         return align;
2978 }
2979 #endif /* CONFIG_PCI_IOV */
2980
2981 /* Prevent enabling devices for which we couldn't properly
2982  * assign a PE
2983  */
2984 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
2985 {
2986         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2987         struct pnv_phb *phb = hose->private_data;
2988         struct pci_dn *pdn;
2989
2990         /* The function is probably called while the PEs have
2991          * not be created yet. For example, resource reassignment
2992          * during PCI probe period. We just skip the check if
2993          * PEs isn't ready.
2994          */
2995         if (!phb->initialized)
2996                 return true;
2997
2998         pdn = pci_get_pdn(dev);
2999         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3000                 return false;
3001
3002         return true;
3003 }
3004
3005 static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
3006                                u32 devfn)
3007 {
3008         return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
3009 }
3010
3011 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3012 {
3013         struct pnv_phb *phb = hose->private_data;
3014
3015         opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3016                        OPAL_ASSERT_RESET);
3017 }
3018
3019 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3020        .dma_dev_setup = pnv_pci_dma_dev_setup,
3021 #ifdef CONFIG_PCI_MSI
3022        .setup_msi_irqs = pnv_setup_msi_irqs,
3023        .teardown_msi_irqs = pnv_teardown_msi_irqs,
3024 #endif
3025        .enable_device_hook = pnv_pci_enable_device_hook,
3026        .window_alignment = pnv_pci_window_alignment,
3027        .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3028        .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3029        .shutdown = pnv_pci_ioda_shutdown,
3030 };
3031
3032 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3033                                          u64 hub_id, int ioda_type)
3034 {
3035         struct pci_controller *hose;
3036         struct pnv_phb *phb;
3037         unsigned long size, m32map_off, pemap_off, iomap_off = 0;
3038         const __be64 *prop64;
3039         const __be32 *prop32;
3040         int len;
3041         u64 phb_id;
3042         void *aux;
3043         long rc;
3044
3045         pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
3046
3047         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3048         if (!prop64) {
3049                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
3050                 return;
3051         }
3052         phb_id = be64_to_cpup(prop64);
3053         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
3054
3055         phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3056
3057         /* Allocate PCI controller */
3058         phb->hose = hose = pcibios_alloc_controller(np);
3059         if (!phb->hose) {
3060                 pr_err("  Can't allocate PCI controller for %s\n",
3061                        np->full_name);
3062                 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3063                 return;
3064         }
3065
3066         spin_lock_init(&phb->lock);
3067         prop32 = of_get_property(np, "bus-range", &len);
3068         if (prop32 && len == 8) {
3069                 hose->first_busno = be32_to_cpu(prop32[0]);
3070                 hose->last_busno = be32_to_cpu(prop32[1]);
3071         } else {
3072                 pr_warn("  Broken <bus-range> on %s\n", np->full_name);
3073                 hose->first_busno = 0;
3074                 hose->last_busno = 0xff;
3075         }
3076         hose->private_data = phb;
3077         phb->hub_id = hub_id;
3078         phb->opal_id = phb_id;
3079         phb->type = ioda_type;
3080         mutex_init(&phb->ioda.pe_alloc_mutex);
3081
3082         /* Detect specific models for error handling */
3083         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3084                 phb->model = PNV_PHB_MODEL_P7IOC;
3085         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3086                 phb->model = PNV_PHB_MODEL_PHB3;
3087         else
3088                 phb->model = PNV_PHB_MODEL_UNKNOWN;
3089
3090         /* Parse 32-bit and IO ranges (if any) */
3091         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3092
3093         /* Get registers */
3094         phb->regs = of_iomap(np, 0);
3095         if (phb->regs == NULL)
3096                 pr_err("  Failed to map registers !\n");
3097
3098         /* Initialize more IODA stuff */
3099         phb->ioda.total_pe = 1;
3100         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3101         if (prop32)
3102                 phb->ioda.total_pe = be32_to_cpup(prop32);
3103         prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3104         if (prop32)
3105                 phb->ioda.reserved_pe = be32_to_cpup(prop32);
3106
3107         /* Parse 64-bit MMIO range */
3108         pnv_ioda_parse_m64_window(phb);
3109
3110         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3111         /* FW Has already off top 64k of M32 space (MSI space) */
3112         phb->ioda.m32_size += 0x10000;
3113
3114         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
3115         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3116         phb->ioda.io_size = hose->pci_io_size;
3117         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
3118         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3119
3120         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3121         size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
3122         m32map_off = size;
3123         size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
3124         if (phb->type == PNV_PHB_IODA1) {
3125                 iomap_off = size;
3126                 size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]);
3127         }
3128         pemap_off = size;
3129         size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
3130         aux = memblock_virt_alloc(size, 0);
3131         phb->ioda.pe_alloc = aux;
3132         phb->ioda.m32_segmap = aux + m32map_off;
3133         if (phb->type == PNV_PHB_IODA1)
3134                 phb->ioda.io_segmap = aux + iomap_off;
3135         phb->ioda.pe_array = aux + pemap_off;
3136         set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc);
3137
3138         INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
3139         INIT_LIST_HEAD(&phb->ioda.pe_list);
3140         mutex_init(&phb->ioda.pe_list_mutex);
3141
3142         /* Calculate how many 32-bit TCE segments we have */
3143         phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
3144
3145 #if 0 /* We should really do that ... */
3146         rc = opal_pci_set_phb_mem_window(opal->phb_id,
3147                                          window_type,
3148                                          window_num,
3149                                          starting_real_address,
3150                                          starting_pci_address,
3151                                          segment_size);
3152 #endif
3153
3154         pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3155                 phb->ioda.total_pe, phb->ioda.reserved_pe,
3156                 phb->ioda.m32_size, phb->ioda.m32_segsize);
3157         if (phb->ioda.m64_size)
3158                 pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
3159                         phb->ioda.m64_size, phb->ioda.m64_segsize);
3160         if (phb->ioda.io_size)
3161                 pr_info("                  IO: 0x%x [segment=0x%x]\n",
3162                         phb->ioda.io_size, phb->ioda.io_segsize);
3163
3164
3165         phb->hose->ops = &pnv_pci_ops;
3166         phb->get_pe_state = pnv_ioda_get_pe_state;
3167         phb->freeze_pe = pnv_ioda_freeze_pe;
3168         phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3169
3170         /* Setup RID -> PE mapping function */
3171         phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
3172
3173         /* Setup TCEs */
3174         phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3175         phb->dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask;
3176
3177         /* Setup MSI support */
3178         pnv_pci_init_ioda_msis(phb);
3179
3180         /*
3181          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3182          * to let the PCI core do resource assignment. It's supposed
3183          * that the PCI core will do correct I/O and MMIO alignment
3184          * for the P2P bridge bars so that each PCI bus (excluding
3185          * the child P2P bridges) can form individual PE.
3186          */
3187         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3188         hose->controller_ops = pnv_pci_ioda_controller_ops;
3189
3190 #ifdef CONFIG_PCI_IOV
3191         ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3192         ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3193 #endif
3194
3195         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3196
3197         /* Reset IODA tables to a clean state */
3198         rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3199         if (rc)
3200                 pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
3201
3202         /* If we're running in kdump kerenl, the previous kerenl never
3203          * shutdown PCI devices correctly. We already got IODA table
3204          * cleaned out. So we have to issue PHB reset to stop all PCI
3205          * transactions from previous kerenl.
3206          */
3207         if (is_kdump_kernel()) {
3208                 pr_info("  Issue PHB reset ...\n");
3209                 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3210                 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3211         }
3212
3213         /* Remove M64 resource if we can't configure it successfully */
3214         if (!phb->init_m64 || phb->init_m64(phb))
3215                 hose->mem_resources[1].flags = 0;
3216 }
3217
3218 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3219 {
3220         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3221 }
3222
3223 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3224 {
3225         struct device_node *phbn;
3226         const __be64 *prop64;
3227         u64 hub_id;
3228
3229         pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3230
3231         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3232         if (!prop64) {
3233                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3234                 return;
3235         }
3236         hub_id = be64_to_cpup(prop64);
3237         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3238
3239         /* Count child PHBs */
3240         for_each_child_of_node(np, phbn) {
3241                 /* Look for IODA1 PHBs */
3242                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3243                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3244         }
3245 }