arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/crash_dump.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/delay.h>
  19 #include <linux/string.h>
  20 #include <linux/init.h>
  21 #include <linux/bootmem.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/msi.h>
  25 #include <linux/memblock.h>
  26 #include <linux/iommu.h>
  27 #include <linux/rculist.h>
  28 #include <linux/sizes.h>
  29
  30 #include <asm/sections.h>
  31 #include <asm/io.h>
  32 #include <asm/prom.h>
  33 #include <asm/pci-bridge.h>
  34 #include <asm/machdep.h>
  35 #include <asm/msi_bitmap.h>
  36 #include <asm/ppc-pci.h>
  37 #include <asm/opal.h>
  38 #include <asm/iommu.h>
  39 #include <asm/tce.h>
  40 #include <asm/xics.h>
  41 #include <asm/debug.h>
  42 #include <asm/firmware.h>
  43 #include <asm/pnv-pci.h>
  44 #include <asm/mmzone.h>
  45
  46 #include <misc/cxl-base.h>
  47
  48 #include "powernv.h"
  49 #include "pci.h"
  50
  51 /* 256M DMA window, 4K TCE pages, 8 bytes TCE */
  52 #define TCE32_TABLE_SIZE        ((0x10000000 / 0x1000) * 8)
  53
  54 #define POWERNV_IOMMU_DEFAULT_LEVELS    1
  55 #define POWERNV_IOMMU_MAX_LEVELS        5
  56
  57 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
  58
  59 static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
  60                             const char *fmt, ...)
  61 {
  62         struct va_format vaf;
  63         va_list args;
  64         char pfix[32];
  65
  66         va_start(args, fmt);
  67
  68         vaf.fmt = fmt;
  69         vaf.va = &args;
  70
  71         if (pe->flags & PNV_IODA_PE_DEV)
  72                 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
  73         else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
  74                 sprintf(pfix, "%04x:%02x     ",
  75                         pci_domain_nr(pe->pbus), pe->pbus->number);
  76 #ifdef CONFIG_PCI_IOV
  77         else if (pe->flags & PNV_IODA_PE_VF)
  78                 sprintf(pfix, "%04x:%02x:%2x.%d",
  79                         pci_domain_nr(pe->parent_dev->bus),
  80                         (pe->rid & 0xff00) >> 8,
  81                         PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
  82 #endif /* CONFIG_PCI_IOV*/
  83
  84         printk("%spci %s: [PE# %.3d] %pV",
  85                level, pfix, pe->pe_number, &vaf);
  86
  87         va_end(args);
  88 }
  89
  90 #define pe_err(pe, fmt, ...)                                    \
  91         pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
  92 #define pe_warn(pe, fmt, ...)                                   \
  93         pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
  94 #define pe_info(pe, fmt, ...)                                   \
  95         pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
  96
  97 static bool pnv_iommu_bypass_disabled __read_mostly;
  98
  99 static int __init iommu_setup(char *str)
 100 {
 101         if (!str)
 102                 return -EINVAL;
 103
 104         while (*str) {
 105                 if (!strncmp(str, "nobypass", 8)) {
 106                         pnv_iommu_bypass_disabled = true;
 107                         pr_info("PowerNV: IOMMU bypass window disabled.\n");
 108                         break;
 109                 }
 110                 str += strcspn(str, ",");
 111                 if (*str == ',')
 112                         str++;
 113         }
 114
 115         return 0;
 116 }
 117 early_param("iommu", iommu_setup);
 118
 119 /*
 120  * stdcix is only supposed to be used in hypervisor real mode as per
 121  * the architecture spec
 122  */
 123 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
 124 {
 125         __asm__ __volatile__("stdcix %0,0,%1"
 126                 : : "r" (val), "r" (paddr) : "memory");
 127 }
 128
 129 static inline bool pnv_pci_is_mem_pref_64(unsigned long flags)
 130 {
 131         return ((flags & (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH)) ==
 132                 (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH));
 133 }
 134
 135 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
 136 {
 137         if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe)) {
 138                 pr_warn("%s: Invalid PE %d on PHB#%x\n",
 139                         __func__, pe_no, phb->hose->global_number);
 140                 return;
 141         }
 142
 143         if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) {
 144                 pr_warn("%s: PE %d was assigned on PHB#%x\n",
 145                         __func__, pe_no, phb->hose->global_number);
 146                 return;
 147         }
 148
 149         phb->ioda.pe_array[pe_no].phb = phb;
 150         phb->ioda.pe_array[pe_no].pe_number = pe_no;
 151 }
 152
 153 static int pnv_ioda_alloc_pe(struct pnv_phb *phb)
 154 {
 155         unsigned long pe;
 156
 157         do {
 158                 pe = find_next_zero_bit(phb->ioda.pe_alloc,
 159                                         phb->ioda.total_pe, 0);
 160                 if (pe >= phb->ioda.total_pe)
 161                         return IODA_INVALID_PE;
 162         } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
 163
 164         phb->ioda.pe_array[pe].phb = phb;
 165         phb->ioda.pe_array[pe].pe_number = pe;
 166         return pe;
 167 }
 168
 169 static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
 170 {
 171         WARN_ON(phb->ioda.pe_array[pe].pdev);
 172
 173         memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
 174         clear_bit(pe, phb->ioda.pe_alloc);
 175 }
 176
 177 /* The default M64 BAR is shared by all PEs */
 178 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
 179 {
 180         const char *desc;
 181         struct resource *r;
 182         s64 rc;
 183
 184         /* Configure the default M64 BAR */
 185         rc = opal_pci_set_phb_mem_window(phb->opal_id,
 186                                          OPAL_M64_WINDOW_TYPE,
 187                                          phb->ioda.m64_bar_idx,
 188                                          phb->ioda.m64_base,
 189                                          0, /* unused */
 190                                          phb->ioda.m64_size);
 191         if (rc != OPAL_SUCCESS) {
 192                 desc = "configuring";
 193                 goto fail;
 194         }
 195
 196         /* Enable the default M64 BAR */
 197         rc = opal_pci_phb_mmio_enable(phb->opal_id,
 198                                       OPAL_M64_WINDOW_TYPE,
 199                                       phb->ioda.m64_bar_idx,
 200                                       OPAL_ENABLE_M64_SPLIT);
 201         if (rc != OPAL_SUCCESS) {
 202                 desc = "enabling";
 203                 goto fail;
 204         }
 205
 206         /* Mark the M64 BAR assigned */
 207         set_bit(phb->ioda.m64_bar_idx, &phb->ioda.m64_bar_alloc);
 208
 209         /*
 210          * Strip off the segment used by the reserved PE, which is
 211          * expected to be 0 or last one of PE capabicity.
 212          */
 213         r = &phb->hose->mem_resources[1];
 214         if (phb->ioda.reserved_pe == 0)
 215                 r->start += phb->ioda.m64_segsize;
 216         else if (phb->ioda.reserved_pe == (phb->ioda.total_pe - 1))
 217                 r->end -= phb->ioda.m64_segsize;
 218         else
 219                 pr_warn("  Cannot strip M64 segment for reserved PE#%d\n",
 220                         phb->ioda.reserved_pe);
 221
 222         return 0;
 223
 224 fail:
 225         pr_warn("  Failure %lld %s M64 BAR#%d\n",
 226                 rc, desc, phb->ioda.m64_bar_idx);
 227         opal_pci_phb_mmio_enable(phb->opal_id,
 228                                  OPAL_M64_WINDOW_TYPE,
 229                                  phb->ioda.m64_bar_idx,
 230                                  OPAL_DISABLE_M64);
 231         return -EIO;
 232 }
 233
 234 static void pnv_ioda2_reserve_m64_pe(struct pnv_phb *phb)
 235 {
 236         resource_size_t sgsz = phb->ioda.m64_segsize;
 237         struct pci_dev *pdev;
 238         struct resource *r;
 239         int base, step, i;
 240
 241         /*
 242          * Root bus always has full M64 range and root port has
 243          * M64 range used in reality. So we're checking root port
 244          * instead of root bus.
 245          */
 246         list_for_each_entry(pdev, &phb->hose->bus->devices, bus_list) {
 247                 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
 248                         r = &pdev->resource[PCI_BRIDGE_RESOURCES + i];
 249                         if (!r->parent ||
 250                             !pnv_pci_is_mem_pref_64(r->flags))
 251                                 continue;
 252
 253                         base = (r->start - phb->ioda.m64_base) / sgsz;
 254                         for (step = 0; step < resource_size(r) / sgsz; step++)
 255                                 pnv_ioda_reserve_pe(phb, base + step);
 256                 }
 257         }
 258 }
 259
 260 static int pnv_ioda2_pick_m64_pe(struct pnv_phb *phb,
 261                                  struct pci_bus *bus, int all)
 262 {
 263         resource_size_t segsz = phb->ioda.m64_segsize;
 264         struct pci_dev *pdev;
 265         struct resource *r;
 266         struct pnv_ioda_pe *master_pe, *pe;
 267         unsigned long size, *pe_alloc;
 268         bool found;
 269         int start, i, j;
 270
 271         /* Root bus shouldn't use M64 */
 272         if (pci_is_root_bus(bus))
 273                 return IODA_INVALID_PE;
 274
 275         /* We support only one M64 window on each bus */
 276         found = false;
 277         pci_bus_for_each_resource(bus, r, i) {
 278                 if (r && r->parent &&
 279                     pnv_pci_is_mem_pref_64(r->flags)) {
 280                         found = true;
 281                         break;
 282                 }
 283         }
 284
 285         /* No M64 window found ? */
 286         if (!found)
 287                 return IODA_INVALID_PE;
 288
 289         /* Allocate bitmap */
 290         size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
 291         pe_alloc = kzalloc(size, GFP_KERNEL);
 292         if (!pe_alloc) {
 293                 pr_warn("%s: Out of memory !\n",
 294                         __func__);
 295                 return IODA_INVALID_PE;
 296         }
 297
 298         /*
 299          * Figure out reserved PE numbers by the PE
 300          * the its child PEs.
 301          */
 302         start = (r->start - phb->ioda.m64_base) / segsz;
 303         for (i = 0; i < resource_size(r) / segsz; i++)
 304                 set_bit(start + i, pe_alloc);
 305
 306         if (all)
 307                 goto done;
 308
 309         /*
 310          * If the PE doesn't cover all subordinate buses,
 311          * we need subtract from reserved PEs for children.
 312          */
 313         list_for_each_entry(pdev, &bus->devices, bus_list) {
 314                 if (!pdev->subordinate)
 315                         continue;
 316
 317                 pci_bus_for_each_resource(pdev->subordinate, r, i) {
 318                         if (!r || !r->parent ||
 319                             !pnv_pci_is_mem_pref_64(r->flags))
 320                                 continue;
 321
 322                         start = (r->start - phb->ioda.m64_base) / segsz;
 323                         for (j = 0; j < resource_size(r) / segsz ; j++)
 324                                 clear_bit(start + j, pe_alloc);
 325                 }
 326         }
 327
 328         /*
 329          * the current bus might not own M64 window and that's all
 330          * contributed by its child buses. For the case, we needn't
 331          * pick M64 dependent PE#.
 332          */
 333         if (bitmap_empty(pe_alloc, phb->ioda.total_pe)) {
 334                 kfree(pe_alloc);
 335                 return IODA_INVALID_PE;
 336         }
 337
 338         /*
 339          * Figure out the master PE and put all slave PEs to master
 340          * PE's list to form compound PE.
 341          */
 342 done:
 343         master_pe = NULL;
 344         i = -1;
 345         while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe, i + 1)) <
 346                 phb->ioda.total_pe) {
 347                 pe = &phb->ioda.pe_array[i];
 348
 349                 if (!master_pe) {
 350                         pe->flags |= PNV_IODA_PE_MASTER;
 351                         INIT_LIST_HEAD(&pe->slaves);
 352                         master_pe = pe;
 353                 } else {
 354                         pe->flags |= PNV_IODA_PE_SLAVE;
 355                         pe->master = master_pe;
 356                         list_add_tail(&pe->list, &master_pe->slaves);
 357                 }
 358         }
 359
 360         kfree(pe_alloc);
 361         return master_pe->pe_number;
 362 }
 363
 364 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
 365 {
 366         struct pci_controller *hose = phb->hose;
 367         struct device_node *dn = hose->dn;
 368         struct resource *res;
 369         const u32 *r;
 370         u64 pci_addr;
 371
 372         /* FIXME: Support M64 for P7IOC */
 373         if (phb->type != PNV_PHB_IODA2) {
 374                 pr_info("  Not support M64 window\n");
 375                 return;
 376         }
 377
 378         if (!firmware_has_feature(FW_FEATURE_OPALv3)) {
 379                 pr_info("  Firmware too old to support M64 window\n");
 380                 return;
 381         }
 382
 383         r = of_get_property(dn, "ibm,opal-m64-window", NULL);
 384         if (!r) {
 385                 pr_info("  No <ibm,opal-m64-window> on %s\n",
 386                         dn->full_name);
 387                 return;
 388         }
 389
 390         res = &hose->mem_resources[1];
 391         res->start = of_translate_address(dn, r + 2);
 392         res->end = res->start + of_read_number(r + 4, 2) - 1;
 393         res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
 394         pci_addr = of_read_number(r, 2);
 395         hose->mem_offset[1] = res->start - pci_addr;
 396
 397         phb->ioda.m64_size = resource_size(res);
 398         phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe;
 399         phb->ioda.m64_base = pci_addr;
 400
 401         pr_info(" MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
 402                         res->start, res->end, pci_addr);
 403
 404         /* Use last M64 BAR to cover M64 window */
 405         phb->ioda.m64_bar_idx = 15;
 406         phb->init_m64 = pnv_ioda2_init_m64;
 407         phb->reserve_m64_pe = pnv_ioda2_reserve_m64_pe;
 408         phb->pick_m64_pe = pnv_ioda2_pick_m64_pe;
 409 }
 410
 411 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
 412 {
 413         struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
 414         struct pnv_ioda_pe *slave;
 415         s64 rc;
 416
 417         /* Fetch master PE */
 418         if (pe->flags & PNV_IODA_PE_SLAVE) {
 419                 pe = pe->master;
 420                 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
 421                         return;
 422
 423                 pe_no = pe->pe_number;
 424         }
 425
 426         /* Freeze master PE */
 427         rc = opal_pci_eeh_freeze_set(phb->opal_id,
 428                                      pe_no,
 429                                      OPAL_EEH_ACTION_SET_FREEZE_ALL);
 430         if (rc != OPAL_SUCCESS) {
 431                 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 432                         __func__, rc, phb->hose->global_number, pe_no);
 433                 return;
 434         }
 435
 436         /* Freeze slave PEs */
 437         if (!(pe->flags & PNV_IODA_PE_MASTER))
 438                 return;
 439
 440         list_for_each_entry(slave, &pe->slaves, list) {
 441                 rc = opal_pci_eeh_freeze_set(phb->opal_id,
 442                                              slave->pe_number,
 443                                              OPAL_EEH_ACTION_SET_FREEZE_ALL);
 444                 if (rc != OPAL_SUCCESS)
 445                         pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
 446                                 __func__, rc, phb->hose->global_number,
 447                                 slave->pe_number);
 448         }
 449 }
 450
 451 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
 452 {
 453         struct pnv_ioda_pe *pe, *slave;
 454         s64 rc;
 455
 456         /* Find master PE */
 457         pe = &phb->ioda.pe_array[pe_no];
 458         if (pe->flags & PNV_IODA_PE_SLAVE) {
 459                 pe = pe->master;
 460                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 461                 pe_no = pe->pe_number;
 462         }
 463
 464         /* Clear frozen state for master PE */
 465         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
 466         if (rc != OPAL_SUCCESS) {
 467                 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 468                         __func__, rc, opt, phb->hose->global_number, pe_no);
 469                 return -EIO;
 470         }
 471
 472         if (!(pe->flags & PNV_IODA_PE_MASTER))
 473                 return 0;
 474
 475         /* Clear frozen state for slave PEs */
 476         list_for_each_entry(slave, &pe->slaves, list) {
 477                 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
 478                                              slave->pe_number,
 479                                              opt);
 480                 if (rc != OPAL_SUCCESS) {
 481                         pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
 482                                 __func__, rc, opt, phb->hose->global_number,
 483                                 slave->pe_number);
 484                         return -EIO;
 485                 }
 486         }
 487
 488         return 0;
 489 }
 490
 491 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
 492 {
 493         struct pnv_ioda_pe *slave, *pe;
 494         u8 fstate, state;
 495         __be16 pcierr;
 496         s64 rc;
 497
 498         /* Sanity check on PE number */
 499         if (pe_no < 0 || pe_no >= phb->ioda.total_pe)
 500                 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
 501
 502         /*
 503          * Fetch the master PE and the PE instance might be
 504          * not initialized yet.
 505          */
 506         pe = &phb->ioda.pe_array[pe_no];
 507         if (pe->flags & PNV_IODA_PE_SLAVE) {
 508                 pe = pe->master;
 509                 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
 510                 pe_no = pe->pe_number;
 511         }
 512
 513         /* Check the master PE */
 514         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
 515                                         &state, &pcierr, NULL);
 516         if (rc != OPAL_SUCCESS) {
 517                 pr_warn("%s: Failure %lld getting "
 518                         "PHB#%x-PE#%x state\n",
 519                         __func__, rc,
 520                         phb->hose->global_number, pe_no);
 521                 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 522         }
 523
 524         /* Check the slave PE */
 525         if (!(pe->flags & PNV_IODA_PE_MASTER))
 526                 return state;
 527
 528         list_for_each_entry(slave, &pe->slaves, list) {
 529                 rc = opal_pci_eeh_freeze_status(phb->opal_id,
 530                                                 slave->pe_number,
 531                                                 &fstate,
 532                                                 &pcierr,
 533                                                 NULL);
 534                 if (rc != OPAL_SUCCESS) {
 535                         pr_warn("%s: Failure %lld getting "
 536                                 "PHB#%x-PE#%x state\n",
 537                                 __func__, rc,
 538                                 phb->hose->global_number, slave->pe_number);
 539                         return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
 540                 }
 541
 542                 /*
 543                  * Override the result based on the ascending
 544                  * priority.
 545                  */
 546                 if (fstate > state)
 547                         state = fstate;
 548         }
 549
 550         return state;
 551 }
 552
 553 /* Currently those 2 are only used when MSIs are enabled, this will change
 554  * but in the meantime, we need to protect them to avoid warnings
 555  */
 556 #ifdef CONFIG_PCI_MSI
 557 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 558 {
 559         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 560         struct pnv_phb *phb = hose->private_data;
 561         struct pci_dn *pdn = pci_get_pdn(dev);
 562
 563         if (!pdn)
 564                 return NULL;
 565         if (pdn->pe_number == IODA_INVALID_PE)
 566                 return NULL;
 567         return &phb->ioda.pe_array[pdn->pe_number];
 568 }
 569 #endif /* CONFIG_PCI_MSI */
 570
 571 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
 572                                   struct pnv_ioda_pe *parent,
 573                                   struct pnv_ioda_pe *child,
 574                                   bool is_add)
 575 {
 576         const char *desc = is_add ? "adding" : "removing";
 577         uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
 578                               OPAL_REMOVE_PE_FROM_DOMAIN;
 579         struct pnv_ioda_pe *slave;
 580         long rc;
 581
 582         /* Parent PE affects child PE */
 583         rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 584                                 child->pe_number, op);
 585         if (rc != OPAL_SUCCESS) {
 586                 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
 587                         rc, desc);
 588                 return -ENXIO;
 589         }
 590
 591         if (!(child->flags & PNV_IODA_PE_MASTER))
 592                 return 0;
 593
 594         /* Compound case: parent PE affects slave PEs */
 595         list_for_each_entry(slave, &child->slaves, list) {
 596                 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
 597                                         slave->pe_number, op);
 598                 if (rc != OPAL_SUCCESS) {
 599                         pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
 600                                 rc, desc);
 601                         return -ENXIO;
 602                 }
 603         }
 604
 605         return 0;
 606 }
 607
 608 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
 609                               struct pnv_ioda_pe *pe,
 610                               bool is_add)
 611 {
 612         struct pnv_ioda_pe *slave;
 613         struct pci_dev *pdev = NULL;
 614         int ret;
 615
 616         /*
 617          * Clear PE frozen state. If it's master PE, we need
 618          * clear slave PE frozen state as well.
 619          */
 620         if (is_add) {
 621                 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 622                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 623                 if (pe->flags & PNV_IODA_PE_MASTER) {
 624                         list_for_each_entry(slave, &pe->slaves, list)
 625                                 opal_pci_eeh_freeze_clear(phb->opal_id,
 626                                                           slave->pe_number,
 627                                                           OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 628                 }
 629         }
 630
 631         /*
 632          * Associate PE in PELT. We need add the PE into the
 633          * corresponding PELT-V as well. Otherwise, the error
 634          * originated from the PE might contribute to other
 635          * PEs.
 636          */
 637         ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
 638         if (ret)
 639                 return ret;
 640
 641         /* For compound PEs, any one affects all of them */
 642         if (pe->flags & PNV_IODA_PE_MASTER) {
 643                 list_for_each_entry(slave, &pe->slaves, list) {
 644                         ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
 645                         if (ret)
 646                                 return ret;
 647                 }
 648         }
 649
 650         if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
 651                 pdev = pe->pbus->self;
 652         else if (pe->flags & PNV_IODA_PE_DEV)
 653                 pdev = pe->pdev->bus->self;
 654 #ifdef CONFIG_PCI_IOV
 655         else if (pe->flags & PNV_IODA_PE_VF)
 656                 pdev = pe->parent_dev->bus->self;
 657 #endif /* CONFIG_PCI_IOV */
 658         while (pdev) {
 659                 struct pci_dn *pdn = pci_get_pdn(pdev);
 660                 struct pnv_ioda_pe *parent;
 661
 662                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 663                         parent = &phb->ioda.pe_array[pdn->pe_number];
 664                         ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
 665                         if (ret)
 666                                 return ret;
 667                 }
 668
 669                 pdev = pdev->bus->self;
 670         }
 671
 672         return 0;
 673 }
 674
 675 #ifdef CONFIG_PCI_IOV
 676 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 677 {
 678         struct pci_dev *parent;
 679         uint8_t bcomp, dcomp, fcomp;
 680         int64_t rc;
 681         long rid_end, rid;
 682
 683         /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
 684         if (pe->pbus) {
 685                 int count;
 686
 687                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 688                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 689                 parent = pe->pbus->self;
 690                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 691                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 692                 else
 693                         count = 1;
 694
 695                 switch(count) {
 696                 case  1: bcomp = OpalPciBusAll;         break;
 697                 case  2: bcomp = OpalPciBus7Bits;       break;
 698                 case  4: bcomp = OpalPciBus6Bits;       break;
 699                 case  8: bcomp = OpalPciBus5Bits;       break;
 700                 case 16: bcomp = OpalPciBus4Bits;       break;
 701                 case 32: bcomp = OpalPciBus3Bits;       break;
 702                 default:
 703                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 704                                 count);
 705                         /* Do an exact match only */
 706                         bcomp = OpalPciBusAll;
 707                 }
 708                 rid_end = pe->rid + (count << 8);
 709         } else {
 710                 if (pe->flags & PNV_IODA_PE_VF)
 711                         parent = pe->parent_dev;
 712                 else
 713                         parent = pe->pdev->bus->self;
 714                 bcomp = OpalPciBusAll;
 715                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 716                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 717                 rid_end = pe->rid + 1;
 718         }
 719
 720         /* Clear the reverse map */
 721         for (rid = pe->rid; rid < rid_end; rid++)
 722                 phb->ioda.pe_rmap[rid] = 0;
 723
 724         /* Release from all parents PELT-V */
 725         while (parent) {
 726                 struct pci_dn *pdn = pci_get_pdn(parent);
 727                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 728                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 729                                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 730                         /* XXX What to do in case of error ? */
 731                 }
 732                 parent = parent->bus->self;
 733         }
 734
 735         opal_pci_eeh_freeze_set(phb->opal_id, pe->pe_number,
 736                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 737
 738         /* Disassociate PE in PELT */
 739         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 740                                 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
 741         if (rc)
 742                 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
 743         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 744                              bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
 745         if (rc)
 746                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 747
 748         pe->pbus = NULL;
 749         pe->pdev = NULL;
 750         pe->parent_dev = NULL;
 751
 752         return 0;
 753 }
 754 #endif /* CONFIG_PCI_IOV */
 755
 756 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 757 {
 758         struct pci_dev *parent;
 759         uint8_t bcomp, dcomp, fcomp;
 760         long rc, rid_end, rid;
 761
 762         /* Bus validation ? */
 763         if (pe->pbus) {
 764                 int count;
 765
 766                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 767                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 768                 parent = pe->pbus->self;
 769                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 770                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 771                 else
 772                         count = 1;
 773
 774                 switch(count) {
 775                 case  1: bcomp = OpalPciBusAll;         break;
 776                 case  2: bcomp = OpalPciBus7Bits;       break;
 777                 case  4: bcomp = OpalPciBus6Bits;       break;
 778                 case  8: bcomp = OpalPciBus5Bits;       break;
 779                 case 16: bcomp = OpalPciBus4Bits;       break;
 780                 case 32: bcomp = OpalPciBus3Bits;       break;
 781                 default:
 782                         dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
 783                                 count);
 784                         /* Do an exact match only */
 785                         bcomp = OpalPciBusAll;
 786                 }
 787                 rid_end = pe->rid + (count << 8);
 788         } else {
 789 #ifdef CONFIG_PCI_IOV
 790                 if (pe->flags & PNV_IODA_PE_VF)
 791                         parent = pe->parent_dev;
 792                 else
 793 #endif /* CONFIG_PCI_IOV */
 794                         parent = pe->pdev->bus->self;
 795                 bcomp = OpalPciBusAll;
 796                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 797                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 798                 rid_end = pe->rid + 1;
 799         }
 800
 801         /*
 802          * Associate PE in PELT. We need add the PE into the
 803          * corresponding PELT-V as well. Otherwise, the error
 804          * originated from the PE might contribute to other
 805          * PEs.
 806          */
 807         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 808                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 809         if (rc) {
 810                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 811                 return -ENXIO;
 812         }
 813
 814         /* Configure PELTV */
 815         pnv_ioda_set_peltv(phb, pe, true);
 816
 817         /* Setup reverse map */
 818         for (rid = pe->rid; rid < rid_end; rid++)
 819                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 820
 821         /* Setup one MVTs on IODA1 */
 822         if (phb->type != PNV_PHB_IODA1) {
 823                 pe->mve_number = 0;
 824                 goto out;
 825         }
 826
 827         pe->mve_number = pe->pe_number;
 828         rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
 829         if (rc != OPAL_SUCCESS) {
 830                 pe_err(pe, "OPAL error %ld setting up MVE %d\n",
 831                        rc, pe->mve_number);
 832                 pe->mve_number = -1;
 833         } else {
 834                 rc = opal_pci_set_mve_enable(phb->opal_id,
 835                                              pe->mve_number, OPAL_ENABLE_MVE);
 836                 if (rc) {
 837                         pe_err(pe, "OPAL error %ld enabling MVE %d\n",
 838                                rc, pe->mve_number);
 839                         pe->mve_number = -1;
 840                 }
 841         }
 842
 843 out:
 844         return 0;
 845 }
 846
 847 static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
 848                                        struct pnv_ioda_pe *pe)
 849 {
 850         struct pnv_ioda_pe *lpe;
 851
 852         list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) {
 853                 if (lpe->dma_weight < pe->dma_weight) {
 854                         list_add_tail(&pe->dma_link, &lpe->dma_link);
 855                         return;
 856                 }
 857         }
 858         list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list);
 859 }
 860
 861 static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
 862 {
 863         /* This is quite simplistic. The "base" weight of a device
 864          * is 10. 0 means no DMA is to be accounted for it.
 865          */
 866
 867         /* If it's a bridge, no DMA */
 868         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
 869                 return 0;
 870
 871         /* Reduce the weight of slow USB controllers */
 872         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
 873             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
 874             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
 875                 return 3;
 876
 877         /* Increase the weight of RAID (includes Obsidian) */
 878         if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
 879                 return 15;
 880
 881         /* Default */
 882         return 10;
 883 }
 884
 885 #ifdef CONFIG_PCI_IOV
 886 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
 887 {
 888         struct pci_dn *pdn = pci_get_pdn(dev);
 889         int i;
 890         struct resource *res, res2;
 891         resource_size_t size;
 892         u16 num_vfs;
 893
 894         if (!dev->is_physfn)
 895                 return -EINVAL;
 896
 897         /*
 898          * "offset" is in VFs.  The M64 windows are sized so that when they
 899          * are segmented, each segment is the same size as the IOV BAR.
 900          * Each segment is in a separate PE, and the high order bits of the
 901          * address are the PE number.  Therefore, each VF's BAR is in a
 902          * separate PE, and changing the IOV BAR start address changes the
 903          * range of PEs the VFs are in.
 904          */
 905         num_vfs = pdn->num_vfs;
 906         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 907                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 908                 if (!res->flags || !res->parent)
 909                         continue;
 910
 911                 if (!pnv_pci_is_mem_pref_64(res->flags))
 912                         continue;
 913
 914                 /*
 915                  * The actual IOV BAR range is determined by the start address
 916                  * and the actual size for num_vfs VFs BAR.  This check is to
 917                  * make sure that after shifting, the range will not overlap
 918                  * with another device.
 919                  */
 920                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 921                 res2.flags = res->flags;
 922                 res2.start = res->start + (size * offset);
 923                 res2.end = res2.start + (size * num_vfs) - 1;
 924
 925                 if (res2.end > res->end) {
 926                         dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
 927                                 i, &res2, res, num_vfs, offset);
 928                         return -EBUSY;
 929                 }
 930         }
 931
 932         /*
 933          * After doing so, there would be a "hole" in the /proc/iomem when
 934          * offset is a positive value. It looks like the device return some
 935          * mmio back to the system, which actually no one could use it.
 936          */
 937         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
 938                 res = &dev->resource[i + PCI_IOV_RESOURCES];
 939                 if (!res->flags || !res->parent)
 940                         continue;
 941
 942                 if (!pnv_pci_is_mem_pref_64(res->flags))
 943                         continue;
 944
 945                 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
 946                 res2 = *res;
 947                 res->start += size * offset;
 948
 949                 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (enabling %d VFs shifted by %d)\n",
 950                          i, &res2, res, num_vfs, offset);
 951                 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
 952         }
 953         return 0;
 954 }
 955 #endif /* CONFIG_PCI_IOV */
 956
 957 #if 0
 958 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
 959 {
 960         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 961         struct pnv_phb *phb = hose->private_data;
 962         struct pci_dn *pdn = pci_get_pdn(dev);
 963         struct pnv_ioda_pe *pe;
 964         int pe_num;
 965
 966         if (!pdn) {
 967                 pr_err("%s: Device tree node not associated properly\n",
 968                            pci_name(dev));
 969                 return NULL;
 970         }
 971         if (pdn->pe_number != IODA_INVALID_PE)
 972                 return NULL;
 973
 974         /* PE#0 has been pre-set */
 975         if (dev->bus->number == 0)
 976                 pe_num = 0;
 977         else
 978                 pe_num = pnv_ioda_alloc_pe(phb);
 979         if (pe_num == IODA_INVALID_PE) {
 980                 pr_warning("%s: Not enough PE# available, disabling device\n",
 981                            pci_name(dev));
 982                 return NULL;
 983         }
 984
 985         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
 986          * pointer in the PE data structure, both should be destroyed at the
 987          * same time. However, this needs to be looked at more closely again
 988          * once we actually start removing things (Hotplug, SR-IOV, ...)
 989          *
 990          * At some point we want to remove the PDN completely anyways
 991          */
 992         pe = &phb->ioda.pe_array[pe_num];
 993         pci_dev_get(dev);
 994         pdn->pcidev = dev;
 995         pdn->pe_number = pe_num;
 996         pe->pdev = dev;
 997         pe->pbus = NULL;
 998         pe->tce32_seg = -1;
 999         pe->mve_number = -1;
1000         pe->rid = dev->bus->number << 8 | pdn->devfn;
1001
1002         pe_info(pe, "Associated device to PE\n");
1003
1004         if (pnv_ioda_configure_pe(phb, pe)) {
1005                 /* XXX What do we do here ? */
1006                 if (pe_num)
1007                         pnv_ioda_free_pe(phb, pe_num);
1008                 pdn->pe_number = IODA_INVALID_PE;
1009                 pe->pdev = NULL;
1010                 pci_dev_put(dev);
1011                 return NULL;
1012         }
1013
1014         /* Assign a DMA weight to the device */
1015         pe->dma_weight = pnv_ioda_dma_weight(dev);
1016         if (pe->dma_weight != 0) {
1017                 phb->ioda.dma_weight += pe->dma_weight;
1018                 phb->ioda.dma_pe_count++;
1019         }
1020
1021         /* Link the PE */
1022         pnv_ioda_link_pe_by_weight(phb, pe);
1023
1024         return pe;
1025 }
1026 #endif /* Useful for SRIOV case */
1027
1028 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1029 {
1030         struct pci_dev *dev;
1031
1032         list_for_each_entry(dev, &bus->devices, bus_list) {
1033                 struct pci_dn *pdn = pci_get_pdn(dev);
1034
1035                 if (pdn == NULL) {
1036                         pr_warn("%s: No device node associated with device !\n",
1037                                 pci_name(dev));
1038                         continue;
1039                 }
1040                 pdn->pe_number = pe->pe_number;
1041                 pe->dma_weight += pnv_ioda_dma_weight(dev);
1042                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1043                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
1044         }
1045 }
1046
1047 /*
1048  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1049  * single PCI bus. Another one that contains the primary PCI bus and its
1050  * subordinate PCI devices and buses. The second type of PE is normally
1051  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1052  */
1053 static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all)
1054 {
1055         struct pci_controller *hose = pci_bus_to_host(bus);
1056         struct pnv_phb *phb = hose->private_data;
1057         struct pnv_ioda_pe *pe;
1058         int pe_num = IODA_INVALID_PE;
1059
1060         /* Check if PE is determined by M64 */
1061         if (phb->pick_m64_pe)
1062                 pe_num = phb->pick_m64_pe(phb, bus, all);
1063
1064         /* The PE number isn't pinned by M64 */
1065         if (pe_num == IODA_INVALID_PE)
1066                 pe_num = pnv_ioda_alloc_pe(phb);
1067
1068         if (pe_num == IODA_INVALID_PE) {
1069                 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1070                         __func__, pci_domain_nr(bus), bus->number);
1071                 return;
1072         }
1073
1074         pe = &phb->ioda.pe_array[pe_num];
1075         pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1076         pe->pbus = bus;
1077         pe->pdev = NULL;
1078         pe->tce32_seg = -1;
1079         pe->mve_number = -1;
1080         pe->rid = bus->busn_res.start << 8;
1081         pe->dma_weight = 0;
1082
1083         if (all)
1084                 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
1085                         bus->busn_res.start, bus->busn_res.end, pe_num);
1086         else
1087                 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
1088                         bus->busn_res.start, pe_num);
1089
1090         if (pnv_ioda_configure_pe(phb, pe)) {
1091                 /* XXX What do we do here ? */
1092                 if (pe_num)
1093                         pnv_ioda_free_pe(phb, pe_num);
1094                 pe->pbus = NULL;
1095                 return;
1096         }
1097
1098         /* Associate it with all child devices */
1099         pnv_ioda_setup_same_PE(bus, pe);
1100
1101         /* Put PE to the list */
1102         list_add_tail(&pe->list, &phb->ioda.pe_list);
1103
1104         /* Account for one DMA PE if at least one DMA capable device exist
1105          * below the bridge
1106          */
1107         if (pe->dma_weight != 0) {
1108                 phb->ioda.dma_weight += pe->dma_weight;
1109                 phb->ioda.dma_pe_count++;
1110         }
1111
1112         /* Link the PE */
1113         pnv_ioda_link_pe_by_weight(phb, pe);
1114 }
1115
1116 static void pnv_ioda_setup_PEs(struct pci_bus *bus)
1117 {
1118         struct pci_dev *dev;
1119
1120         pnv_ioda_setup_bus_PE(bus, 0);
1121
1122         list_for_each_entry(dev, &bus->devices, bus_list) {
1123                 if (dev->subordinate) {
1124                         if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
1125                                 pnv_ioda_setup_bus_PE(dev->subordinate, 1);
1126                         else
1127                                 pnv_ioda_setup_PEs(dev->subordinate);
1128                 }
1129         }
1130 }
1131
1132 /*
1133  * Configure PEs so that the downstream PCI buses and devices
1134  * could have their associated PE#. Unfortunately, we didn't
1135  * figure out the way to identify the PLX bridge yet. So we
1136  * simply put the PCI bus and the subordinate behind the root
1137  * port to PE# here. The game rule here is expected to be changed
1138  * as soon as we can detected PLX bridge correctly.
1139  */
1140 static void pnv_pci_ioda_setup_PEs(void)
1141 {
1142         struct pci_controller *hose, *tmp;
1143         struct pnv_phb *phb;
1144
1145         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1146                 phb = hose->private_data;
1147
1148                 /* M64 layout might affect PE allocation */
1149                 if (phb->reserve_m64_pe)
1150                         phb->reserve_m64_pe(phb);
1151
1152                 pnv_ioda_setup_PEs(hose->bus);
1153         }
1154 }
1155
1156 #ifdef CONFIG_PCI_IOV
1157 static int pnv_pci_vf_release_m64(struct pci_dev *pdev)
1158 {
1159         struct pci_bus        *bus;
1160         struct pci_controller *hose;
1161         struct pnv_phb        *phb;
1162         struct pci_dn         *pdn;
1163         int                    i, j;
1164
1165         bus = pdev->bus;
1166         hose = pci_bus_to_host(bus);
1167         phb = hose->private_data;
1168         pdn = pci_get_pdn(pdev);
1169
1170         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1171                 for (j = 0; j < M64_PER_IOV; j++) {
1172                         if (pdn->m64_wins[i][j] == IODA_INVALID_M64)
1173                                 continue;
1174                         opal_pci_phb_mmio_enable(phb->opal_id,
1175                                 OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 0);
1176                         clear_bit(pdn->m64_wins[i][j], &phb->ioda.m64_bar_alloc);
1177                         pdn->m64_wins[i][j] = IODA_INVALID_M64;
1178                 }
1179
1180         return 0;
1181 }
1182
1183 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1184 {
1185         struct pci_bus        *bus;
1186         struct pci_controller *hose;
1187         struct pnv_phb        *phb;
1188         struct pci_dn         *pdn;
1189         unsigned int           win;
1190         struct resource       *res;
1191         int                    i, j;
1192         int64_t                rc;
1193         int                    total_vfs;
1194         resource_size_t        size, start;
1195         int                    pe_num;
1196         int                    vf_groups;
1197         int                    vf_per_group;
1198
1199         bus = pdev->bus;
1200         hose = pci_bus_to_host(bus);
1201         phb = hose->private_data;
1202         pdn = pci_get_pdn(pdev);
1203         total_vfs = pci_sriov_get_totalvfs(pdev);
1204
1205         /* Initialize the m64_wins to IODA_INVALID_M64 */
1206         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1207                 for (j = 0; j < M64_PER_IOV; j++)
1208                         pdn->m64_wins[i][j] = IODA_INVALID_M64;
1209
1210         if (pdn->m64_per_iov == M64_PER_IOV) {
1211                 vf_groups = (num_vfs <= M64_PER_IOV) ? num_vfs: M64_PER_IOV;
1212                 vf_per_group = (num_vfs <= M64_PER_IOV)? 1:
1213                         roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1214         } else {
1215                 vf_groups = 1;
1216                 vf_per_group = 1;
1217         }
1218
1219         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1220                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1221                 if (!res->flags || !res->parent)
1222                         continue;
1223
1224                 if (!pnv_pci_is_mem_pref_64(res->flags))
1225                         continue;
1226
1227                 for (j = 0; j < vf_groups; j++) {
1228                         do {
1229                                 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1230                                                 phb->ioda.m64_bar_idx + 1, 0);
1231
1232                                 if (win >= phb->ioda.m64_bar_idx + 1)
1233                                         goto m64_failed;
1234                         } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1235
1236                         pdn->m64_wins[i][j] = win;
1237
1238                         if (pdn->m64_per_iov == M64_PER_IOV) {
1239                                 size = pci_iov_resource_size(pdev,
1240                                                         PCI_IOV_RESOURCES + i);
1241                                 size = size * vf_per_group;
1242                                 start = res->start + size * j;
1243                         } else {
1244                                 size = resource_size(res);
1245                                 start = res->start;
1246                         }
1247
1248                         /* Map the M64 here */
1249                         if (pdn->m64_per_iov == M64_PER_IOV) {
1250                                 pe_num = pdn->offset + j;
1251                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1252                                                 pe_num, OPAL_M64_WINDOW_TYPE,
1253                                                 pdn->m64_wins[i][j], 0);
1254                         }
1255
1256                         rc = opal_pci_set_phb_mem_window(phb->opal_id,
1257                                                  OPAL_M64_WINDOW_TYPE,
1258                                                  pdn->m64_wins[i][j],
1259                                                  start,
1260                                                  0, /* unused */
1261                                                  size);
1262
1263
1264                         if (rc != OPAL_SUCCESS) {
1265                                 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1266                                         win, rc);
1267                                 goto m64_failed;
1268                         }
1269
1270                         if (pdn->m64_per_iov == M64_PER_IOV)
1271                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1272                                      OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 2);
1273                         else
1274                                 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1275                                      OPAL_M64_WINDOW_TYPE, pdn->m64_wins[i][j], 1);
1276
1277                         if (rc != OPAL_SUCCESS) {
1278                                 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1279                                         win, rc);
1280                                 goto m64_failed;
1281                         }
1282                 }
1283         }
1284         return 0;
1285
1286 m64_failed:
1287         pnv_pci_vf_release_m64(pdev);
1288         return -EBUSY;
1289 }
1290
1291 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1292                 int num);
1293 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1294
1295 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1296 {
1297         struct iommu_table    *tbl;
1298         int64_t               rc;
1299
1300         tbl = pe->table_group.tables[0];
1301         rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1302         if (rc)
1303                 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1304
1305         pnv_pci_ioda2_set_bypass(pe, false);
1306         if (pe->table_group.group) {
1307                 iommu_group_put(pe->table_group.group);
1308                 BUG_ON(pe->table_group.group);
1309         }
1310         pnv_pci_ioda2_table_free_pages(tbl);
1311         iommu_free_table(tbl, of_node_full_name(dev->dev.of_node));
1312 }
1313
1314 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1315 {
1316         struct pci_bus        *bus;
1317         struct pci_controller *hose;
1318         struct pnv_phb        *phb;
1319         struct pnv_ioda_pe    *pe, *pe_n;
1320         struct pci_dn         *pdn;
1321         u16                    vf_index;
1322         int64_t                rc;
1323
1324         bus = pdev->bus;
1325         hose = pci_bus_to_host(bus);
1326         phb = hose->private_data;
1327         pdn = pci_get_pdn(pdev);
1328
1329         if (!pdev->is_physfn)
1330                 return;
1331
1332         if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) {
1333                 int   vf_group;
1334                 int   vf_per_group;
1335                 int   vf_index1;
1336
1337                 vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1338
1339                 for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++)
1340                         for (vf_index = vf_group * vf_per_group;
1341                                 vf_index < (vf_group + 1) * vf_per_group &&
1342                                 vf_index < num_vfs;
1343                                 vf_index++)
1344                                 for (vf_index1 = vf_group * vf_per_group;
1345                                         vf_index1 < (vf_group + 1) * vf_per_group &&
1346                                         vf_index1 < num_vfs;
1347                                         vf_index1++){
1348
1349                                         rc = opal_pci_set_peltv(phb->opal_id,
1350                                                 pdn->offset + vf_index,
1351                                                 pdn->offset + vf_index1,
1352                                                 OPAL_REMOVE_PE_FROM_DOMAIN);
1353
1354                                         if (rc)
1355                                             dev_warn(&pdev->dev, "%s: Failed to unlink same group PE#%d(%lld)\n",
1356                                                 __func__,
1357                                                 pdn->offset + vf_index1, rc);
1358                                 }
1359         }
1360
1361         list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1362                 if (pe->parent_dev != pdev)
1363                         continue;
1364
1365                 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1366
1367                 /* Remove from list */
1368                 mutex_lock(&phb->ioda.pe_list_mutex);
1369                 list_del(&pe->list);
1370                 mutex_unlock(&phb->ioda.pe_list_mutex);
1371
1372                 pnv_ioda_deconfigure_pe(phb, pe);
1373
1374                 pnv_ioda_free_pe(phb, pe->pe_number);
1375         }
1376 }
1377
1378 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1379 {
1380         struct pci_bus        *bus;
1381         struct pci_controller *hose;
1382         struct pnv_phb        *phb;
1383         struct pci_dn         *pdn;
1384         struct pci_sriov      *iov;
1385         u16 num_vfs;
1386
1387         bus = pdev->bus;
1388         hose = pci_bus_to_host(bus);
1389         phb = hose->private_data;
1390         pdn = pci_get_pdn(pdev);
1391         iov = pdev->sriov;
1392         num_vfs = pdn->num_vfs;
1393
1394         /* Release VF PEs */
1395         pnv_ioda_release_vf_PE(pdev, num_vfs);
1396
1397         if (phb->type == PNV_PHB_IODA2) {
1398                 if (pdn->m64_per_iov == 1)
1399                         pnv_pci_vf_resource_shift(pdev, -pdn->offset);
1400
1401                 /* Release M64 windows */
1402                 pnv_pci_vf_release_m64(pdev);
1403
1404                 /* Release PE numbers */
1405                 bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1406                 pdn->offset = 0;
1407         }
1408 }
1409
1410 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1411                                        struct pnv_ioda_pe *pe);
1412 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1413 {
1414         struct pci_bus        *bus;
1415         struct pci_controller *hose;
1416         struct pnv_phb        *phb;
1417         struct pnv_ioda_pe    *pe;
1418         int                    pe_num;
1419         u16                    vf_index;
1420         struct pci_dn         *pdn;
1421         int64_t                rc;
1422
1423         bus = pdev->bus;
1424         hose = pci_bus_to_host(bus);
1425         phb = hose->private_data;
1426         pdn = pci_get_pdn(pdev);
1427
1428         if (!pdev->is_physfn)
1429                 return;
1430
1431         /* Reserve PE for each VF */
1432         for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1433                 pe_num = pdn->offset + vf_index;
1434
1435                 pe = &phb->ioda.pe_array[pe_num];
1436                 pe->pe_number = pe_num;
1437                 pe->phb = phb;
1438                 pe->flags = PNV_IODA_PE_VF;
1439                 pe->pbus = NULL;
1440                 pe->parent_dev = pdev;
1441                 pe->tce32_seg = -1;
1442                 pe->mve_number = -1;
1443                 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1444                            pci_iov_virtfn_devfn(pdev, vf_index);
1445
1446                 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1447                         hose->global_number, pdev->bus->number,
1448                         PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1449                         PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1450
1451                 if (pnv_ioda_configure_pe(phb, pe)) {
1452                         /* XXX What do we do here ? */
1453                         if (pe_num)
1454                                 pnv_ioda_free_pe(phb, pe_num);
1455                         pe->pdev = NULL;
1456                         continue;
1457                 }
1458
1459                 /* Put PE to the list */
1460                 mutex_lock(&phb->ioda.pe_list_mutex);
1461                 list_add_tail(&pe->list, &phb->ioda.pe_list);
1462                 mutex_unlock(&phb->ioda.pe_list_mutex);
1463
1464                 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1465         }
1466
1467         if (pdn->m64_per_iov == M64_PER_IOV && num_vfs > M64_PER_IOV) {
1468                 int   vf_group;
1469                 int   vf_per_group;
1470                 int   vf_index1;
1471
1472                 vf_per_group = roundup_pow_of_two(num_vfs) / pdn->m64_per_iov;
1473
1474                 for (vf_group = 0; vf_group < M64_PER_IOV; vf_group++) {
1475                         for (vf_index = vf_group * vf_per_group;
1476                              vf_index < (vf_group + 1) * vf_per_group &&
1477                              vf_index < num_vfs;
1478                              vf_index++) {
1479                                 for (vf_index1 = vf_group * vf_per_group;
1480                                      vf_index1 < (vf_group + 1) * vf_per_group &&
1481                                      vf_index1 < num_vfs;
1482                                      vf_index1++) {
1483
1484                                         rc = opal_pci_set_peltv(phb->opal_id,
1485                                                 pdn->offset + vf_index,
1486                                                 pdn->offset + vf_index1,
1487                                                 OPAL_ADD_PE_TO_DOMAIN);
1488
1489                                         if (rc)
1490                                             dev_warn(&pdev->dev, "%s: Failed to link same group PE#%d(%lld)\n",
1491                                                 __func__,
1492                                                 pdn->offset + vf_index1, rc);
1493                                 }
1494                         }
1495                 }
1496         }
1497 }
1498
1499 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1500 {
1501         struct pci_bus        *bus;
1502         struct pci_controller *hose;
1503         struct pnv_phb        *phb;
1504         struct pci_dn         *pdn;
1505         int                    ret;
1506
1507         bus = pdev->bus;
1508         hose = pci_bus_to_host(bus);
1509         phb = hose->private_data;
1510         pdn = pci_get_pdn(pdev);
1511
1512         if (phb->type == PNV_PHB_IODA2) {
1513                 /* Calculate available PE for required VFs */
1514                 mutex_lock(&phb->ioda.pe_alloc_mutex);
1515                 pdn->offset = bitmap_find_next_zero_area(
1516                         phb->ioda.pe_alloc, phb->ioda.total_pe,
1517                         0, num_vfs, 0);
1518                 if (pdn->offset >= phb->ioda.total_pe) {
1519                         mutex_unlock(&phb->ioda.pe_alloc_mutex);
1520                         dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1521                         pdn->offset = 0;
1522                         return -EBUSY;
1523                 }
1524                 bitmap_set(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1525                 pdn->num_vfs = num_vfs;
1526                 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1527
1528                 /* Assign M64 window accordingly */
1529                 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1530                 if (ret) {
1531                         dev_info(&pdev->dev, "Not enough M64 window resources\n");
1532                         goto m64_failed;
1533                 }
1534
1535                 /*
1536                  * When using one M64 BAR to map one IOV BAR, we need to shift
1537                  * the IOV BAR according to the PE# allocated to the VFs.
1538                  * Otherwise, the PE# for the VF will conflict with others.
1539                  */
1540                 if (pdn->m64_per_iov == 1) {
1541                         ret = pnv_pci_vf_resource_shift(pdev, pdn->offset);
1542                         if (ret)
1543                                 goto m64_failed;
1544                 }
1545         }
1546
1547         /* Setup VF PEs */
1548         pnv_ioda_setup_vf_PE(pdev, num_vfs);
1549
1550         return 0;
1551
1552 m64_failed:
1553         bitmap_clear(phb->ioda.pe_alloc, pdn->offset, num_vfs);
1554         pdn->offset = 0;
1555
1556         return ret;
1557 }
1558
1559 int pcibios_sriov_disable(struct pci_dev *pdev)
1560 {
1561         pnv_pci_sriov_disable(pdev);
1562
1563         /* Release PCI data */
1564         remove_dev_pci_data(pdev);
1565         return 0;
1566 }
1567
1568 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1569 {
1570         /* Allocate PCI data */
1571         add_dev_pci_data(pdev);
1572
1573         pnv_pci_sriov_enable(pdev, num_vfs);
1574         return 0;
1575 }
1576 #endif /* CONFIG_PCI_IOV */
1577
1578 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1579 {
1580         struct pci_dn *pdn = pci_get_pdn(pdev);
1581         struct pnv_ioda_pe *pe;
1582
1583         /*
1584          * The function can be called while the PE#
1585          * hasn't been assigned. Do nothing for the
1586          * case.
1587          */
1588         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1589                 return;
1590
1591         pe = &phb->ioda.pe_array[pdn->pe_number];
1592         WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1593         set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1594         /*
1595          * Note: iommu_add_device() will fail here as
1596          * for physical PE: the device is already added by now;
1597          * for virtual PE: sysfs entries are not ready yet and
1598          * tce_iommu_bus_notifier will add the device to a group later.
1599          */
1600 }
1601
1602 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1603 {
1604         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1605         struct pnv_phb *phb = hose->private_data;
1606         struct pci_dn *pdn = pci_get_pdn(pdev);
1607         struct pnv_ioda_pe *pe;
1608         uint64_t top;
1609         bool bypass = false;
1610
1611         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1612                 return -ENODEV;;
1613
1614         pe = &phb->ioda.pe_array[pdn->pe_number];
1615         if (pe->tce_bypass_enabled) {
1616                 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1617                 bypass = (dma_mask >= top);
1618         }
1619
1620         if (bypass) {
1621                 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1622                 set_dma_ops(&pdev->dev, &dma_direct_ops);
1623                 set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1624         } else {
1625                 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1626                 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1627                 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1628         }
1629         *pdev->dev.dma_mask = dma_mask;
1630         return 0;
1631 }
1632
1633 static u64 pnv_pci_ioda_dma_get_required_mask(struct pnv_phb *phb,
1634                                               struct pci_dev *pdev)
1635 {
1636         struct pci_dn *pdn = pci_get_pdn(pdev);
1637         struct pnv_ioda_pe *pe;
1638         u64 end, mask;
1639
1640         if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1641                 return 0;
1642
1643         pe = &phb->ioda.pe_array[pdn->pe_number];
1644         if (!pe->tce_bypass_enabled)
1645                 return __dma_get_required_mask(&pdev->dev);
1646
1647
1648         end = pe->tce_bypass_base + memblock_end_of_DRAM();
1649         mask = 1ULL << (fls64(end) - 1);
1650         mask += mask - 1;
1651
1652         return mask;
1653 }
1654
1655 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1656                                    struct pci_bus *bus)
1657 {
1658         struct pci_dev *dev;
1659
1660         list_for_each_entry(dev, &bus->devices, bus_list) {
1661                 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1662                 iommu_add_device(&dev->dev);
1663
1664                 if (dev->subordinate)
1665                         pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1666         }
1667 }
1668
1669 static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
1670                 unsigned long index, unsigned long npages, bool rm)
1671 {
1672         struct iommu_table_group_link *tgl = list_first_entry_or_null(
1673                         &tbl->it_group_list, struct iommu_table_group_link,
1674                         next);
1675         struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1676                         struct pnv_ioda_pe, table_group);
1677         __be64 __iomem *invalidate = rm ?
1678                 (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1679                 pe->phb->ioda.tce_inval_reg;
1680         unsigned long start, end, inc;
1681         const unsigned shift = tbl->it_page_shift;
1682
1683         start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1684         end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1685                         npages - 1);
1686
1687         /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
1688         if (tbl->it_busno) {
1689                 start <<= shift;
1690                 end <<= shift;
1691                 inc = 128ull << shift;
1692                 start |= tbl->it_busno;
1693                 end |= tbl->it_busno;
1694         } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
1695                 /* p7ioc-style invalidation, 2 TCEs per write */
1696                 start |= (1ull << 63);
1697                 end |= (1ull << 63);
1698                 inc = 16;
1699         } else {
1700                 /* Default (older HW) */
1701                 inc = 128;
1702         }
1703
1704         end |= inc - 1; /* round up end to be different than start */
1705
1706         mb(); /* Ensure above stores are visible */
1707         while (start <= end) {
1708                 if (rm)
1709                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1710                 else
1711                         __raw_writeq(cpu_to_be64(start), invalidate);
1712                 start += inc;
1713         }
1714
1715         /*
1716          * The iommu layer will do another mb() for us on build()
1717          * and we don't care on free()
1718          */
1719 }
1720
1721 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1722                 long npages, unsigned long uaddr,
1723                 enum dma_data_direction direction,
1724                 struct dma_attrs *attrs)
1725 {
1726         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1727                         attrs);
1728
1729         if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1730                 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1731
1732         return ret;
1733 }
1734
1735 #ifdef CONFIG_IOMMU_API
1736 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1737                 unsigned long *hpa, enum dma_data_direction *direction)
1738 {
1739         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1740
1741         if (!ret && (tbl->it_type &
1742                         (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1743                 pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false);
1744
1745         return ret;
1746 }
1747 #endif
1748
1749 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1750                 long npages)
1751 {
1752         pnv_tce_free(tbl, index, npages);
1753
1754         if (tbl->it_type & TCE_PCI_SWINV_FREE)
1755                 pnv_pci_ioda1_tce_invalidate(tbl, index, npages, false);
1756 }
1757
1758 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1759         .set = pnv_ioda1_tce_build,
1760 #ifdef CONFIG_IOMMU_API
1761         .exchange = pnv_ioda1_tce_xchg,
1762 #endif
1763         .clear = pnv_ioda1_tce_free,
1764         .get = pnv_tce_get,
1765 };
1766
1767 static inline void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_ioda_pe *pe)
1768 {
1769         /* 01xb - invalidate TCEs that match the specified PE# */
1770         unsigned long val = (0x4ull << 60) | (pe->pe_number & 0xFF);
1771         struct pnv_phb *phb = pe->phb;
1772
1773         if (!phb->ioda.tce_inval_reg)
1774                 return;
1775
1776         mb(); /* Ensure above stores are visible */
1777         __raw_writeq(cpu_to_be64(val), phb->ioda.tce_inval_reg);
1778 }
1779
1780 static void pnv_pci_ioda2_do_tce_invalidate(unsigned pe_number, bool rm,
1781                 __be64 __iomem *invalidate, unsigned shift,
1782                 unsigned long index, unsigned long npages)
1783 {
1784         unsigned long start, end, inc;
1785
1786         /* We'll invalidate DMA address in PE scope */
1787         start = 0x2ull << 60;
1788         start |= (pe_number & 0xFF);
1789         end = start;
1790
1791         /* Figure out the start, end and step */
1792         start |= (index << shift);
1793         end |= ((index + npages - 1) << shift);
1794         inc = (0x1ull << shift);
1795         mb();
1796
1797         while (start <= end) {
1798                 if (rm)
1799                         __raw_rm_writeq(cpu_to_be64(start), invalidate);
1800                 else
1801                         __raw_writeq(cpu_to_be64(start), invalidate);
1802                 start += inc;
1803         }
1804 }
1805
1806 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1807                 unsigned long index, unsigned long npages, bool rm)
1808 {
1809         struct iommu_table_group_link *tgl;
1810
1811         list_for_each_entry_rcu(tgl, &tbl->it_group_list, next) {
1812                 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1813                                 struct pnv_ioda_pe, table_group);
1814                 __be64 __iomem *invalidate = rm ?
1815                         (__be64 __iomem *)pe->phb->ioda.tce_inval_reg_phys :
1816                         pe->phb->ioda.tce_inval_reg;
1817
1818                 pnv_pci_ioda2_do_tce_invalidate(pe->pe_number, rm,
1819                         invalidate, tbl->it_page_shift,
1820                         index, npages);
1821         }
1822 }
1823
1824 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1825                 long npages, unsigned long uaddr,
1826                 enum dma_data_direction direction,
1827                 struct dma_attrs *attrs)
1828 {
1829         int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1830                         attrs);
1831
1832         if (!ret && (tbl->it_type & TCE_PCI_SWINV_CREATE))
1833                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1834
1835         return ret;
1836 }
1837
1838 #ifdef CONFIG_IOMMU_API
1839 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
1840                 unsigned long *hpa, enum dma_data_direction *direction)
1841 {
1842         long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1843
1844         if (!ret && (tbl->it_type &
1845                         (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))
1846                 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
1847
1848         return ret;
1849 }
1850 #endif
1851
1852 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1853                 long npages)
1854 {
1855         pnv_tce_free(tbl, index, npages);
1856
1857         if (tbl->it_type & TCE_PCI_SWINV_FREE)
1858                 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
1859 }
1860
1861 static void pnv_ioda2_table_free(struct iommu_table *tbl)
1862 {
1863         pnv_pci_ioda2_table_free_pages(tbl);
1864         iommu_free_table(tbl, "pnv");
1865 }
1866
1867 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
1868         .set = pnv_ioda2_tce_build,
1869 #ifdef CONFIG_IOMMU_API
1870         .exchange = pnv_ioda2_tce_xchg,
1871 #endif
1872         .clear = pnv_ioda2_tce_free,
1873         .get = pnv_tce_get,
1874         .free = pnv_ioda2_table_free,
1875 };
1876
1877 static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
1878                                       struct pnv_ioda_pe *pe, unsigned int base,
1879                                       unsigned int segs)
1880 {
1881
1882         struct page *tce_mem = NULL;
1883         struct iommu_table *tbl;
1884         unsigned int i;
1885         int64_t rc;
1886         void *addr;
1887
1888         /* XXX FIXME: Handle 64-bit only DMA devices */
1889         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
1890         /* XXX FIXME: Allocate multi-level tables on PHB3 */
1891
1892         /* We shouldn't already have a 32-bit DMA associated */
1893         if (WARN_ON(pe->tce32_seg >= 0))
1894                 return;
1895
1896         tbl = pnv_pci_table_alloc(phb->hose->node);
1897         iommu_register_group(&pe->table_group, phb->hose->global_number,
1898                         pe->pe_number);
1899         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
1900
1901         /* Grab a 32-bit TCE table */
1902         pe->tce32_seg = base;
1903         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
1904                 (base << 28), ((base + segs) << 28) - 1);
1905
1906         /* XXX Currently, we allocate one big contiguous table for the
1907          * TCEs. We only really need one chunk per 256M of TCE space
1908          * (ie per segment) but that's an optimization for later, it
1909          * requires some added smarts with our get/put_tce implementation
1910          */
1911         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
1912                                    get_order(TCE32_TABLE_SIZE * segs));
1913         if (!tce_mem) {
1914                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
1915                 goto fail;
1916         }
1917         addr = page_address(tce_mem);
1918         memset(addr, 0, TCE32_TABLE_SIZE * segs);
1919
1920         /* Configure HW */
1921         for (i = 0; i < segs; i++) {
1922                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
1923                                               pe->pe_number,
1924                                               base + i, 1,
1925                                               __pa(addr) + TCE32_TABLE_SIZE * i,
1926                                               TCE32_TABLE_SIZE, 0x1000);
1927                 if (rc) {
1928                         pe_err(pe, " Failed to configure 32-bit TCE table,"
1929                                " err %ld\n", rc);
1930                         goto fail;
1931                 }
1932         }
1933
1934         /* Setup linux iommu table */
1935         pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
1936                                   base << 28, IOMMU_PAGE_SHIFT_4K);
1937
1938         /* OPAL variant of P7IOC SW invalidated TCEs */
1939         if (phb->ioda.tce_inval_reg)
1940                 tbl->it_type |= (TCE_PCI_SWINV_CREATE |
1941                                  TCE_PCI_SWINV_FREE   |
1942                                  TCE_PCI_SWINV_PAIR);
1943
1944         tbl->it_ops = &pnv_ioda1_iommu_ops;
1945         pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
1946         pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
1947         iommu_init_table(tbl, phb->hose->node);
1948
1949         if (pe->flags & PNV_IODA_PE_DEV) {
1950                 /*
1951                  * Setting table base here only for carrying iommu_group
1952                  * further down to let iommu_add_device() do the job.
1953                  * pnv_pci_ioda_dma_dev_setup will override it later anyway.
1954                  */
1955                 set_iommu_table_base(&pe->pdev->dev, tbl);
1956                 iommu_add_device(&pe->pdev->dev);
1957         } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
1958                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
1959
1960         return;
1961  fail:
1962         /* XXX Failure: Try to fallback to 64-bit only ? */
1963         if (pe->tce32_seg >= 0)
1964                 pe->tce32_seg = -1;
1965         if (tce_mem)
1966                 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
1967         if (tbl) {
1968                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
1969                 iommu_free_table(tbl, "pnv");
1970         }
1971 }
1972
1973 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
1974                 int num, struct iommu_table *tbl)
1975 {
1976         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1977                         table_group);
1978         struct pnv_phb *phb = pe->phb;
1979         int64_t rc;
1980         const unsigned long size = tbl->it_indirect_levels ?
1981                         tbl->it_level_size : tbl->it_size;
1982         const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
1983         const __u64 win_size = tbl->it_size << tbl->it_page_shift;
1984
1985         pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
1986                         start_addr, start_addr + win_size - 1,
1987                         IOMMU_PAGE_SIZE(tbl));
1988
1989         /*
1990          * Map TCE table through TVT. The TVE index is the PE number
1991          * shifted by 1 bit for 32-bits DMA space.
1992          */
1993         rc = opal_pci_map_pe_dma_window(phb->opal_id,
1994                         pe->pe_number,
1995                         (pe->pe_number << 1) + num,
1996                         tbl->it_indirect_levels + 1,
1997                         __pa(tbl->it_base),
1998                         size << 3,
1999                         IOMMU_PAGE_SIZE(tbl));
2000         if (rc) {
2001                 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2002                 return rc;
2003         }
2004
2005         pnv_pci_link_table_and_group(phb->hose->node, num,
2006                         tbl, &pe->table_group);
2007         pnv_pci_ioda2_tce_invalidate_entire(pe);
2008
2009         return 0;
2010 }
2011
2012 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2013 {
2014         uint16_t window_id = (pe->pe_number << 1 ) + 1;
2015         int64_t rc;
2016
2017         pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2018         if (enable) {
2019                 phys_addr_t top = memblock_end_of_DRAM();
2020
2021                 top = roundup_pow_of_two(top);
2022                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2023                                                      pe->pe_number,
2024                                                      window_id,
2025                                                      pe->tce_bypass_base,
2026                                                      top);
2027         } else {
2028                 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2029                                                      pe->pe_number,
2030                                                      window_id,
2031                                                      pe->tce_bypass_base,
2032                                                      0);
2033         }
2034         if (rc)
2035                 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2036         else
2037                 pe->tce_bypass_enabled = enable;
2038 }
2039
2040 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2041                 __u32 page_shift, __u64 window_size, __u32 levels,
2042                 struct iommu_table *tbl);
2043
2044 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2045                 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2046                 struct iommu_table **ptbl)
2047 {
2048         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2049                         table_group);
2050         int nid = pe->phb->hose->node;
2051         __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2052         long ret;
2053         struct iommu_table *tbl;
2054
2055         tbl = pnv_pci_table_alloc(nid);
2056         if (!tbl)
2057                 return -ENOMEM;
2058
2059         ret = pnv_pci_ioda2_table_alloc_pages(nid,
2060                         bus_offset, page_shift, window_size,
2061                         levels, tbl);
2062         if (ret) {
2063                 iommu_free_table(tbl, "pnv");
2064                 return ret;
2065         }
2066
2067         tbl->it_ops = &pnv_ioda2_iommu_ops;
2068         if (pe->phb->ioda.tce_inval_reg)
2069                 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2070
2071         *ptbl = tbl;
2072
2073         return 0;
2074 }
2075
2076 #ifdef CONFIG_IOMMU_API
2077 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2078                 __u64 window_size, __u32 levels)
2079 {
2080         unsigned long bytes = 0;
2081         const unsigned window_shift = ilog2(window_size);
2082         unsigned entries_shift = window_shift - page_shift;
2083         unsigned table_shift = entries_shift + 3;
2084         unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2085         unsigned long direct_table_size;
2086
2087         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2088                         (window_size > memory_hotplug_max()) ||
2089                         !is_power_of_2(window_size))
2090                 return 0;
2091
2092         /* Calculate a direct table size from window_size and levels */
2093         entries_shift = (entries_shift + levels - 1) / levels;
2094         table_shift = entries_shift + 3;
2095         table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2096         direct_table_size =  1UL << table_shift;
2097
2098         for ( ; levels; --levels) {
2099                 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2100
2101                 tce_table_size /= direct_table_size;
2102                 tce_table_size <<= 3;
2103                 tce_table_size = _ALIGN_UP(tce_table_size, direct_table_size);
2104         }
2105
2106         return bytes;
2107 }
2108
2109 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2110                 int num)
2111 {
2112         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2113                         table_group);
2114         struct pnv_phb *phb = pe->phb;
2115         long ret;
2116
2117         pe_info(pe, "Removing DMA window #%d\n", num);
2118
2119         ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2120                         (pe->pe_number << 1) + num,
2121                         0/* levels */, 0/* table address */,
2122                         0/* table size */, 0/* page size */);
2123         if (ret)
2124                 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2125         else
2126                 pnv_pci_ioda2_tce_invalidate_entire(pe);
2127
2128         pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2129
2130         return ret;
2131 }
2132
2133 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2134 {
2135         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2136                                                 table_group);
2137
2138         iommu_take_ownership(table_group->tables[0]);
2139         pnv_pci_ioda2_set_bypass(pe, false);
2140 }
2141
2142 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2143 {
2144         struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2145                                                 table_group);
2146
2147         iommu_release_ownership(table_group->tables[0]);
2148         pnv_pci_ioda2_set_bypass(pe, true);
2149 }
2150
2151 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2152         .get_table_size = pnv_pci_ioda2_get_table_size,
2153         .create_table = pnv_pci_ioda2_create_table,
2154         .set_window = pnv_pci_ioda2_set_window,
2155         .unset_window = pnv_pci_ioda2_unset_window,
2156         .take_ownership = pnv_ioda2_take_ownership,
2157         .release_ownership = pnv_ioda2_release_ownership,
2158 };
2159 #endif
2160
2161 static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb)
2162 {
2163         const __be64 *swinvp;
2164
2165         /* OPAL variant of PHB3 invalidated TCEs */
2166         swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
2167         if (!swinvp)
2168                 return;
2169
2170         phb->ioda.tce_inval_reg_phys = be64_to_cpup(swinvp);
2171         phb->ioda.tce_inval_reg = ioremap(phb->ioda.tce_inval_reg_phys, 8);
2172 }
2173
2174 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2175                 unsigned levels, unsigned long limit,
2176                 unsigned long *current_offset)
2177 {
2178         struct page *tce_mem = NULL;
2179         __be64 *addr, *tmp;
2180         unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2181         unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2182         unsigned entries = 1UL << (shift - 3);
2183         long i;
2184
2185         tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2186         if (!tce_mem) {
2187                 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2188                 return NULL;
2189         }
2190         addr = page_address(tce_mem);
2191         memset(addr, 0, allocated);
2192
2193         --levels;
2194         if (!levels) {
2195                 *current_offset += allocated;
2196                 return addr;
2197         }
2198
2199         for (i = 0; i < entries; ++i) {
2200                 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2201                                 levels, limit, current_offset);
2202                 if (!tmp)
2203                         break;
2204
2205                 addr[i] = cpu_to_be64(__pa(tmp) |
2206                                 TCE_PCI_READ | TCE_PCI_WRITE);
2207
2208                 if (*current_offset >= limit)
2209                         break;
2210         }
2211
2212         return addr;
2213 }
2214
2215 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2216                 unsigned long size, unsigned level);
2217
2218 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2219                 __u32 page_shift, __u64 window_size, __u32 levels,
2220                 struct iommu_table *tbl)
2221 {
2222         void *addr;
2223         unsigned long offset = 0, level_shift;
2224         const unsigned window_shift = ilog2(window_size);
2225         unsigned entries_shift = window_shift - page_shift;
2226         unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2227         const unsigned long tce_table_size = 1UL << table_shift;
2228
2229         if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2230                 return -EINVAL;
2231
2232         if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2233                 return -EINVAL;
2234
2235         /* Adjust direct table size from window_size and levels */
2236         entries_shift = (entries_shift + levels - 1) / levels;
2237         level_shift = entries_shift + 3;
2238         level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2239
2240         /* Allocate TCE table */
2241         addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2242                         levels, tce_table_size, &offset);
2243
2244         /* addr==NULL means that the first level allocation failed */
2245         if (!addr)
2246                 return -ENOMEM;
2247
2248         /*
2249          * First level was allocated but some lower level failed as
2250          * we did not allocate as much as we wanted,
2251          * release partially allocated table.
2252          */
2253         if (offset < tce_table_size) {
2254                 pnv_pci_ioda2_table_do_free_pages(addr,
2255                                 1ULL << (level_shift - 3), levels - 1);
2256                 return -ENOMEM;
2257         }
2258
2259         /* Setup linux iommu table */
2260         pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2261                         page_shift);
2262         tbl->it_level_size = 1ULL << (level_shift - 3);
2263         tbl->it_indirect_levels = levels - 1;
2264         tbl->it_allocated_size = offset;
2265
2266         pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2267                         window_size, tce_table_size, bus_offset);
2268
2269         return 0;
2270 }
2271
2272 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2273                 unsigned long size, unsigned level)
2274 {
2275         const unsigned long addr_ul = (unsigned long) addr &
2276                         ~(TCE_PCI_READ | TCE_PCI_WRITE);
2277
2278         if (level) {
2279                 long i;
2280                 u64 *tmp = (u64 *) addr_ul;
2281
2282                 for (i = 0; i < size; ++i) {
2283                         unsigned long hpa = be64_to_cpu(tmp[i]);
2284
2285                         if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2286                                 continue;
2287
2288                         pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2289                                         level - 1);
2290                 }
2291         }
2292
2293         free_pages(addr_ul, get_order(size << 3));
2294 }
2295
2296 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2297 {
2298         const unsigned long size = tbl->it_indirect_levels ?
2299                         tbl->it_level_size : tbl->it_size;
2300
2301         if (!tbl->it_size)
2302                 return;
2303
2304         pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2305                         tbl->it_indirect_levels);
2306 }
2307
2308 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2309                                        struct pnv_ioda_pe *pe)
2310 {
2311         struct iommu_table *tbl = NULL;
2312         int64_t rc;
2313
2314         /* We shouldn't already have a 32-bit DMA associated */
2315         if (WARN_ON(pe->tce32_seg >= 0))
2316                 return;
2317
2318         /* TVE #1 is selected by PCI address bit 59 */
2319         pe->tce_bypass_base = 1ull << 59;
2320
2321         iommu_register_group(&pe->table_group, phb->hose->global_number,
2322                         pe->pe_number);
2323
2324         /* The PE will reserve all possible 32-bits space */
2325         pe->tce32_seg = 0;
2326         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2327                 phb->ioda.m32_pci_base);
2328
2329         /* Setup linux iommu table */
2330         pe->table_group.tce32_start = 0;
2331         pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2332         pe->table_group.max_dynamic_windows_supported =
2333                         IOMMU_TABLE_GROUP_MAX_TABLES;
2334         pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2335         pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2336
2337         rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2338                         IOMMU_PAGE_SHIFT_4K,
2339                         pe->table_group.tce32_size,
2340                         POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2341         if (rc) {
2342                 pe_err(pe, "Failed to create 32-bit TCE table, err %ld", rc);
2343                 goto fail;
2344         }
2345         pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2346
2347         tbl->it_ops = &pnv_ioda2_iommu_ops;
2348         iommu_init_table(tbl, phb->hose->node);
2349 #ifdef CONFIG_IOMMU_API
2350         pe->table_group.ops = &pnv_pci_ioda2_ops;
2351 #endif
2352
2353         rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2354         if (rc) {
2355                 pe_err(pe, "Failed to configure 32-bit TCE table,"
2356                        " err %ld\n", rc);
2357                 goto fail;
2358         }
2359
2360         /* OPAL variant of PHB3 invalidated TCEs */
2361         if (phb->ioda.tce_inval_reg)
2362                 tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
2363
2364         if (pe->flags & PNV_IODA_PE_DEV) {
2365                 /*
2366                  * Setting table base here only for carrying iommu_group
2367                  * further down to let iommu_add_device() do the job.
2368                  * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2369                  */
2370                 set_iommu_table_base(&pe->pdev->dev, tbl);
2371                 iommu_add_device(&pe->pdev->dev);
2372         } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2373                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2374
2375         /* Also create a bypass window */
2376         if (!pnv_iommu_bypass_disabled)
2377                 pnv_pci_ioda2_set_bypass(pe, true);
2378
2379         return;
2380 fail:
2381         if (pe->tce32_seg >= 0)
2382                 pe->tce32_seg = -1;
2383         if (tbl) {
2384                 pnv_pci_ioda2_table_free_pages(tbl);
2385                 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2386                 iommu_free_table(tbl, "pnv");
2387         }
2388 }
2389
2390 static void pnv_ioda_setup_dma(struct pnv_phb *phb)
2391 {
2392         struct pci_controller *hose = phb->hose;
2393         unsigned int residual, remaining, segs, tw, base;
2394         struct pnv_ioda_pe *pe;
2395
2396         /* If we have more PE# than segments available, hand out one
2397          * per PE until we run out and let the rest fail. If not,
2398          * then we assign at least one segment per PE, plus more based
2399          * on the amount of devices under that PE
2400          */
2401         if (phb->ioda.dma_pe_count > phb->ioda.tce32_count)
2402                 residual = 0;
2403         else
2404                 residual = phb->ioda.tce32_count -
2405                         phb->ioda.dma_pe_count;
2406
2407         pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
2408                 hose->global_number, phb->ioda.tce32_count);
2409         pr_info("PCI: %d PE# for a total weight of %d\n",
2410                 phb->ioda.dma_pe_count, phb->ioda.dma_weight);
2411
2412         pnv_pci_ioda_setup_opal_tce_kill(phb);
2413
2414         /* Walk our PE list and configure their DMA segments, hand them
2415          * out one base segment plus any residual segments based on
2416          * weight
2417          */
2418         remaining = phb->ioda.tce32_count;
2419         tw = phb->ioda.dma_weight;
2420         base = 0;
2421         list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
2422                 if (!pe->dma_weight)
2423                         continue;
2424                 if (!remaining) {
2425                         pe_warn(pe, "No DMA32 resources available\n");
2426                         continue;
2427                 }
2428                 segs = 1;
2429                 if (residual) {
2430                         segs += ((pe->dma_weight * residual)  + (tw / 2)) / tw;
2431                         if (segs > remaining)
2432                                 segs = remaining;
2433                 }
2434
2435                 /*
2436                  * For IODA2 compliant PHB3, we needn't care about the weight.
2437                  * The all available 32-bits DMA space will be assigned to
2438                  * the specific PE.
2439                  */
2440                 if (phb->type == PNV_PHB_IODA1) {
2441                         pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
2442                                 pe->dma_weight, segs);
2443                         pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
2444                 } else {
2445                         pe_info(pe, "Assign DMA32 space\n");
2446                         segs = 0;
2447                         pnv_pci_ioda2_setup_dma_pe(phb, pe);
2448                 }
2449
2450                 remaining -= segs;
2451                 base += segs;
2452         }
2453 }
2454
2455 #ifdef CONFIG_PCI_MSI
2456 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2457 {
2458         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2459         struct irq_chip *chip = irq_data_get_irq_chip(d);
2460         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2461                                            ioda.irq_chip);
2462         int64_t rc;
2463
2464         rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
2465         WARN_ON_ONCE(rc);
2466
2467         icp_native_eoi(d);
2468 }
2469
2470
2471 static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2472 {
2473         struct irq_data *idata;
2474         struct irq_chip *ichip;
2475
2476         if (phb->type != PNV_PHB_IODA2)
2477                 return;
2478
2479         if (!phb->ioda.irq_chip_init) {
2480                 /*
2481                  * First time we setup an MSI IRQ, we need to setup the
2482                  * corresponding IRQ chip to route correctly.
2483                  */
2484                 idata = irq_get_irq_data(virq);
2485                 ichip = irq_data_get_irq_chip(idata);
2486                 phb->ioda.irq_chip_init = 1;
2487                 phb->ioda.irq_chip = *ichip;
2488                 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2489         }
2490         irq_set_chip(virq, &phb->ioda.irq_chip);
2491 }
2492
2493 #ifdef CONFIG_CXL_BASE
2494
2495 struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev)
2496 {
2497         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2498
2499         return of_node_get(hose->dn);
2500 }
2501 EXPORT_SYMBOL(pnv_pci_get_phb_node);
2502
2503 int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
2504 {
2505         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2506         struct pnv_phb *phb = hose->private_data;
2507         struct pnv_ioda_pe *pe;
2508         int rc;
2509
2510         pe = pnv_ioda_get_pe(dev);
2511         if (!pe)
2512                 return -ENODEV;
2513
2514         pe_info(pe, "Switching PHB to CXL\n");
2515
2516         rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
2517         if (rc)
2518                 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
2519
2520         return rc;
2521 }
2522 EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
2523
2524 /* Find PHB for cxl dev and allocate MSI hwirqs?
2525  * Returns the absolute hardware IRQ number
2526  */
2527 int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
2528 {
2529         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2530         struct pnv_phb *phb = hose->private_data;
2531         int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
2532
2533         if (hwirq < 0) {
2534                 dev_warn(&dev->dev, "Failed to find a free MSI\n");
2535                 return -ENOSPC;
2536         }
2537
2538         return phb->msi_base + hwirq;
2539 }
2540 EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
2541
2542 void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
2543 {
2544         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2545         struct pnv_phb *phb = hose->private_data;
2546
2547         msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
2548 }
2549 EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
2550
2551 void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
2552                                   struct pci_dev *dev)
2553 {
2554         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2555         struct pnv_phb *phb = hose->private_data;
2556         int i, hwirq;
2557
2558         for (i = 1; i < CXL_IRQ_RANGES; i++) {
2559                 if (!irqs->range[i])
2560                         continue;
2561                 pr_devel("cxl release irq range 0x%x: offset: 0x%lx  limit: %ld\n",
2562                          i, irqs->offset[i],
2563                          irqs->range[i]);
2564                 hwirq = irqs->offset[i] - phb->msi_base;
2565                 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
2566                                        irqs->range[i]);
2567         }
2568 }
2569 EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
2570
2571 int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
2572                                struct pci_dev *dev, int num)
2573 {
2574         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2575         struct pnv_phb *phb = hose->private_data;
2576         int i, hwirq, try;
2577
2578         memset(irqs, 0, sizeof(struct cxl_irq_ranges));
2579
2580         /* 0 is reserved for the multiplexed PSL DSI interrupt */
2581         for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
2582                 try = num;
2583                 while (try) {
2584                         hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
2585                         if (hwirq >= 0)
2586                                 break;
2587                         try /= 2;
2588                 }
2589                 if (!try)
2590                         goto fail;
2591
2592                 irqs->offset[i] = phb->msi_base + hwirq;
2593                 irqs->range[i] = try;
2594                 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx  limit: %li\n",
2595                          i, irqs->offset[i], irqs->range[i]);
2596                 num -= try;
2597         }
2598         if (num)
2599                 goto fail;
2600
2601         return 0;
2602 fail:
2603         pnv_cxl_release_hwirq_ranges(irqs, dev);
2604         return -ENOSPC;
2605 }
2606 EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
2607
2608 int pnv_cxl_get_irq_count(struct pci_dev *dev)
2609 {
2610         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2611         struct pnv_phb *phb = hose->private_data;
2612
2613         return phb->msi_bmp.irq_count;
2614 }
2615 EXPORT_SYMBOL(pnv_cxl_get_irq_count);
2616
2617 int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
2618                            unsigned int virq)
2619 {
2620         struct pci_controller *hose = pci_bus_to_host(dev->bus);
2621         struct pnv_phb *phb = hose->private_data;
2622         unsigned int xive_num = hwirq - phb->msi_base;
2623         struct pnv_ioda_pe *pe;
2624         int rc;
2625
2626         if (!(pe = pnv_ioda_get_pe(dev)))
2627                 return -ENODEV;
2628
2629         /* Assign XIVE to PE */
2630         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2631         if (rc) {
2632                 pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
2633                         "hwirq 0x%x XIVE 0x%x PE\n",
2634                         pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
2635                 return -EIO;
2636         }
2637         set_msi_irq_chip(phb, virq);
2638
2639         return 0;
2640 }
2641 EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
2642 #endif
2643
2644 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2645                                   unsigned int hwirq, unsigned int virq,
2646                                   unsigned int is_64, struct msi_msg *msg)
2647 {
2648         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2649         unsigned int xive_num = hwirq - phb->msi_base;
2650         __be32 data;
2651         int rc;
2652
2653         /* No PE assigned ? bail out ... no MSI for you ! */
2654         if (pe == NULL)
2655                 return -ENXIO;
2656
2657         /* Check if we have an MVE */
2658         if (pe->mve_number < 0)
2659                 return -ENXIO;
2660
2661         /* Force 32-bit MSI on some broken devices */
2662         if (dev->no_64bit_msi)
2663                 is_64 = 0;
2664
2665         /* Assign XIVE to PE */
2666         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2667         if (rc) {
2668                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2669                         pci_name(dev), rc, xive_num);
2670                 return -EIO;
2671         }
2672
2673         if (is_64) {
2674                 __be64 addr64;
2675
2676                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2677                                      &addr64, &data);
2678                 if (rc) {
2679                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2680                                 pci_name(dev), rc);
2681                         return -EIO;
2682                 }
2683                 msg->address_hi = be64_to_cpu(addr64) >> 32;
2684                 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2685         } else {
2686                 __be32 addr32;
2687
2688                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2689                                      &addr32, &data);
2690                 if (rc) {
2691                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2692                                 pci_name(dev), rc);
2693                         return -EIO;
2694                 }
2695                 msg->address_hi = 0;
2696                 msg->address_lo = be32_to_cpu(addr32);
2697         }
2698         msg->data = be32_to_cpu(data);
2699
2700         set_msi_irq_chip(phb, virq);
2701
2702         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2703                  " address=%x_%08x data=%x PE# %d\n",
2704                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2705                  msg->address_hi, msg->address_lo, data, pe->pe_number);
2706
2707         return 0;
2708 }
2709
2710 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2711 {
2712         unsigned int count;
2713         const __be32 *prop = of_get_property(phb->hose->dn,
2714                                              "ibm,opal-msi-ranges", NULL);
2715         if (!prop) {
2716                 /* BML Fallback */
2717                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2718         }
2719         if (!prop)
2720                 return;
2721
2722         phb->msi_base = be32_to_cpup(prop);
2723         count = be32_to_cpup(prop + 1);
2724         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2725                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2726                        phb->hose->global_number);
2727                 return;
2728         }
2729
2730         phb->msi_setup = pnv_pci_ioda_msi_setup;
2731         phb->msi32_support = 1;
2732         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2733                 count, phb->msi_base);
2734 }
2735 #else
2736 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2737 #endif /* CONFIG_PCI_MSI */
2738
2739 #ifdef CONFIG_PCI_IOV
2740 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2741 {
2742         struct pci_controller *hose;
2743         struct pnv_phb *phb;
2744         struct resource *res;
2745         int i;
2746         resource_size_t size;
2747         struct pci_dn *pdn;
2748         int mul, total_vfs;
2749
2750         if (!pdev->is_physfn || pdev->is_added)
2751                 return;
2752
2753         hose = pci_bus_to_host(pdev->bus);
2754         phb = hose->private_data;
2755
2756         pdn = pci_get_pdn(pdev);
2757         pdn->vfs_expanded = 0;
2758
2759         total_vfs = pci_sriov_get_totalvfs(pdev);
2760         pdn->m64_per_iov = 1;
2761         mul = phb->ioda.total_pe;
2762
2763         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2764                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2765                 if (!res->flags || res->parent)
2766                         continue;
2767                 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2768                         dev_warn(&pdev->dev, " non M64 VF BAR%d: %pR\n",
2769                                  i, res);
2770                         continue;
2771                 }
2772
2773                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2774
2775                 /* bigger than 64M */
2776                 if (size > (1 << 26)) {
2777                         dev_info(&pdev->dev, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n",
2778                                  i, res);
2779                         pdn->m64_per_iov = M64_PER_IOV;
2780                         mul = roundup_pow_of_two(total_vfs);
2781                         break;
2782                 }
2783         }
2784
2785         for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2786                 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2787                 if (!res->flags || res->parent)
2788                         continue;
2789                 if (!pnv_pci_is_mem_pref_64(res->flags)) {
2790                         dev_warn(&pdev->dev, "Skipping expanding VF BAR%d: %pR\n",
2791                                  i, res);
2792                         continue;
2793                 }
2794
2795                 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2796                 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2797                 res->end = res->start + size * mul - 1;
2798                 dev_dbg(&pdev->dev, "                       %pR\n", res);
2799                 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2800                          i, res, mul);
2801         }
2802         pdn->vfs_expanded = mul;
2803 }
2804 #endif /* CONFIG_PCI_IOV */
2805
2806 /*
2807  * This function is supposed to be called on basis of PE from top
2808  * to bottom style. So the the I/O or MMIO segment assigned to
2809  * parent PE could be overrided by its child PEs if necessary.
2810  */
2811 static void pnv_ioda_setup_pe_seg(struct pci_controller *hose,
2812                                   struct pnv_ioda_pe *pe)
2813 {
2814         struct pnv_phb *phb = hose->private_data;
2815         struct pci_bus_region region;
2816         struct resource *res;
2817         int i, index;
2818         int rc;
2819
2820         /*
2821          * NOTE: We only care PCI bus based PE for now. For PCI
2822          * device based PE, for example SRIOV sensitive VF should
2823          * be figured out later.
2824          */
2825         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
2826
2827         pci_bus_for_each_resource(pe->pbus, res, i) {
2828                 if (!res || !res->flags ||
2829                     res->start > res->end)
2830                         continue;
2831
2832                 if (res->flags & IORESOURCE_IO) {
2833                         region.start = res->start - phb->ioda.io_pci_base;
2834                         region.end   = res->end - phb->ioda.io_pci_base;
2835                         index = region.start / phb->ioda.io_segsize;
2836
2837                         while (index < phb->ioda.total_pe &&
2838                                region.start <= region.end) {
2839                                 phb->ioda.io_segmap[index] = pe->pe_number;
2840                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2841                                         pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2842                                 if (rc != OPAL_SUCCESS) {
2843                                         pr_err("%s: OPAL error %d when mapping IO "
2844                                                "segment #%d to PE#%d\n",
2845                                                __func__, rc, index, pe->pe_number);
2846                                         break;
2847                                 }
2848
2849                                 region.start += phb->ioda.io_segsize;
2850                                 index++;
2851                         }
2852                 } else if ((res->flags & IORESOURCE_MEM) &&
2853                            !pnv_pci_is_mem_pref_64(res->flags)) {
2854                         region.start = res->start -
2855                                        hose->mem_offset[0] -
2856                                        phb->ioda.m32_pci_base;
2857                         region.end   = res->end -
2858                                        hose->mem_offset[0] -
2859                                        phb->ioda.m32_pci_base;
2860                         index = region.start / phb->ioda.m32_segsize;
2861
2862                         while (index < phb->ioda.total_pe &&
2863                                region.start <= region.end) {
2864                                 phb->ioda.m32_segmap[index] = pe->pe_number;
2865                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2866                                         pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
2867                                 if (rc != OPAL_SUCCESS) {
2868                                         pr_err("%s: OPAL error %d when mapping M32 "
2869                                                "segment#%d to PE#%d",
2870                                                __func__, rc, index, pe->pe_number);
2871                                         break;
2872                                 }
2873
2874                                 region.start += phb->ioda.m32_segsize;
2875                                 index++;
2876                         }
2877                 }
2878         }
2879 }
2880
2881 static void pnv_pci_ioda_setup_seg(void)
2882 {
2883         struct pci_controller *tmp, *hose;
2884         struct pnv_phb *phb;
2885         struct pnv_ioda_pe *pe;
2886
2887         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2888                 phb = hose->private_data;
2889                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2890                         pnv_ioda_setup_pe_seg(hose, pe);
2891                 }
2892         }
2893 }
2894
2895 static void pnv_pci_ioda_setup_DMA(void)
2896 {
2897         struct pci_controller *hose, *tmp;
2898         struct pnv_phb *phb;
2899
2900         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2901                 pnv_ioda_setup_dma(hose->private_data);
2902
2903                 /* Mark the PHB initialization done */
2904                 phb = hose->private_data;
2905                 phb->initialized = 1;
2906         }
2907 }
2908
2909 static void pnv_pci_ioda_create_dbgfs(void)
2910 {
2911 #ifdef CONFIG_DEBUG_FS
2912         struct pci_controller *hose, *tmp;
2913         struct pnv_phb *phb;
2914         char name[16];
2915
2916         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2917                 phb = hose->private_data;
2918
2919                 sprintf(name, "PCI%04x", hose->global_number);
2920                 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
2921                 if (!phb->dbgfs)
2922                         pr_warning("%s: Error on creating debugfs on PHB#%x\n",
2923                                 __func__, hose->global_number);
2924         }
2925 #endif /* CONFIG_DEBUG_FS */
2926 }
2927
2928 static void pnv_pci_ioda_fixup(void)
2929 {
2930         pnv_pci_ioda_setup_PEs();
2931         pnv_pci_ioda_setup_seg();
2932         pnv_pci_ioda_setup_DMA();
2933
2934         pnv_pci_ioda_create_dbgfs();
2935
2936 #ifdef CONFIG_EEH
2937         eeh_init();
2938         eeh_addr_cache_build();
2939 #endif
2940 }
2941
2942 /*
2943  * Returns the alignment for I/O or memory windows for P2P
2944  * bridges. That actually depends on how PEs are segmented.
2945  * For now, we return I/O or M32 segment size for PE sensitive
2946  * P2P bridges. Otherwise, the default values (4KiB for I/O,
2947  * 1MiB for memory) will be returned.
2948  *
2949  * The current PCI bus might be put into one PE, which was
2950  * create against the parent PCI bridge. For that case, we
2951  * needn't enlarge the alignment so that we can save some
2952  * resources.
2953  */
2954 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
2955                                                 unsigned long type)
2956 {
2957         struct pci_dev *bridge;
2958         struct pci_controller *hose = pci_bus_to_host(bus);
2959         struct pnv_phb *phb = hose->private_data;
2960         int num_pci_bridges = 0;
2961
2962         bridge = bus->self;
2963         while (bridge) {
2964                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
2965                         num_pci_bridges++;
2966                         if (num_pci_bridges >= 2)
2967                                 return 1;
2968                 }
2969
2970                 bridge = bridge->bus->self;
2971         }
2972
2973         /* We fail back to M32 if M64 isn't supported */
2974         if (phb->ioda.m64_segsize &&
2975             pnv_pci_is_mem_pref_64(type))
2976                 return phb->ioda.m64_segsize;
2977         if (type & IORESOURCE_MEM)
2978                 return phb->ioda.m32_segsize;
2979
2980         return phb->ioda.io_segsize;
2981 }
2982
2983 #ifdef CONFIG_PCI_IOV
2984 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
2985                                                       int resno)
2986 {
2987         struct pci_dn *pdn = pci_get_pdn(pdev);
2988         resource_size_t align, iov_align;
2989
2990         iov_align = resource_size(&pdev->resource[resno]);
2991         if (iov_align)
2992                 return iov_align;
2993
2994         align = pci_iov_resource_size(pdev, resno);
2995         if (pdn->vfs_expanded)
2996                 return pdn->vfs_expanded * align;
2997
2998         return align;
2999 }
3000 #endif /* CONFIG_PCI_IOV */
3001
3002 /* Prevent enabling devices for which we couldn't properly
3003  * assign a PE
3004  */
3005 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3006 {
3007         struct pci_controller *hose = pci_bus_to_host(dev->bus);
3008         struct pnv_phb *phb = hose->private_data;
3009         struct pci_dn *pdn;
3010
3011         /* The function is probably called while the PEs have
3012          * not be created yet. For example, resource reassignment
3013          * during PCI probe period. We just skip the check if
3014          * PEs isn't ready.
3015          */
3016         if (!phb->initialized)
3017                 return true;
3018
3019         pdn = pci_get_pdn(dev);
3020         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3021                 return false;
3022
3023         return true;
3024 }
3025
3026 static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
3027                                u32 devfn)
3028 {
3029         return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
3030 }
3031
3032 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3033 {
3034         struct pnv_phb *phb = hose->private_data;
3035
3036         opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3037                        OPAL_ASSERT_RESET);
3038 }
3039
3040 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3041        .dma_dev_setup = pnv_pci_dma_dev_setup,
3042 #ifdef CONFIG_PCI_MSI
3043        .setup_msi_irqs = pnv_setup_msi_irqs,
3044        .teardown_msi_irqs = pnv_teardown_msi_irqs,
3045 #endif
3046        .enable_device_hook = pnv_pci_enable_device_hook,
3047        .window_alignment = pnv_pci_window_alignment,
3048        .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3049        .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3050        .shutdown = pnv_pci_ioda_shutdown,
3051 };
3052
3053 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3054                                          u64 hub_id, int ioda_type)
3055 {
3056         struct pci_controller *hose;
3057         struct pnv_phb *phb;
3058         unsigned long size, m32map_off, pemap_off, iomap_off = 0;
3059         const __be64 *prop64;
3060         const __be32 *prop32;
3061         int len;
3062         u64 phb_id;
3063         void *aux;
3064         long rc;
3065
3066         pr_info("Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
3067
3068         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3069         if (!prop64) {
3070                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
3071                 return;
3072         }
3073         phb_id = be64_to_cpup(prop64);
3074         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
3075
3076         phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3077
3078         /* Allocate PCI controller */
3079         phb->hose = hose = pcibios_alloc_controller(np);
3080         if (!phb->hose) {
3081                 pr_err("  Can't allocate PCI controller for %s\n",
3082                        np->full_name);
3083                 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3084                 return;
3085         }
3086
3087         spin_lock_init(&phb->lock);
3088         prop32 = of_get_property(np, "bus-range", &len);
3089         if (prop32 && len == 8) {
3090                 hose->first_busno = be32_to_cpu(prop32[0]);
3091                 hose->last_busno = be32_to_cpu(prop32[1]);
3092         } else {
3093                 pr_warn("  Broken <bus-range> on %s\n", np->full_name);
3094                 hose->first_busno = 0;
3095                 hose->last_busno = 0xff;
3096         }
3097         hose->private_data = phb;
3098         phb->hub_id = hub_id;
3099         phb->opal_id = phb_id;
3100         phb->type = ioda_type;
3101         mutex_init(&phb->ioda.pe_alloc_mutex);
3102
3103         /* Detect specific models for error handling */
3104         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3105                 phb->model = PNV_PHB_MODEL_P7IOC;
3106         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3107                 phb->model = PNV_PHB_MODEL_PHB3;
3108         else
3109                 phb->model = PNV_PHB_MODEL_UNKNOWN;
3110
3111         /* Parse 32-bit and IO ranges (if any) */
3112         pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3113
3114         /* Get registers */
3115         phb->regs = of_iomap(np, 0);
3116         if (phb->regs == NULL)
3117                 pr_err("  Failed to map registers !\n");
3118
3119         /* Initialize more IODA stuff */
3120         phb->ioda.total_pe = 1;
3121         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3122         if (prop32)
3123                 phb->ioda.total_pe = be32_to_cpup(prop32);
3124         prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3125         if (prop32)
3126                 phb->ioda.reserved_pe = be32_to_cpup(prop32);
3127
3128         /* Parse 64-bit MMIO range */
3129         pnv_ioda_parse_m64_window(phb);
3130
3131         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3132         /* FW Has already off top 64k of M32 space (MSI space) */
3133         phb->ioda.m32_size += 0x10000;
3134
3135         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
3136         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3137         phb->ioda.io_size = hose->pci_io_size;
3138         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
3139         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3140
3141         /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3142         size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
3143         m32map_off = size;
3144         size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
3145         if (phb->type == PNV_PHB_IODA1) {
3146                 iomap_off = size;
3147                 size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]);
3148         }
3149         pemap_off = size;
3150         size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
3151         aux = memblock_virt_alloc(size, 0);
3152         phb->ioda.pe_alloc = aux;
3153         phb->ioda.m32_segmap = aux + m32map_off;
3154         if (phb->type == PNV_PHB_IODA1)
3155                 phb->ioda.io_segmap = aux + iomap_off;
3156         phb->ioda.pe_array = aux + pemap_off;
3157         set_bit(phb->ioda.reserved_pe, phb->ioda.pe_alloc);
3158
3159         INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
3160         INIT_LIST_HEAD(&phb->ioda.pe_list);
3161         mutex_init(&phb->ioda.pe_list_mutex);
3162
3163         /* Calculate how many 32-bit TCE segments we have */
3164         phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
3165
3166 #if 0 /* We should really do that ... */
3167         rc = opal_pci_set_phb_mem_window(opal->phb_id,
3168                                          window_type,
3169                                          window_num,
3170                                          starting_real_address,
3171                                          starting_pci_address,
3172                                          segment_size);
3173 #endif
3174
3175         pr_info("  %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3176                 phb->ioda.total_pe, phb->ioda.reserved_pe,
3177                 phb->ioda.m32_size, phb->ioda.m32_segsize);
3178         if (phb->ioda.m64_size)
3179                 pr_info("                 M64: 0x%lx [segment=0x%lx]\n",
3180                         phb->ioda.m64_size, phb->ioda.m64_segsize);
3181         if (phb->ioda.io_size)
3182                 pr_info("                  IO: 0x%x [segment=0x%x]\n",
3183                         phb->ioda.io_size, phb->ioda.io_segsize);
3184
3185
3186         phb->hose->ops = &pnv_pci_ops;
3187         phb->get_pe_state = pnv_ioda_get_pe_state;
3188         phb->freeze_pe = pnv_ioda_freeze_pe;
3189         phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3190
3191         /* Setup RID -> PE mapping function */
3192         phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
3193
3194         /* Setup TCEs */
3195         phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3196         phb->dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask;
3197
3198         /* Setup MSI support */
3199         pnv_pci_init_ioda_msis(phb);
3200
3201         /*
3202          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3203          * to let the PCI core do resource assignment. It's supposed
3204          * that the PCI core will do correct I/O and MMIO alignment
3205          * for the P2P bridge bars so that each PCI bus (excluding
3206          * the child P2P bridges) can form individual PE.
3207          */
3208         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3209         hose->controller_ops = pnv_pci_ioda_controller_ops;
3210
3211 #ifdef CONFIG_PCI_IOV
3212         ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3213         ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3214 #endif
3215
3216         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3217
3218         /* Reset IODA tables to a clean state */
3219         rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3220         if (rc)
3221                 pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
3222
3223         /* If we're running in kdump kerenl, the previous kerenl never
3224          * shutdown PCI devices correctly. We already got IODA table
3225          * cleaned out. So we have to issue PHB reset to stop all PCI
3226          * transactions from previous kerenl.
3227          */
3228         if (is_kdump_kernel()) {
3229                 pr_info("  Issue PHB reset ...\n");
3230                 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3231                 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3232         }
3233
3234         /* Remove M64 resource if we can't configure it successfully */
3235         if (!phb->init_m64 || phb->init_m64(phb))
3236                 hose->mem_resources[1].flags = 0;
3237 }
3238
3239 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3240 {
3241         pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3242 }
3243
3244 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3245 {
3246         struct device_node *phbn;
3247         const __be64 *prop64;
3248         u64 hub_id;
3249
3250         pr_info("Probing IODA IO-Hub %s\n", np->full_name);
3251
3252         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3253         if (!prop64) {
3254                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3255                 return;
3256         }
3257         hub_id = be64_to_cpup(prop64);
3258         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3259
3260         /* Count child PHBs */
3261         for_each_child_of_node(np, phbn) {
3262                 /* Look for IODA1 PHBs */
3263                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3264                         pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3265         }
3266 }