arch/powerpc/platforms/powermac/smp.c

   1 /*
   2  * SMP support for power macintosh.
   3  *
   4  * We support both the old "powersurge" SMP architecture
   5  * and the current Core99 (G4 PowerMac) machines.
   6  *
   7  * Note that we don't support the very first rev. of
   8  * Apple/DayStar 2 CPUs board, the one with the funky
   9  * watchdog. Hopefully, none of these should be there except
  10  * maybe internally to Apple. I should probably still add some
  11  * code to detect this card though and disable SMP. --BenH.
  12  *
  13  * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
  14  * and Ben Herrenschmidt <benh@kernel.crashing.org>.
  15  *
  16  * Support for DayStar quad CPU cards
  17  * Copyright (C) XLR8, Inc. 1994-2000
  18  *
  19  *  This program is free software; you can redistribute it and/or
  20  *  modify it under the terms of the GNU General Public License
  21  *  as published by the Free Software Foundation; either version
  22  *  2 of the License, or (at your option) any later version.
  23  */
  24 #include <linux/kernel.h>
  25 #include <linux/sched.h>
  26 #include <linux/smp.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/kernel_stat.h>
  29 #include <linux/delay.h>
  30 #include <linux/init.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/errno.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/cpu.h>
  35 #include <linux/compiler.h>
  36
  37 #include <asm/ptrace.h>
  38 #include <asm/atomic.h>
  39 #include <asm/code-patching.h>
  40 #include <asm/irq.h>
  41 #include <asm/page.h>
  42 #include <asm/pgtable.h>
  43 #include <asm/sections.h>
  44 #include <asm/io.h>
  45 #include <asm/prom.h>
  46 #include <asm/smp.h>
  47 #include <asm/machdep.h>
  48 #include <asm/pmac_feature.h>
  49 #include <asm/time.h>
  50 #include <asm/mpic.h>
  51 #include <asm/cacheflush.h>
  52 #include <asm/keylargo.h>
  53 #include <asm/pmac_low_i2c.h>
  54 #include <asm/pmac_pfunc.h>
  55
  56 #include "pmac.h"
  57
  58 #undef DEBUG
  59
  60 #ifdef DEBUG
  61 #define DBG(fmt...) udbg_printf(fmt)
  62 #else
  63 #define DBG(fmt...)
  64 #endif
  65
  66 extern void __secondary_start_pmac_0(void);
  67 extern int pmac_pfunc_base_install(void);
  68
  69 static void (*pmac_tb_freeze)(int freeze);
  70 static u64 timebase;
  71 static int tb_req;
  72
  73 #ifdef CONFIG_PPC32
  74
  75 /*
  76  * Powersurge (old powermac SMP) support.
  77  */
  78
  79 /* Addresses for powersurge registers */
  80 #define HAMMERHEAD_BASE         0xf8000000
  81 #define HHEAD_CONFIG            0x90
  82 #define HHEAD_SEC_INTR          0xc0
  83
  84 /* register for interrupting the primary processor on the powersurge */
  85 /* N.B. this is actually the ethernet ROM! */
  86 #define PSURGE_PRI_INTR         0xf3019000
  87
  88 /* register for storing the start address for the secondary processor */
  89 /* N.B. this is the PCI config space address register for the 1st bridge */
  90 #define PSURGE_START            0xf2800000
  91
  92 /* Daystar/XLR8 4-CPU card */
  93 #define PSURGE_QUAD_REG_ADDR    0xf8800000
  94
  95 #define PSURGE_QUAD_IRQ_SET     0
  96 #define PSURGE_QUAD_IRQ_CLR     1
  97 #define PSURGE_QUAD_IRQ_PRIMARY 2
  98 #define PSURGE_QUAD_CKSTOP_CTL  3
  99 #define PSURGE_QUAD_PRIMARY_ARB 4
 100 #define PSURGE_QUAD_BOARD_ID    6
 101 #define PSURGE_QUAD_WHICH_CPU   7
 102 #define PSURGE_QUAD_CKSTOP_RDBK 8
 103 #define PSURGE_QUAD_RESET_CTL   11
 104
 105 #define PSURGE_QUAD_OUT(r, v)   (out_8(quad_base + ((r) << 4) + 4, (v)))
 106 #define PSURGE_QUAD_IN(r)       (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
 107 #define PSURGE_QUAD_BIS(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
 108 #define PSURGE_QUAD_BIC(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
 109
 110 /* virtual addresses for the above */
 111 static volatile u8 __iomem *hhead_base;
 112 static volatile u8 __iomem *quad_base;
 113 static volatile u32 __iomem *psurge_pri_intr;
 114 static volatile u8 __iomem *psurge_sec_intr;
 115 static volatile u32 __iomem *psurge_start;
 116
 117 /* values for psurge_type */
 118 #define PSURGE_NONE             -1
 119 #define PSURGE_DUAL             0
 120 #define PSURGE_QUAD_OKEE        1
 121 #define PSURGE_QUAD_COTTON      2
 122 #define PSURGE_QUAD_ICEGRASS    3
 123
 124 /* what sort of powersurge board we have */
 125 static int psurge_type = PSURGE_NONE;
 126
 127 /*
 128  * Set and clear IPIs for powersurge.
 129  */
 130 static inline void psurge_set_ipi(int cpu)
 131 {
 132         if (psurge_type == PSURGE_NONE)
 133                 return;
 134         if (cpu == 0)
 135                 in_be32(psurge_pri_intr);
 136         else if (psurge_type == PSURGE_DUAL)
 137                 out_8(psurge_sec_intr, 0);
 138         else
 139                 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
 140 }
 141
 142 static inline void psurge_clr_ipi(int cpu)
 143 {
 144         if (cpu > 0) {
 145                 switch(psurge_type) {
 146                 case PSURGE_DUAL:
 147                         out_8(psurge_sec_intr, ~0);
 148                 case PSURGE_NONE:
 149                         break;
 150                 default:
 151                         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
 152                 }
 153         }
 154 }
 155
 156 /*
 157  * On powersurge (old SMP powermac architecture) we don't have
 158  * separate IPIs for separate messages like openpic does.  Instead
 159  * we have a bitmap for each processor, where a 1 bit means that
 160  * the corresponding message is pending for that processor.
 161  * Ideally each cpu's entry would be in a different cache line.
 162  *  -- paulus.
 163  */
 164 static unsigned long psurge_smp_message[NR_CPUS];
 165
 166 void psurge_smp_message_recv(void)
 167 {
 168         int cpu = smp_processor_id();
 169         int msg;
 170
 171         /* clear interrupt */
 172         psurge_clr_ipi(cpu);
 173
 174         if (num_online_cpus() < 2)
 175                 return;
 176
 177         /* make sure there is a message there */
 178         for (msg = 0; msg < 4; msg++)
 179                 if (test_and_clear_bit(msg, &psurge_smp_message[cpu]))
 180                         smp_message_recv(msg);
 181 }
 182
 183 irqreturn_t psurge_primary_intr(int irq, void *d)
 184 {
 185         psurge_smp_message_recv();
 186         return IRQ_HANDLED;
 187 }
 188
 189 static void smp_psurge_message_pass(int target, int msg)
 190 {
 191         int i;
 192
 193         if (num_online_cpus() < 2)
 194                 return;
 195
 196         for_each_online_cpu(i) {
 197                 if (target == MSG_ALL
 198                     || (target == MSG_ALL_BUT_SELF && i != smp_processor_id())
 199                     || target == i) {
 200                         set_bit(msg, &psurge_smp_message[i]);
 201                         psurge_set_ipi(i);
 202                 }
 203         }
 204 }
 205
 206 /*
 207  * Determine a quad card presence. We read the board ID register, we
 208  * force the data bus to change to something else, and we read it again.
 209  * It it's stable, then the register probably exist (ugh !)
 210  */
 211 static int __init psurge_quad_probe(void)
 212 {
 213         int type;
 214         unsigned int i;
 215
 216         type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
 217         if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
 218             || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
 219                 return PSURGE_DUAL;
 220
 221         /* looks OK, try a slightly more rigorous test */
 222         /* bogus is not necessarily cacheline-aligned,
 223            though I don't suppose that really matters.  -- paulus */
 224         for (i = 0; i < 100; i++) {
 225                 volatile u32 bogus[8];
 226                 bogus[(0+i)%8] = 0x00000000;
 227                 bogus[(1+i)%8] = 0x55555555;
 228                 bogus[(2+i)%8] = 0xFFFFFFFF;
 229                 bogus[(3+i)%8] = 0xAAAAAAAA;
 230                 bogus[(4+i)%8] = 0x33333333;
 231                 bogus[(5+i)%8] = 0xCCCCCCCC;
 232                 bogus[(6+i)%8] = 0xCCCCCCCC;
 233                 bogus[(7+i)%8] = 0x33333333;
 234                 wmb();
 235                 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
 236                 mb();
 237                 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
 238                         return PSURGE_DUAL;
 239         }
 240         return type;
 241 }
 242
 243 static void __init psurge_quad_init(void)
 244 {
 245         int procbits;
 246
 247         if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
 248         procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
 249         if (psurge_type == PSURGE_QUAD_ICEGRASS)
 250                 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
 251         else
 252                 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
 253         mdelay(33);
 254         out_8(psurge_sec_intr, ~0);
 255         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
 256         PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
 257         if (psurge_type != PSURGE_QUAD_ICEGRASS)
 258                 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
 259         PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
 260         mdelay(33);
 261         PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
 262         mdelay(33);
 263         PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
 264         mdelay(33);
 265 }
 266
 267 static int __init smp_psurge_probe(void)
 268 {
 269         int i, ncpus;
 270         struct device_node *dn;
 271
 272         /* We don't do SMP on the PPC601 -- paulus */
 273         if (PVR_VER(mfspr(SPRN_PVR)) == 1)
 274                 return 1;
 275
 276         /*
 277          * The powersurge cpu board can be used in the generation
 278          * of powermacs that have a socket for an upgradeable cpu card,
 279          * including the 7500, 8500, 9500, 9600.
 280          * The device tree doesn't tell you if you have 2 cpus because
 281          * OF doesn't know anything about the 2nd processor.
 282          * Instead we look for magic bits in magic registers,
 283          * in the hammerhead memory controller in the case of the
 284          * dual-cpu powersurge board.  -- paulus.
 285          */
 286         dn = of_find_node_by_name(NULL, "hammerhead");
 287         if (dn == NULL)
 288                 return 1;
 289         of_node_put(dn);
 290
 291         hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
 292         quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
 293         psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
 294
 295         psurge_type = psurge_quad_probe();
 296         if (psurge_type != PSURGE_DUAL) {
 297                 psurge_quad_init();
 298                 /* All released cards using this HW design have 4 CPUs */
 299                 ncpus = 4;
 300                 /* No sure how timebase sync works on those, let's use SW */
 301                 smp_ops->give_timebase = smp_generic_give_timebase;
 302                 smp_ops->take_timebase = smp_generic_take_timebase;
 303         } else {
 304                 iounmap(quad_base);
 305                 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
 306                         /* not a dual-cpu card */
 307                         iounmap(hhead_base);
 308                         psurge_type = PSURGE_NONE;
 309                         return 1;
 310                 }
 311                 ncpus = 2;
 312         }
 313
 314         psurge_start = ioremap(PSURGE_START, 4);
 315         psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
 316
 317         /* This is necessary because OF doesn't know about the
 318          * secondary cpu(s), and thus there aren't nodes in the
 319          * device tree for them, and smp_setup_cpu_maps hasn't
 320          * set their bits in cpu_present_mask.
 321          */
 322         if (ncpus > NR_CPUS)
 323                 ncpus = NR_CPUS;
 324         for (i = 1; i < ncpus ; ++i)
 325                 set_cpu_present(i, true);
 326
 327         if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
 328
 329         return ncpus;
 330 }
 331
 332 static int __init smp_psurge_kick_cpu(int nr)
 333 {
 334         unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
 335         unsigned long a, flags;
 336         int i, j;
 337
 338         /* Defining this here is evil ... but I prefer hiding that
 339          * crap to avoid giving people ideas that they can do the
 340          * same.
 341          */
 342         extern volatile unsigned int cpu_callin_map[NR_CPUS];
 343
 344         /* may need to flush here if secondary bats aren't setup */
 345         for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
 346                 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
 347         asm volatile("sync");
 348
 349         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
 350
 351         /* This is going to freeze the timeebase, we disable interrupts */
 352         local_irq_save(flags);
 353
 354         out_be32(psurge_start, start);
 355         mb();
 356
 357         psurge_set_ipi(nr);
 358
 359         /*
 360          * We can't use udelay here because the timebase is now frozen.
 361          */
 362         for (i = 0; i < 2000; ++i)
 363                 asm volatile("nop" : : : "memory");
 364         psurge_clr_ipi(nr);
 365
 366         /*
 367          * Also, because the timebase is frozen, we must not return to the
 368          * caller which will try to do udelay's etc... Instead, we wait -here-
 369          * for the CPU to callin.
 370          */
 371         for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) {
 372                 for (j = 1; j < 10000; j++)
 373                         asm volatile("nop" : : : "memory");
 374                 asm volatile("sync" : : : "memory");
 375         }
 376         if (!cpu_callin_map[nr])
 377                 goto stuck;
 378
 379         /* And we do the TB sync here too for standard dual CPU cards */
 380         if (psurge_type == PSURGE_DUAL) {
 381                 while(!tb_req)
 382                         barrier();
 383                 tb_req = 0;
 384                 mb();
 385                 timebase = get_tb();
 386                 mb();
 387                 while (timebase)
 388                         barrier();
 389                 mb();
 390         }
 391  stuck:
 392         /* now interrupt the secondary, restarting both TBs */
 393         if (psurge_type == PSURGE_DUAL)
 394                 psurge_set_ipi(1);
 395
 396         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
 397
 398         return 0;
 399 }
 400
 401 static struct irqaction psurge_irqaction = {
 402         .handler = psurge_primary_intr,
 403         .flags = IRQF_DISABLED,
 404         .name = "primary IPI",
 405 };
 406
 407 static void __init smp_psurge_setup_cpu(int cpu_nr)
 408 {
 409         if (cpu_nr != 0)
 410                 return;
 411
 412         /* reset the entry point so if we get another intr we won't
 413          * try to startup again */
 414         out_be32(psurge_start, 0x100);
 415         if (setup_irq(irq_create_mapping(NULL, 30), &psurge_irqaction))
 416                 printk(KERN_ERR "Couldn't get primary IPI interrupt");
 417 }
 418
 419 void __init smp_psurge_take_timebase(void)
 420 {
 421         if (psurge_type != PSURGE_DUAL)
 422                 return;
 423
 424         tb_req = 1;
 425         mb();
 426         while (!timebase)
 427                 barrier();
 428         mb();
 429         set_tb(timebase >> 32, timebase & 0xffffffff);
 430         timebase = 0;
 431         mb();
 432         set_dec(tb_ticks_per_jiffy/2);
 433 }
 434
 435 void __init smp_psurge_give_timebase(void)
 436 {
 437         /* Nothing to do here */
 438 }
 439
 440 /* PowerSurge-style Macs */
 441 struct smp_ops_t psurge_smp_ops = {
 442         .message_pass   = smp_psurge_message_pass,
 443         .probe          = smp_psurge_probe,
 444         .kick_cpu       = smp_psurge_kick_cpu,
 445         .setup_cpu      = smp_psurge_setup_cpu,
 446         .give_timebase  = smp_psurge_give_timebase,
 447         .take_timebase  = smp_psurge_take_timebase,
 448 };
 449 #endif /* CONFIG_PPC32 - actually powersurge support */
 450
 451 /*
 452  * Core 99 and later support
 453  */
 454
 455
 456 static void smp_core99_give_timebase(void)
 457 {
 458         unsigned long flags;
 459
 460         local_irq_save(flags);
 461
 462         while(!tb_req)
 463                 barrier();
 464         tb_req = 0;
 465         (*pmac_tb_freeze)(1);
 466         mb();
 467         timebase = get_tb();
 468         mb();
 469         while (timebase)
 470                 barrier();
 471         mb();
 472         (*pmac_tb_freeze)(0);
 473         mb();
 474
 475         local_irq_restore(flags);
 476 }
 477
 478
 479 static void __devinit smp_core99_take_timebase(void)
 480 {
 481         unsigned long flags;
 482
 483         local_irq_save(flags);
 484
 485         tb_req = 1;
 486         mb();
 487         while (!timebase)
 488                 barrier();
 489         mb();
 490         set_tb(timebase >> 32, timebase & 0xffffffff);
 491         timebase = 0;
 492         mb();
 493
 494         local_irq_restore(flags);
 495 }
 496
 497 #ifdef CONFIG_PPC64
 498 /*
 499  * G5s enable/disable the timebase via an i2c-connected clock chip.
 500  */
 501 static struct pmac_i2c_bus *pmac_tb_clock_chip_host;
 502 static u8 pmac_tb_pulsar_addr;
 503
 504 static void smp_core99_cypress_tb_freeze(int freeze)
 505 {
 506         u8 data;
 507         int rc;
 508
 509         /* Strangely, the device-tree says address is 0xd2, but darwin
 510          * accesses 0xd0 ...
 511          */
 512         pmac_i2c_setmode(pmac_tb_clock_chip_host,
 513                          pmac_i2c_mode_combined);
 514         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
 515                            0xd0 | pmac_i2c_read,
 516                            1, 0x81, &data, 1);
 517         if (rc != 0)
 518                 goto bail;
 519
 520         data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
 521
 522         pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
 523         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
 524                            0xd0 | pmac_i2c_write,
 525                            1, 0x81, &data, 1);
 526
 527  bail:
 528         if (rc != 0) {
 529                 printk("Cypress Timebase %s rc: %d\n",
 530                        freeze ? "freeze" : "unfreeze", rc);
 531                 panic("Timebase freeze failed !\n");
 532         }
 533 }
 534
 535
 536 static void smp_core99_pulsar_tb_freeze(int freeze)
 537 {
 538         u8 data;
 539         int rc;
 540
 541         pmac_i2c_setmode(pmac_tb_clock_chip_host,
 542                          pmac_i2c_mode_combined);
 543         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
 544                            pmac_tb_pulsar_addr | pmac_i2c_read,
 545                            1, 0x2e, &data, 1);
 546         if (rc != 0)
 547                 goto bail;
 548
 549         data = (data & 0x88) | (freeze ? 0x11 : 0x22);
 550
 551         pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
 552         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
 553                            pmac_tb_pulsar_addr | pmac_i2c_write,
 554                            1, 0x2e, &data, 1);
 555  bail:
 556         if (rc != 0) {
 557                 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
 558                        freeze ? "freeze" : "unfreeze", rc);
 559                 panic("Timebase freeze failed !\n");
 560         }
 561 }
 562
 563 static void __init smp_core99_setup_i2c_hwsync(int ncpus)
 564 {
 565         struct device_node *cc = NULL;
 566         struct device_node *p;
 567         const char *name = NULL;
 568         const u32 *reg;
 569         int ok;
 570
 571         /* Look for the clock chip */
 572         while ((cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL) {
 573                 p = of_get_parent(cc);
 574                 ok = p && of_device_is_compatible(p, "uni-n-i2c");
 575                 of_node_put(p);
 576                 if (!ok)
 577                         continue;
 578
 579                 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc);
 580                 if (pmac_tb_clock_chip_host == NULL)
 581                         continue;
 582                 reg = of_get_property(cc, "reg", NULL);
 583                 if (reg == NULL)
 584                         continue;
 585                 switch (*reg) {
 586                 case 0xd2:
 587                         if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) {
 588                                 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
 589                                 pmac_tb_pulsar_addr = 0xd2;
 590                                 name = "Pulsar";
 591                         } else if (of_device_is_compatible(cc, "cy28508")) {
 592                                 pmac_tb_freeze = smp_core99_cypress_tb_freeze;
 593                                 name = "Cypress";
 594                         }
 595                         break;
 596                 case 0xd4:
 597                         pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
 598                         pmac_tb_pulsar_addr = 0xd4;
 599                         name = "Pulsar";
 600                         break;
 601                 }
 602                 if (pmac_tb_freeze != NULL)
 603                         break;
 604         }
 605         if (pmac_tb_freeze != NULL) {
 606                 /* Open i2c bus for synchronous access */
 607                 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) {
 608                         printk(KERN_ERR "Failed top open i2c bus for clock"
 609                                " sync, fallback to software sync !\n");
 610                         goto no_i2c_sync;
 611                 }
 612                 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n",
 613                        name);
 614                 return;
 615         }
 616  no_i2c_sync:
 617         pmac_tb_freeze = NULL;
 618         pmac_tb_clock_chip_host = NULL;
 619 }
 620
 621
 622
 623 /*
 624  * Newer G5s uses a platform function
 625  */
 626
 627 static void smp_core99_pfunc_tb_freeze(int freeze)
 628 {
 629         struct device_node *cpus;
 630         struct pmf_args args;
 631
 632         cpus = of_find_node_by_path("/cpus");
 633         BUG_ON(cpus == NULL);
 634         args.count = 1;
 635         args.u[0].v = !freeze;
 636         pmf_call_function(cpus, "cpu-timebase", &args);
 637         of_node_put(cpus);
 638 }
 639
 640 #else /* CONFIG_PPC64 */
 641
 642 /*
 643  * SMP G4 use a GPIO to enable/disable the timebase.
 644  */
 645
 646 static unsigned int core99_tb_gpio;     /* Timebase freeze GPIO */
 647
 648 static void smp_core99_gpio_tb_freeze(int freeze)
 649 {
 650         if (freeze)
 651                 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
 652         else
 653                 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
 654         pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
 655 }
 656
 657
 658 #endif /* !CONFIG_PPC64 */
 659
 660 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
 661 volatile static long int core99_l2_cache;
 662 volatile static long int core99_l3_cache;
 663
 664 static void __devinit core99_init_caches(int cpu)
 665 {
 666 #ifndef CONFIG_PPC64
 667         if (!cpu_has_feature(CPU_FTR_L2CR))
 668                 return;
 669
 670         if (cpu == 0) {
 671                 core99_l2_cache = _get_L2CR();
 672                 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
 673         } else {
 674                 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
 675                 _set_L2CR(0);
 676                 _set_L2CR(core99_l2_cache);
 677                 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
 678         }
 679
 680         if (!cpu_has_feature(CPU_FTR_L3CR))
 681                 return;
 682
 683         if (cpu == 0){
 684                 core99_l3_cache = _get_L3CR();
 685                 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
 686         } else {
 687                 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
 688                 _set_L3CR(0);
 689                 _set_L3CR(core99_l3_cache);
 690                 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
 691         }
 692 #endif /* !CONFIG_PPC64 */
 693 }
 694
 695 static void __init smp_core99_setup(int ncpus)
 696 {
 697 #ifdef CONFIG_PPC64
 698
 699         /* i2c based HW sync on some G5s */
 700         if (of_machine_is_compatible("PowerMac7,2") ||
 701             of_machine_is_compatible("PowerMac7,3") ||
 702             of_machine_is_compatible("RackMac3,1"))
 703                 smp_core99_setup_i2c_hwsync(ncpus);
 704
 705         /* pfunc based HW sync on recent G5s */
 706         if (pmac_tb_freeze == NULL) {
 707                 struct device_node *cpus =
 708                         of_find_node_by_path("/cpus");
 709                 if (cpus &&
 710                     of_get_property(cpus, "platform-cpu-timebase", NULL)) {
 711                         pmac_tb_freeze = smp_core99_pfunc_tb_freeze;
 712                         printk(KERN_INFO "Processor timebase sync using"
 713                                " platform function\n");
 714                 }
 715         }
 716
 717 #else /* CONFIG_PPC64 */
 718
 719         /* GPIO based HW sync on ppc32 Core99 */
 720         if (pmac_tb_freeze == NULL && !of_machine_is_compatible("MacRISC4")) {
 721                 struct device_node *cpu;
 722                 const u32 *tbprop = NULL;
 723
 724                 core99_tb_gpio = KL_GPIO_TB_ENABLE;     /* default value */
 725                 cpu = of_find_node_by_type(NULL, "cpu");
 726                 if (cpu != NULL) {
 727                         tbprop = of_get_property(cpu, "timebase-enable", NULL);
 728                         if (tbprop)
 729                                 core99_tb_gpio = *tbprop;
 730                         of_node_put(cpu);
 731                 }
 732                 pmac_tb_freeze = smp_core99_gpio_tb_freeze;
 733                 printk(KERN_INFO "Processor timebase sync using"
 734                        " GPIO 0x%02x\n", core99_tb_gpio);
 735         }
 736
 737 #endif /* CONFIG_PPC64 */
 738
 739         /* No timebase sync, fallback to software */
 740         if (pmac_tb_freeze == NULL) {
 741                 smp_ops->give_timebase = smp_generic_give_timebase;
 742                 smp_ops->take_timebase = smp_generic_take_timebase;
 743                 printk(KERN_INFO "Processor timebase sync using software\n");
 744         }
 745
 746 #ifndef CONFIG_PPC64
 747         {
 748                 int i;
 749
 750                 /* XXX should get this from reg properties */
 751                 for (i = 1; i < ncpus; ++i)
 752                         set_hard_smp_processor_id(i, i);
 753         }
 754 #endif
 755
 756         /* 32 bits SMP can't NAP */
 757         if (!of_machine_is_compatible("MacRISC4"))
 758                 powersave_nap = 0;
 759 }
 760
 761 static int __init smp_core99_probe(void)
 762 {
 763         struct device_node *cpus;
 764         int ncpus = 0;
 765
 766         if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
 767
 768         /* Count CPUs in the device-tree */
 769         for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;)
 770                 ++ncpus;
 771
 772         printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
 773
 774         /* Nothing more to do if less than 2 of them */
 775         if (ncpus <= 1)
 776                 return 1;
 777
 778         /* We need to perform some early initialisations before we can start
 779          * setting up SMP as we are running before initcalls
 780          */
 781         pmac_pfunc_base_install();
 782         pmac_i2c_init();
 783
 784         /* Setup various bits like timebase sync method, ability to nap, ... */
 785         smp_core99_setup(ncpus);
 786
 787         /* Install IPIs */
 788         mpic_request_ipis();
 789
 790         /* Collect l2cr and l3cr values from CPU 0 */
 791         core99_init_caches(0);
 792
 793         return ncpus;
 794 }
 795
 796 static int __devinit smp_core99_kick_cpu(int nr)
 797 {
 798         unsigned int save_vector;
 799         unsigned long target, flags;
 800         unsigned int *vector = (unsigned int *)(PAGE_OFFSET+0x100);
 801
 802         if (nr < 0 || nr > 3)
 803                 return -ENOENT;
 804
 805         if (ppc_md.progress)
 806                 ppc_md.progress("smp_core99_kick_cpu", 0x346);
 807
 808         local_irq_save(flags);
 809
 810         /* Save reset vector */
 811         save_vector = *vector;
 812
 813         /* Setup fake reset vector that does
 814          *   b __secondary_start_pmac_0 + nr*8
 815          */
 816         target = (unsigned long) __secondary_start_pmac_0 + nr * 8;
 817         patch_branch(vector, target, BRANCH_SET_LINK);
 818
 819         /* Put some life in our friend */
 820         pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
 821
 822         /* FIXME: We wait a bit for the CPU to take the exception, I should
 823          * instead wait for the entry code to set something for me. Well,
 824          * ideally, all that crap will be done in prom.c and the CPU left
 825          * in a RAM-based wait loop like CHRP.
 826          */
 827         mdelay(1);
 828
 829         /* Restore our exception vector */
 830         *vector = save_vector;
 831         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
 832
 833         local_irq_restore(flags);
 834         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
 835
 836         return 0;
 837 }
 838
 839 static void __devinit smp_core99_setup_cpu(int cpu_nr)
 840 {
 841         /* Setup L2/L3 */
 842         if (cpu_nr != 0)
 843                 core99_init_caches(cpu_nr);
 844
 845         /* Setup openpic */
 846         mpic_setup_this_cpu();
 847 }
 848
 849 #ifdef CONFIG_PPC64
 850 #ifdef CONFIG_HOTPLUG_CPU
 851 static int smp_core99_cpu_notify(struct notifier_block *self,
 852                                  unsigned long action, void *hcpu)
 853 {
 854         int rc;
 855
 856         switch(action) {
 857         case CPU_UP_PREPARE:
 858         case CPU_UP_PREPARE_FROZEN:
 859                 /* Open i2c bus if it was used for tb sync */
 860                 if (pmac_tb_clock_chip_host) {
 861                         rc = pmac_i2c_open(pmac_tb_clock_chip_host, 1);
 862                         if (rc) {
 863                                 pr_err("Failed to open i2c bus for time sync\n");
 864                                 return notifier_from_errno(rc);
 865                         }
 866                 }
 867                 break;
 868         case CPU_ONLINE:
 869         case CPU_UP_CANCELED:
 870                 /* Close i2c bus if it was used for tb sync */
 871                 if (pmac_tb_clock_chip_host)
 872                         pmac_i2c_close(pmac_tb_clock_chip_host);
 873                 break;
 874         default:
 875                 break;
 876         }
 877         return NOTIFY_OK;
 878 }
 879
 880 static struct notifier_block __cpuinitdata smp_core99_cpu_nb = {
 881         .notifier_call  = smp_core99_cpu_notify,
 882 };
 883 #endif /* CONFIG_HOTPLUG_CPU */
 884
 885 static void __init smp_core99_bringup_done(void)
 886 {
 887         extern void g5_phy_disable_cpu1(void);
 888
 889         /* Close i2c bus if it was used for tb sync */
 890         if (pmac_tb_clock_chip_host)
 891                 pmac_i2c_close(pmac_tb_clock_chip_host);
 892
 893         /* If we didn't start the second CPU, we must take
 894          * it off the bus.
 895          */
 896         if (of_machine_is_compatible("MacRISC4") &&
 897             num_online_cpus() < 2) {
 898                 set_cpu_present(1, false);
 899                 g5_phy_disable_cpu1();
 900         }
 901 #ifdef CONFIG_HOTPLUG_CPU
 902         register_cpu_notifier(&smp_core99_cpu_nb);
 903 #endif
 904
 905         if (ppc_md.progress)
 906                 ppc_md.progress("smp_core99_bringup_done", 0x349);
 907 }
 908 #endif /* CONFIG_PPC64 */
 909
 910 #ifdef CONFIG_HOTPLUG_CPU
 911
 912 static int smp_core99_cpu_disable(void)
 913 {
 914         int rc = generic_cpu_disable();
 915         if (rc)
 916                 return rc;
 917
 918         mpic_cpu_set_priority(0xf);
 919
 920         return 0;
 921 }
 922
 923 #ifdef CONFIG_PPC32
 924
 925 static void pmac_cpu_die(void)
 926 {
 927         int cpu = smp_processor_id();
 928
 929         local_irq_disable();
 930         idle_task_exit();
 931         pr_debug("CPU%d offline\n", cpu);
 932         generic_set_cpu_dead(cpu);
 933         smp_wmb();
 934         mb();
 935         low_cpu_die();
 936 }
 937
 938 #else /* CONFIG_PPC32 */
 939
 940 static void pmac_cpu_die(void)
 941 {
 942         int cpu = smp_processor_id();
 943
 944         local_irq_disable();
 945         idle_task_exit();
 946
 947         /*
 948          * turn off as much as possible, we'll be
 949          * kicked out as this will only be invoked
 950          * on core99 platforms for now ...
 951          */
 952
 953         printk(KERN_INFO "CPU#%d offline\n", cpu);
 954         generic_set_cpu_dead(cpu);
 955         smp_wmb();
 956
 957         /*
 958          * Re-enable interrupts. The NAP code needs to enable them
 959          * anyways, do it now so we deal with the case where one already
 960          * happened while soft-disabled.
 961          * We shouldn't get any external interrupts, only decrementer, and the
 962          * decrementer handler is safe for use on offline CPUs
 963          */
 964         local_irq_enable();
 965
 966         while (1) {
 967                 /* let's not take timer interrupts too often ... */
 968                 set_dec(0x7fffffff);
 969
 970                 /* Enter NAP mode */
 971                 power4_idle();
 972         }
 973 }
 974
 975 #endif /* else CONFIG_PPC32 */
 976 #endif /* CONFIG_HOTPLUG_CPU */
 977
 978 /* Core99 Macs (dual G4s and G5s) */
 979 struct smp_ops_t core99_smp_ops = {
 980         .message_pass   = smp_mpic_message_pass,
 981         .probe          = smp_core99_probe,
 982 #ifdef CONFIG_PPC64
 983         .bringup_done   = smp_core99_bringup_done,
 984 #endif
 985         .kick_cpu       = smp_core99_kick_cpu,
 986         .setup_cpu      = smp_core99_setup_cpu,
 987         .give_timebase  = smp_core99_give_timebase,
 988         .take_timebase  = smp_core99_take_timebase,
 989 #if defined(CONFIG_HOTPLUG_CPU)
 990         .cpu_disable    = smp_core99_cpu_disable,
 991         .cpu_die        = generic_cpu_die,
 992 #endif
 993 };
 994
 995 void __init pmac_setup_smp(void)
 996 {
 997         struct device_node *np;
 998
 999         /* Check for Core99 */
1000         np = of_find_node_by_name(NULL, "uni-n");
1001         if (!np)
1002                 np = of_find_node_by_name(NULL, "u3");
1003         if (!np)
1004                 np = of_find_node_by_name(NULL, "u4");
1005         if (np) {
1006                 of_node_put(np);
1007                 smp_ops = &core99_smp_ops;
1008         }
1009 #ifdef CONFIG_PPC32
1010         else {
1011                 /* We have to set bits in cpu_possible_mask here since the
1012                  * secondary CPU(s) aren't in the device tree. Various
1013                  * things won't be initialized for CPUs not in the possible
1014                  * map, so we really need to fix it up here.
1015                  */
1016                 int cpu;
1017
1018                 for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu)
1019                         set_cpu_possible(cpu, true);
1020                 smp_ops = &psurge_smp_ops;
1021         }
1022 #endif /* CONFIG_PPC32 */
1023
1024 #ifdef CONFIG_HOTPLUG_CPU
1025         ppc_md.cpu_die = pmac_cpu_die;
1026 #endif
1027 }
1028
1029