arch/powerpc/platforms/powermac/smp.c

   1 /*
   2  * SMP support for power macintosh.
   3  *
   4  * We support both the old "powersurge" SMP architecture
   5  * and the current Core99 (G4 PowerMac) machines.
   6  *
   7  * Note that we don't support the very first rev. of
   8  * Apple/DayStar 2 CPUs board, the one with the funky
   9  * watchdog. Hopefully, none of these should be there except
  10  * maybe internally to Apple. I should probably still add some
  11  * code to detect this card though and disable SMP. --BenH.
  12  *
  13  * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
  14  * and Ben Herrenschmidt <benh@kernel.crashing.org>.
  15  *
  16  * Support for DayStar quad CPU cards
  17  * Copyright (C) XLR8, Inc. 1994-2000
  18  *
  19  *  This program is free software; you can redistribute it and/or
  20  *  modify it under the terms of the GNU General Public License
  21  *  as published by the Free Software Foundation; either version
  22  *  2 of the License, or (at your option) any later version.
  23  */
  24 #include <linux/kernel.h>
  25 #include <linux/sched.h>
  26 #include <linux/smp.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/kernel_stat.h>
  29 #include <linux/delay.h>
  30 #include <linux/init.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/errno.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/cpu.h>
  35 #include <linux/compiler.h>
  36
  37 #include <asm/ptrace.h>
  38 #include <asm/atomic.h>
  39 #include <asm/code-patching.h>
  40 #include <asm/irq.h>
  41 #include <asm/page.h>
  42 #include <asm/pgtable.h>
  43 #include <asm/sections.h>
  44 #include <asm/io.h>
  45 #include <asm/prom.h>
  46 #include <asm/smp.h>
  47 #include <asm/machdep.h>
  48 #include <asm/pmac_feature.h>
  49 #include <asm/time.h>
  50 #include <asm/mpic.h>
  51 #include <asm/cacheflush.h>
  52 #include <asm/keylargo.h>
  53 #include <asm/pmac_low_i2c.h>
  54 #include <asm/pmac_pfunc.h>
  55
  56 #include "pmac.h"
  57
  58 #undef DEBUG
  59
  60 #ifdef DEBUG
  61 #define DBG(fmt...) udbg_printf(fmt)
  62 #else
  63 #define DBG(fmt...)
  64 #endif
  65
  66 extern void __secondary_start_pmac_0(void);
  67 extern int pmac_pfunc_base_install(void);
  68
  69 static void (*pmac_tb_freeze)(int freeze);
  70 static u64 timebase;
  71 static int tb_req;
  72
  73 #ifdef CONFIG_PPC32
  74
  75 /*
  76  * Powersurge (old powermac SMP) support.
  77  */
  78
  79 /* Addresses for powersurge registers */
  80 #define HAMMERHEAD_BASE         0xf8000000
  81 #define HHEAD_CONFIG            0x90
  82 #define HHEAD_SEC_INTR          0xc0
  83
  84 /* register for interrupting the primary processor on the powersurge */
  85 /* N.B. this is actually the ethernet ROM! */
  86 #define PSURGE_PRI_INTR         0xf3019000
  87
  88 /* register for storing the start address for the secondary processor */
  89 /* N.B. this is the PCI config space address register for the 1st bridge */
  90 #define PSURGE_START            0xf2800000
  91
  92 /* Daystar/XLR8 4-CPU card */
  93 #define PSURGE_QUAD_REG_ADDR    0xf8800000
  94
  95 #define PSURGE_QUAD_IRQ_SET     0
  96 #define PSURGE_QUAD_IRQ_CLR     1
  97 #define PSURGE_QUAD_IRQ_PRIMARY 2
  98 #define PSURGE_QUAD_CKSTOP_CTL  3
  99 #define PSURGE_QUAD_PRIMARY_ARB 4
 100 #define PSURGE_QUAD_BOARD_ID    6
 101 #define PSURGE_QUAD_WHICH_CPU   7
 102 #define PSURGE_QUAD_CKSTOP_RDBK 8
 103 #define PSURGE_QUAD_RESET_CTL   11
 104
 105 #define PSURGE_QUAD_OUT(r, v)   (out_8(quad_base + ((r) << 4) + 4, (v)))
 106 #define PSURGE_QUAD_IN(r)       (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
 107 #define PSURGE_QUAD_BIS(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
 108 #define PSURGE_QUAD_BIC(r, v)   (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
 109
 110 /* virtual addresses for the above */
 111 static volatile u8 __iomem *hhead_base;
 112 static volatile u8 __iomem *quad_base;
 113 static volatile u32 __iomem *psurge_pri_intr;
 114 static volatile u8 __iomem *psurge_sec_intr;
 115 static volatile u32 __iomem *psurge_start;
 116
 117 /* values for psurge_type */
 118 #define PSURGE_NONE             -1
 119 #define PSURGE_DUAL             0
 120 #define PSURGE_QUAD_OKEE        1
 121 #define PSURGE_QUAD_COTTON      2
 122 #define PSURGE_QUAD_ICEGRASS    3
 123
 124 /* what sort of powersurge board we have */
 125 static int psurge_type = PSURGE_NONE;
 126
 127 /*
 128  * Set and clear IPIs for powersurge.
 129  */
 130 static inline void psurge_set_ipi(int cpu)
 131 {
 132         if (psurge_type == PSURGE_NONE)
 133                 return;
 134         if (cpu == 0)
 135                 in_be32(psurge_pri_intr);
 136         else if (psurge_type == PSURGE_DUAL)
 137                 out_8(psurge_sec_intr, 0);
 138         else
 139                 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
 140 }
 141
 142 static inline void psurge_clr_ipi(int cpu)
 143 {
 144         if (cpu > 0) {
 145                 switch(psurge_type) {
 146                 case PSURGE_DUAL:
 147                         out_8(psurge_sec_intr, ~0);
 148                 case PSURGE_NONE:
 149                         break;
 150                 default:
 151                         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
 152                 }
 153         }
 154 }
 155
 156 /*
 157  * On powersurge (old SMP powermac architecture) we don't have
 158  * separate IPIs for separate messages like openpic does.  Instead
 159  * use the generic demux helpers
 160  *  -- paulus.
 161  */
 162 void psurge_smp_message_recv(void)
 163 {
 164         psurge_clr_ipi(smp_processor_id());
 165         smp_ipi_demux();
 166 }
 167
 168 irqreturn_t psurge_primary_intr(int irq, void *d)
 169 {
 170         psurge_smp_message_recv();
 171         return IRQ_HANDLED;
 172 }
 173
 174 static void smp_psurge_cause_ipi(int cpu, unsigned long data)
 175 {
 176         psurge_set_ipi(cpu);
 177 }
 178
 179 /*
 180  * Determine a quad card presence. We read the board ID register, we
 181  * force the data bus to change to something else, and we read it again.
 182  * It it's stable, then the register probably exist (ugh !)
 183  */
 184 static int __init psurge_quad_probe(void)
 185 {
 186         int type;
 187         unsigned int i;
 188
 189         type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
 190         if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
 191             || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
 192                 return PSURGE_DUAL;
 193
 194         /* looks OK, try a slightly more rigorous test */
 195         /* bogus is not necessarily cacheline-aligned,
 196            though I don't suppose that really matters.  -- paulus */
 197         for (i = 0; i < 100; i++) {
 198                 volatile u32 bogus[8];
 199                 bogus[(0+i)%8] = 0x00000000;
 200                 bogus[(1+i)%8] = 0x55555555;
 201                 bogus[(2+i)%8] = 0xFFFFFFFF;
 202                 bogus[(3+i)%8] = 0xAAAAAAAA;
 203                 bogus[(4+i)%8] = 0x33333333;
 204                 bogus[(5+i)%8] = 0xCCCCCCCC;
 205                 bogus[(6+i)%8] = 0xCCCCCCCC;
 206                 bogus[(7+i)%8] = 0x33333333;
 207                 wmb();
 208                 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
 209                 mb();
 210                 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
 211                         return PSURGE_DUAL;
 212         }
 213         return type;
 214 }
 215
 216 static void __init psurge_quad_init(void)
 217 {
 218         int procbits;
 219
 220         if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
 221         procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
 222         if (psurge_type == PSURGE_QUAD_ICEGRASS)
 223                 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
 224         else
 225                 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
 226         mdelay(33);
 227         out_8(psurge_sec_intr, ~0);
 228         PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
 229         PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
 230         if (psurge_type != PSURGE_QUAD_ICEGRASS)
 231                 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
 232         PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
 233         mdelay(33);
 234         PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
 235         mdelay(33);
 236         PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
 237         mdelay(33);
 238 }
 239
 240 static int __init smp_psurge_probe(void)
 241 {
 242         int i, ncpus;
 243         struct device_node *dn;
 244
 245         /* We don't do SMP on the PPC601 -- paulus */
 246         if (PVR_VER(mfspr(SPRN_PVR)) == 1)
 247                 return 1;
 248
 249         /*
 250          * The powersurge cpu board can be used in the generation
 251          * of powermacs that have a socket for an upgradeable cpu card,
 252          * including the 7500, 8500, 9500, 9600.
 253          * The device tree doesn't tell you if you have 2 cpus because
 254          * OF doesn't know anything about the 2nd processor.
 255          * Instead we look for magic bits in magic registers,
 256          * in the hammerhead memory controller in the case of the
 257          * dual-cpu powersurge board.  -- paulus.
 258          */
 259         dn = of_find_node_by_name(NULL, "hammerhead");
 260         if (dn == NULL)
 261                 return 1;
 262         of_node_put(dn);
 263
 264         hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
 265         quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
 266         psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
 267
 268         psurge_type = psurge_quad_probe();
 269         if (psurge_type != PSURGE_DUAL) {
 270                 psurge_quad_init();
 271                 /* All released cards using this HW design have 4 CPUs */
 272                 ncpus = 4;
 273                 /* No sure how timebase sync works on those, let's use SW */
 274                 smp_ops->give_timebase = smp_generic_give_timebase;
 275                 smp_ops->take_timebase = smp_generic_take_timebase;
 276         } else {
 277                 iounmap(quad_base);
 278                 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
 279                         /* not a dual-cpu card */
 280                         iounmap(hhead_base);
 281                         psurge_type = PSURGE_NONE;
 282                         return 1;
 283                 }
 284                 ncpus = 2;
 285         }
 286
 287         psurge_start = ioremap(PSURGE_START, 4);
 288         psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
 289
 290         /* This is necessary because OF doesn't know about the
 291          * secondary cpu(s), and thus there aren't nodes in the
 292          * device tree for them, and smp_setup_cpu_maps hasn't
 293          * set their bits in cpu_present_mask.
 294          */
 295         if (ncpus > NR_CPUS)
 296                 ncpus = NR_CPUS;
 297         for (i = 1; i < ncpus ; ++i)
 298                 set_cpu_present(i, true);
 299
 300         if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
 301
 302         return ncpus;
 303 }
 304
 305 static int __init smp_psurge_kick_cpu(int nr)
 306 {
 307         unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
 308         unsigned long a, flags;
 309         int i, j;
 310
 311         /* Defining this here is evil ... but I prefer hiding that
 312          * crap to avoid giving people ideas that they can do the
 313          * same.
 314          */
 315         extern volatile unsigned int cpu_callin_map[NR_CPUS];
 316
 317         /* may need to flush here if secondary bats aren't setup */
 318         for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
 319                 asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
 320         asm volatile("sync");
 321
 322         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
 323
 324         /* This is going to freeze the timeebase, we disable interrupts */
 325         local_irq_save(flags);
 326
 327         out_be32(psurge_start, start);
 328         mb();
 329
 330         psurge_set_ipi(nr);
 331
 332         /*
 333          * We can't use udelay here because the timebase is now frozen.
 334          */
 335         for (i = 0; i < 2000; ++i)
 336                 asm volatile("nop" : : : "memory");
 337         psurge_clr_ipi(nr);
 338
 339         /*
 340          * Also, because the timebase is frozen, we must not return to the
 341          * caller which will try to do udelay's etc... Instead, we wait -here-
 342          * for the CPU to callin.
 343          */
 344         for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) {
 345                 for (j = 1; j < 10000; j++)
 346                         asm volatile("nop" : : : "memory");
 347                 asm volatile("sync" : : : "memory");
 348         }
 349         if (!cpu_callin_map[nr])
 350                 goto stuck;
 351
 352         /* And we do the TB sync here too for standard dual CPU cards */
 353         if (psurge_type == PSURGE_DUAL) {
 354                 while(!tb_req)
 355                         barrier();
 356                 tb_req = 0;
 357                 mb();
 358                 timebase = get_tb();
 359                 mb();
 360                 while (timebase)
 361                         barrier();
 362                 mb();
 363         }
 364  stuck:
 365         /* now interrupt the secondary, restarting both TBs */
 366         if (psurge_type == PSURGE_DUAL)
 367                 psurge_set_ipi(1);
 368
 369         if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
 370
 371         return 0;
 372 }
 373
 374 static struct irqaction psurge_irqaction = {
 375         .handler = psurge_primary_intr,
 376         .flags = IRQF_DISABLED,
 377         .name = "primary IPI",
 378 };
 379
 380 static void __init smp_psurge_setup_cpu(int cpu_nr)
 381 {
 382         if (cpu_nr != 0)
 383                 return;
 384
 385         /* reset the entry point so if we get another intr we won't
 386          * try to startup again */
 387         out_be32(psurge_start, 0x100);
 388         if (setup_irq(irq_create_mapping(NULL, 30), &psurge_irqaction))
 389                 printk(KERN_ERR "Couldn't get primary IPI interrupt");
 390 }
 391
 392 void __init smp_psurge_take_timebase(void)
 393 {
 394         if (psurge_type != PSURGE_DUAL)
 395                 return;
 396
 397         tb_req = 1;
 398         mb();
 399         while (!timebase)
 400                 barrier();
 401         mb();
 402         set_tb(timebase >> 32, timebase & 0xffffffff);
 403         timebase = 0;
 404         mb();
 405         set_dec(tb_ticks_per_jiffy/2);
 406 }
 407
 408 void __init smp_psurge_give_timebase(void)
 409 {
 410         /* Nothing to do here */
 411 }
 412
 413 /* PowerSurge-style Macs */
 414 struct smp_ops_t psurge_smp_ops = {
 415         .message_pass   = smp_muxed_ipi_message_pass,
 416         .cause_ipi      = smp_psurge_cause_ipi,
 417         .probe          = smp_psurge_probe,
 418         .kick_cpu       = smp_psurge_kick_cpu,
 419         .setup_cpu      = smp_psurge_setup_cpu,
 420         .give_timebase  = smp_psurge_give_timebase,
 421         .take_timebase  = smp_psurge_take_timebase,
 422 };
 423 #endif /* CONFIG_PPC32 - actually powersurge support */
 424
 425 /*
 426  * Core 99 and later support
 427  */
 428
 429
 430 static void smp_core99_give_timebase(void)
 431 {
 432         unsigned long flags;
 433
 434         local_irq_save(flags);
 435
 436         while(!tb_req)
 437                 barrier();
 438         tb_req = 0;
 439         (*pmac_tb_freeze)(1);
 440         mb();
 441         timebase = get_tb();
 442         mb();
 443         while (timebase)
 444                 barrier();
 445         mb();
 446         (*pmac_tb_freeze)(0);
 447         mb();
 448
 449         local_irq_restore(flags);
 450 }
 451
 452
 453 static void __devinit smp_core99_take_timebase(void)
 454 {
 455         unsigned long flags;
 456
 457         local_irq_save(flags);
 458
 459         tb_req = 1;
 460         mb();
 461         while (!timebase)
 462                 barrier();
 463         mb();
 464         set_tb(timebase >> 32, timebase & 0xffffffff);
 465         timebase = 0;
 466         mb();
 467
 468         local_irq_restore(flags);
 469 }
 470
 471 #ifdef CONFIG_PPC64
 472 /*
 473  * G5s enable/disable the timebase via an i2c-connected clock chip.
 474  */
 475 static struct pmac_i2c_bus *pmac_tb_clock_chip_host;
 476 static u8 pmac_tb_pulsar_addr;
 477
 478 static void smp_core99_cypress_tb_freeze(int freeze)
 479 {
 480         u8 data;
 481         int rc;
 482
 483         /* Strangely, the device-tree says address is 0xd2, but darwin
 484          * accesses 0xd0 ...
 485          */
 486         pmac_i2c_setmode(pmac_tb_clock_chip_host,
 487                          pmac_i2c_mode_combined);
 488         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
 489                            0xd0 | pmac_i2c_read,
 490                            1, 0x81, &data, 1);
 491         if (rc != 0)
 492                 goto bail;
 493
 494         data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
 495
 496         pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
 497         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
 498                            0xd0 | pmac_i2c_write,
 499                            1, 0x81, &data, 1);
 500
 501  bail:
 502         if (rc != 0) {
 503                 printk("Cypress Timebase %s rc: %d\n",
 504                        freeze ? "freeze" : "unfreeze", rc);
 505                 panic("Timebase freeze failed !\n");
 506         }
 507 }
 508
 509
 510 static void smp_core99_pulsar_tb_freeze(int freeze)
 511 {
 512         u8 data;
 513         int rc;
 514
 515         pmac_i2c_setmode(pmac_tb_clock_chip_host,
 516                          pmac_i2c_mode_combined);
 517         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
 518                            pmac_tb_pulsar_addr | pmac_i2c_read,
 519                            1, 0x2e, &data, 1);
 520         if (rc != 0)
 521                 goto bail;
 522
 523         data = (data & 0x88) | (freeze ? 0x11 : 0x22);
 524
 525         pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
 526         rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
 527                            pmac_tb_pulsar_addr | pmac_i2c_write,
 528                            1, 0x2e, &data, 1);
 529  bail:
 530         if (rc != 0) {
 531                 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
 532                        freeze ? "freeze" : "unfreeze", rc);
 533                 panic("Timebase freeze failed !\n");
 534         }
 535 }
 536
 537 static void __init smp_core99_setup_i2c_hwsync(int ncpus)
 538 {
 539         struct device_node *cc = NULL;
 540         struct device_node *p;
 541         const char *name = NULL;
 542         const u32 *reg;
 543         int ok;
 544
 545         /* Look for the clock chip */
 546         while ((cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL) {
 547                 p = of_get_parent(cc);
 548                 ok = p && of_device_is_compatible(p, "uni-n-i2c");
 549                 of_node_put(p);
 550                 if (!ok)
 551                         continue;
 552
 553                 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc);
 554                 if (pmac_tb_clock_chip_host == NULL)
 555                         continue;
 556                 reg = of_get_property(cc, "reg", NULL);
 557                 if (reg == NULL)
 558                         continue;
 559                 switch (*reg) {
 560                 case 0xd2:
 561                         if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) {
 562                                 pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
 563                                 pmac_tb_pulsar_addr = 0xd2;
 564                                 name = "Pulsar";
 565                         } else if (of_device_is_compatible(cc, "cy28508")) {
 566                                 pmac_tb_freeze = smp_core99_cypress_tb_freeze;
 567                                 name = "Cypress";
 568                         }
 569                         break;
 570                 case 0xd4:
 571                         pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
 572                         pmac_tb_pulsar_addr = 0xd4;
 573                         name = "Pulsar";
 574                         break;
 575                 }
 576                 if (pmac_tb_freeze != NULL)
 577                         break;
 578         }
 579         if (pmac_tb_freeze != NULL) {
 580                 /* Open i2c bus for synchronous access */
 581                 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) {
 582                         printk(KERN_ERR "Failed top open i2c bus for clock"
 583                                " sync, fallback to software sync !\n");
 584                         goto no_i2c_sync;
 585                 }
 586                 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n",
 587                        name);
 588                 return;
 589         }
 590  no_i2c_sync:
 591         pmac_tb_freeze = NULL;
 592         pmac_tb_clock_chip_host = NULL;
 593 }
 594
 595
 596
 597 /*
 598  * Newer G5s uses a platform function
 599  */
 600
 601 static void smp_core99_pfunc_tb_freeze(int freeze)
 602 {
 603         struct device_node *cpus;
 604         struct pmf_args args;
 605
 606         cpus = of_find_node_by_path("/cpus");
 607         BUG_ON(cpus == NULL);
 608         args.count = 1;
 609         args.u[0].v = !freeze;
 610         pmf_call_function(cpus, "cpu-timebase", &args);
 611         of_node_put(cpus);
 612 }
 613
 614 #else /* CONFIG_PPC64 */
 615
 616 /*
 617  * SMP G4 use a GPIO to enable/disable the timebase.
 618  */
 619
 620 static unsigned int core99_tb_gpio;     /* Timebase freeze GPIO */
 621
 622 static void smp_core99_gpio_tb_freeze(int freeze)
 623 {
 624         if (freeze)
 625                 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
 626         else
 627                 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
 628         pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
 629 }
 630
 631
 632 #endif /* !CONFIG_PPC64 */
 633
 634 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
 635 volatile static long int core99_l2_cache;
 636 volatile static long int core99_l3_cache;
 637
 638 static void __devinit core99_init_caches(int cpu)
 639 {
 640 #ifndef CONFIG_PPC64
 641         if (!cpu_has_feature(CPU_FTR_L2CR))
 642                 return;
 643
 644         if (cpu == 0) {
 645                 core99_l2_cache = _get_L2CR();
 646                 printk("CPU0: L2CR is %lx\n", core99_l2_cache);
 647         } else {
 648                 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
 649                 _set_L2CR(0);
 650                 _set_L2CR(core99_l2_cache);
 651                 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
 652         }
 653
 654         if (!cpu_has_feature(CPU_FTR_L3CR))
 655                 return;
 656
 657         if (cpu == 0){
 658                 core99_l3_cache = _get_L3CR();
 659                 printk("CPU0: L3CR is %lx\n", core99_l3_cache);
 660         } else {
 661                 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
 662                 _set_L3CR(0);
 663                 _set_L3CR(core99_l3_cache);
 664                 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
 665         }
 666 #endif /* !CONFIG_PPC64 */
 667 }
 668
 669 static void __init smp_core99_setup(int ncpus)
 670 {
 671 #ifdef CONFIG_PPC64
 672
 673         /* i2c based HW sync on some G5s */
 674         if (of_machine_is_compatible("PowerMac7,2") ||
 675             of_machine_is_compatible("PowerMac7,3") ||
 676             of_machine_is_compatible("RackMac3,1"))
 677                 smp_core99_setup_i2c_hwsync(ncpus);
 678
 679         /* pfunc based HW sync on recent G5s */
 680         if (pmac_tb_freeze == NULL) {
 681                 struct device_node *cpus =
 682                         of_find_node_by_path("/cpus");
 683                 if (cpus &&
 684                     of_get_property(cpus, "platform-cpu-timebase", NULL)) {
 685                         pmac_tb_freeze = smp_core99_pfunc_tb_freeze;
 686                         printk(KERN_INFO "Processor timebase sync using"
 687                                " platform function\n");
 688                 }
 689         }
 690
 691 #else /* CONFIG_PPC64 */
 692
 693         /* GPIO based HW sync on ppc32 Core99 */
 694         if (pmac_tb_freeze == NULL && !of_machine_is_compatible("MacRISC4")) {
 695                 struct device_node *cpu;
 696                 const u32 *tbprop = NULL;
 697
 698                 core99_tb_gpio = KL_GPIO_TB_ENABLE;     /* default value */
 699                 cpu = of_find_node_by_type(NULL, "cpu");
 700                 if (cpu != NULL) {
 701                         tbprop = of_get_property(cpu, "timebase-enable", NULL);
 702                         if (tbprop)
 703                                 core99_tb_gpio = *tbprop;
 704                         of_node_put(cpu);
 705                 }
 706                 pmac_tb_freeze = smp_core99_gpio_tb_freeze;
 707                 printk(KERN_INFO "Processor timebase sync using"
 708                        " GPIO 0x%02x\n", core99_tb_gpio);
 709         }
 710
 711 #endif /* CONFIG_PPC64 */
 712
 713         /* No timebase sync, fallback to software */
 714         if (pmac_tb_freeze == NULL) {
 715                 smp_ops->give_timebase = smp_generic_give_timebase;
 716                 smp_ops->take_timebase = smp_generic_take_timebase;
 717                 printk(KERN_INFO "Processor timebase sync using software\n");
 718         }
 719
 720 #ifndef CONFIG_PPC64
 721         {
 722                 int i;
 723
 724                 /* XXX should get this from reg properties */
 725                 for (i = 1; i < ncpus; ++i)
 726                         set_hard_smp_processor_id(i, i);
 727         }
 728 #endif
 729
 730         /* 32 bits SMP can't NAP */
 731         if (!of_machine_is_compatible("MacRISC4"))
 732                 powersave_nap = 0;
 733 }
 734
 735 static int __init smp_core99_probe(void)
 736 {
 737         struct device_node *cpus;
 738         int ncpus = 0;
 739
 740         if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
 741
 742         /* Count CPUs in the device-tree */
 743         for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;)
 744                 ++ncpus;
 745
 746         printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
 747
 748         /* Nothing more to do if less than 2 of them */
 749         if (ncpus <= 1)
 750                 return 1;
 751
 752         /* We need to perform some early initialisations before we can start
 753          * setting up SMP as we are running before initcalls
 754          */
 755         pmac_pfunc_base_install();
 756         pmac_i2c_init();
 757
 758         /* Setup various bits like timebase sync method, ability to nap, ... */
 759         smp_core99_setup(ncpus);
 760
 761         /* Install IPIs */
 762         mpic_request_ipis();
 763
 764         /* Collect l2cr and l3cr values from CPU 0 */
 765         core99_init_caches(0);
 766
 767         return ncpus;
 768 }
 769
 770 static int __devinit smp_core99_kick_cpu(int nr)
 771 {
 772         unsigned int save_vector;
 773         unsigned long target, flags;
 774         unsigned int *vector = (unsigned int *)(PAGE_OFFSET+0x100);
 775
 776         if (nr < 0 || nr > 3)
 777                 return -ENOENT;
 778
 779         if (ppc_md.progress)
 780                 ppc_md.progress("smp_core99_kick_cpu", 0x346);
 781
 782         local_irq_save(flags);
 783
 784         /* Save reset vector */
 785         save_vector = *vector;
 786
 787         /* Setup fake reset vector that does
 788          *   b __secondary_start_pmac_0 + nr*8
 789          */
 790         target = (unsigned long) __secondary_start_pmac_0 + nr * 8;
 791         patch_branch(vector, target, BRANCH_SET_LINK);
 792
 793         /* Put some life in our friend */
 794         pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
 795
 796         /* FIXME: We wait a bit for the CPU to take the exception, I should
 797          * instead wait for the entry code to set something for me. Well,
 798          * ideally, all that crap will be done in prom.c and the CPU left
 799          * in a RAM-based wait loop like CHRP.
 800          */
 801         mdelay(1);
 802
 803         /* Restore our exception vector */
 804         *vector = save_vector;
 805         flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
 806
 807         local_irq_restore(flags);
 808         if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
 809
 810         return 0;
 811 }
 812
 813 static void __devinit smp_core99_setup_cpu(int cpu_nr)
 814 {
 815         /* Setup L2/L3 */
 816         if (cpu_nr != 0)
 817                 core99_init_caches(cpu_nr);
 818
 819         /* Setup openpic */
 820         mpic_setup_this_cpu();
 821 }
 822
 823 #ifdef CONFIG_PPC64
 824 #ifdef CONFIG_HOTPLUG_CPU
 825 static int smp_core99_cpu_notify(struct notifier_block *self,
 826                                  unsigned long action, void *hcpu)
 827 {
 828         int rc;
 829
 830         switch(action) {
 831         case CPU_UP_PREPARE:
 832         case CPU_UP_PREPARE_FROZEN:
 833                 /* Open i2c bus if it was used for tb sync */
 834                 if (pmac_tb_clock_chip_host) {
 835                         rc = pmac_i2c_open(pmac_tb_clock_chip_host, 1);
 836                         if (rc) {
 837                                 pr_err("Failed to open i2c bus for time sync\n");
 838                                 return notifier_from_errno(rc);
 839                         }
 840                 }
 841                 break;
 842         case CPU_ONLINE:
 843         case CPU_UP_CANCELED:
 844                 /* Close i2c bus if it was used for tb sync */
 845                 if (pmac_tb_clock_chip_host)
 846                         pmac_i2c_close(pmac_tb_clock_chip_host);
 847                 break;
 848         default:
 849                 break;
 850         }
 851         return NOTIFY_OK;
 852 }
 853
 854 static struct notifier_block __cpuinitdata smp_core99_cpu_nb = {
 855         .notifier_call  = smp_core99_cpu_notify,
 856 };
 857 #endif /* CONFIG_HOTPLUG_CPU */
 858
 859 static void __init smp_core99_bringup_done(void)
 860 {
 861         extern void g5_phy_disable_cpu1(void);
 862
 863         /* Close i2c bus if it was used for tb sync */
 864         if (pmac_tb_clock_chip_host)
 865                 pmac_i2c_close(pmac_tb_clock_chip_host);
 866
 867         /* If we didn't start the second CPU, we must take
 868          * it off the bus.
 869          */
 870         if (of_machine_is_compatible("MacRISC4") &&
 871             num_online_cpus() < 2) {
 872                 set_cpu_present(1, false);
 873                 g5_phy_disable_cpu1();
 874         }
 875 #ifdef CONFIG_HOTPLUG_CPU
 876         register_cpu_notifier(&smp_core99_cpu_nb);
 877 #endif
 878
 879         if (ppc_md.progress)
 880                 ppc_md.progress("smp_core99_bringup_done", 0x349);
 881 }
 882 #endif /* CONFIG_PPC64 */
 883
 884 #ifdef CONFIG_HOTPLUG_CPU
 885
 886 static int smp_core99_cpu_disable(void)
 887 {
 888         int rc = generic_cpu_disable();
 889         if (rc)
 890                 return rc;
 891
 892         mpic_cpu_set_priority(0xf);
 893
 894         return 0;
 895 }
 896
 897 #ifdef CONFIG_PPC32
 898
 899 static void pmac_cpu_die(void)
 900 {
 901         int cpu = smp_processor_id();
 902
 903         local_irq_disable();
 904         idle_task_exit();
 905         pr_debug("CPU%d offline\n", cpu);
 906         generic_set_cpu_dead(cpu);
 907         smp_wmb();
 908         mb();
 909         low_cpu_die();
 910 }
 911
 912 #else /* CONFIG_PPC32 */
 913
 914 static void pmac_cpu_die(void)
 915 {
 916         int cpu = smp_processor_id();
 917
 918         local_irq_disable();
 919         idle_task_exit();
 920
 921         /*
 922          * turn off as much as possible, we'll be
 923          * kicked out as this will only be invoked
 924          * on core99 platforms for now ...
 925          */
 926
 927         printk(KERN_INFO "CPU#%d offline\n", cpu);
 928         generic_set_cpu_dead(cpu);
 929         smp_wmb();
 930
 931         /*
 932          * Re-enable interrupts. The NAP code needs to enable them
 933          * anyways, do it now so we deal with the case where one already
 934          * happened while soft-disabled.
 935          * We shouldn't get any external interrupts, only decrementer, and the
 936          * decrementer handler is safe for use on offline CPUs
 937          */
 938         local_irq_enable();
 939
 940         while (1) {
 941                 /* let's not take timer interrupts too often ... */
 942                 set_dec(0x7fffffff);
 943
 944                 /* Enter NAP mode */
 945                 power4_idle();
 946         }
 947 }
 948
 949 #endif /* else CONFIG_PPC32 */
 950 #endif /* CONFIG_HOTPLUG_CPU */
 951
 952 /* Core99 Macs (dual G4s and G5s) */
 953 struct smp_ops_t core99_smp_ops = {
 954         .message_pass   = smp_mpic_message_pass,
 955         .probe          = smp_core99_probe,
 956 #ifdef CONFIG_PPC64
 957         .bringup_done   = smp_core99_bringup_done,
 958 #endif
 959         .kick_cpu       = smp_core99_kick_cpu,
 960         .setup_cpu      = smp_core99_setup_cpu,
 961         .give_timebase  = smp_core99_give_timebase,
 962         .take_timebase  = smp_core99_take_timebase,
 963 #if defined(CONFIG_HOTPLUG_CPU)
 964         .cpu_disable    = smp_core99_cpu_disable,
 965         .cpu_die        = generic_cpu_die,
 966 #endif
 967 };
 968
 969 void __init pmac_setup_smp(void)
 970 {
 971         struct device_node *np;
 972
 973         /* Check for Core99 */
 974         np = of_find_node_by_name(NULL, "uni-n");
 975         if (!np)
 976                 np = of_find_node_by_name(NULL, "u3");
 977         if (!np)
 978                 np = of_find_node_by_name(NULL, "u4");
 979         if (np) {
 980                 of_node_put(np);
 981                 smp_ops = &core99_smp_ops;
 982         }
 983 #ifdef CONFIG_PPC32
 984         else {
 985                 /* We have to set bits in cpu_possible_mask here since the
 986                  * secondary CPU(s) aren't in the device tree. Various
 987                  * things won't be initialized for CPUs not in the possible
 988                  * map, so we really need to fix it up here.
 989                  */
 990                 int cpu;
 991
 992                 for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu)
 993                         set_cpu_possible(cpu, true);
 994                 smp_ops = &psurge_smp_ops;
 995         }
 996 #endif /* CONFIG_PPC32 */
 997
 998 #ifdef CONFIG_HOTPLUG_CPU
 999         ppc_md.cpu_die = pmac_cpu_die;
1000 #endif
1001 }
1002
1003