2 * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/string.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
20 #include <asm/sections.h>
23 #include <asm/pci-bridge.h>
24 #include <asm/machdep.h>
25 #include <asm/iommu.h>
26 #include <asm/ppc-pci.h>
31 #define DBG(x...) printk(x)
36 static struct pci_controller *u3_agp, *u3_ht;
38 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
40 for (; node != 0;node = node->sibling) {
42 const unsigned int *class_code;
45 /* For PCI<->PCI bridges or CardBus bridges, we go down */
46 class_code = get_property(node, "class-code", NULL);
47 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
48 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
50 bus_range = get_property(node, "bus-range", &len);
51 if (bus_range != NULL && len > 2 * sizeof(int)) {
52 if (bus_range[1] > higher)
53 higher = bus_range[1];
55 higher = fixup_one_level_bus_range(node->child, higher);
60 /* This routine fixes the "bus-range" property of all bridges in the
61 * system since they tend to have their "last" member wrong on macs
63 * Note that the bus numbers manipulated here are OF bus numbers, they
64 * are not Linux bus numbers.
66 static void __init fixup_bus_range(struct device_node *bridge)
69 struct property *prop;
72 /* Lookup the "bus-range" property for the hose */
73 prop = of_find_property(bridge, "bus-range", &len);
74 if (prop == NULL || prop->value == NULL || len < 2 * sizeof(int)) {
75 printk(KERN_WARNING "Can't get bus-range for %s\n",
79 bus_range = (int *)prop->value;
80 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
84 #define U3_AGP_CFA0(devfn, off) \
85 ((1 << (unsigned long)PCI_SLOT(dev_fn)) \
86 | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
87 | (((unsigned long)(off)) & 0xFCUL))
89 #define U3_AGP_CFA1(bus, devfn, off) \
90 ((((unsigned long)(bus)) << 16) \
91 |(((unsigned long)(devfn)) << 8) \
92 |(((unsigned long)(off)) & 0xFCUL) \
95 static unsigned long u3_agp_cfg_access(struct pci_controller* hose,
96 u8 bus, u8 dev_fn, u8 offset)
100 if (bus == hose->first_busno) {
101 if (dev_fn < (11 << 3))
103 caddr = U3_AGP_CFA0(dev_fn, offset);
105 caddr = U3_AGP_CFA1(bus, dev_fn, offset);
107 /* Uninorth will return garbage if we don't read back the value ! */
109 out_le32(hose->cfg_addr, caddr);
110 } while (in_le32(hose->cfg_addr) != caddr);
113 return ((unsigned long)hose->cfg_data) + offset;
116 static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
117 int offset, int len, u32 *val)
119 struct pci_controller *hose;
122 hose = pci_bus_to_host(bus);
124 return PCIBIOS_DEVICE_NOT_FOUND;
126 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
128 return PCIBIOS_DEVICE_NOT_FOUND;
130 * Note: the caller has already checked that offset is
131 * suitably aligned and that len is 1, 2 or 4.
135 *val = in_8((u8 *)addr);
138 *val = in_le16((u16 *)addr);
141 *val = in_le32((u32 *)addr);
144 return PCIBIOS_SUCCESSFUL;
147 static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
148 int offset, int len, u32 val)
150 struct pci_controller *hose;
153 hose = pci_bus_to_host(bus);
155 return PCIBIOS_DEVICE_NOT_FOUND;
157 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
159 return PCIBIOS_DEVICE_NOT_FOUND;
161 * Note: the caller has already checked that offset is
162 * suitably aligned and that len is 1, 2 or 4.
166 out_8((u8 *)addr, val);
167 (void) in_8((u8 *)addr);
170 out_le16((u16 *)addr, val);
171 (void) in_le16((u16 *)addr);
174 out_le32((u32 *)addr, val);
175 (void) in_le32((u32 *)addr);
178 return PCIBIOS_SUCCESSFUL;
181 static struct pci_ops u3_agp_pci_ops =
188 #define U3_HT_CFA0(devfn, off) \
189 ((((unsigned long)devfn) << 8) | offset)
190 #define U3_HT_CFA1(bus, devfn, off) \
191 (U3_HT_CFA0(devfn, off) \
192 + (((unsigned long)bus) << 16) \
195 static unsigned long u3_ht_cfg_access(struct pci_controller* hose,
196 u8 bus, u8 devfn, u8 offset)
198 if (bus == hose->first_busno) {
199 if (PCI_SLOT(devfn) == 0)
201 return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset);
203 return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset);
206 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
207 int offset, int len, u32 *val)
209 struct pci_controller *hose;
212 hose = pci_bus_to_host(bus);
214 return PCIBIOS_DEVICE_NOT_FOUND;
217 return PCIBIOS_BAD_REGISTER_NUMBER;
219 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
221 return PCIBIOS_DEVICE_NOT_FOUND;
224 * Note: the caller has already checked that offset is
225 * suitably aligned and that len is 1, 2 or 4.
229 *val = in_8((u8 *)addr);
232 *val = in_le16((u16 *)addr);
235 *val = in_le32((u32 *)addr);
238 return PCIBIOS_SUCCESSFUL;
241 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
242 int offset, int len, u32 val)
244 struct pci_controller *hose;
247 hose = pci_bus_to_host(bus);
249 return PCIBIOS_DEVICE_NOT_FOUND;
252 return PCIBIOS_BAD_REGISTER_NUMBER;
254 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
256 return PCIBIOS_DEVICE_NOT_FOUND;
258 * Note: the caller has already checked that offset is
259 * suitably aligned and that len is 1, 2 or 4.
263 out_8((u8 *)addr, val);
264 (void) in_8((u8 *)addr);
267 out_le16((u16 *)addr, val);
268 (void) in_le16((u16 *)addr);
271 out_le32((u32 *)addr, val);
272 (void) in_le32((u32 *)addr);
275 return PCIBIOS_SUCCESSFUL;
278 static struct pci_ops u3_ht_pci_ops =
284 static void __init setup_u3_agp(struct pci_controller* hose)
286 /* On G5, we move AGP up to high bus number so we don't need
287 * to reassign bus numbers for HT. If we ever have P2P bridges
288 * on AGP, we'll have to move pci_assign_all_buses to the
289 * pci_controller structure so we enable it for AGP and not for
291 * We hard code the address because of the different size of
292 * the reg address cell, we shall fix that by killing struct
293 * reg_property and using some accessor functions instead
295 hose->first_busno = 0xf0;
296 hose->last_busno = 0xff;
297 hose->ops = &u3_agp_pci_ops;
298 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
299 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
304 static void __init setup_u3_ht(struct pci_controller* hose)
306 hose->ops = &u3_ht_pci_ops;
308 /* We hard code the address because of the different size of
309 * the reg address cell, we shall fix that by killing struct
310 * reg_property and using some accessor functions instead
312 hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000);
314 hose->first_busno = 0;
315 hose->last_busno = 0xef;
320 static int __init add_bridge(struct device_node *dev)
323 struct pci_controller *hose;
325 const int *bus_range;
328 DBG("Adding PCI host bridge %s\n", dev->full_name);
330 bus_range = get_property(dev, "bus-range", &len);
331 if (bus_range == NULL || len < 2 * sizeof(int)) {
332 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
336 hose = pcibios_alloc_controller(dev);
339 hose->first_busno = bus_range ? bus_range[0] : 0;
340 hose->last_busno = bus_range ? bus_range[1] : 0xff;
343 if (device_is_compatible(dev, "u3-agp")) {
345 disp_name = "U3-AGP";
347 } else if (device_is_compatible(dev, "u3-ht")) {
352 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
353 disp_name, hose->first_busno, hose->last_busno);
355 /* Interpret the "ranges" property */
356 /* This also maps the I/O region and sets isa_io/mem_base */
357 pci_process_bridge_OF_ranges(hose, dev, primary);
358 pci_setup_phb_io(hose, primary);
360 /* Fixup "bus-range" OF property */
361 fixup_bus_range(dev);
367 void __init maple_pcibios_fixup(void)
369 struct pci_dev *dev = NULL;
371 DBG(" -> maple_pcibios_fixup\n");
373 for_each_pci_dev(dev)
374 pci_read_irq_line(dev);
376 DBG(" <- maple_pcibios_fixup\n");
379 static void __init maple_fixup_phb_resources(void)
381 struct pci_controller *hose, *tmp;
383 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
384 unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base;
385 hose->io_resource.start += offset;
386 hose->io_resource.end += offset;
387 printk(KERN_INFO "PCI Host %d, io start: %llx; io end: %llx\n",
389 (unsigned long long)hose->io_resource.start,
390 (unsigned long long)hose->io_resource.end);
394 void __init maple_pci_init(void)
396 struct device_node *np, *root;
397 struct device_node *ht = NULL;
399 /* Probe root PCI hosts, that is on U3 the AGP host and the
400 * HyperTransport host. That one is actually "kept" around
401 * and actually added last as it's resource management relies
402 * on the AGP resources to have been setup first
404 root = of_find_node_by_path("/");
406 printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n");
409 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
410 if (np->name == NULL)
412 if (strcmp(np->name, "pci") == 0) {
413 if (add_bridge(np) == 0)
416 if (strcmp(np->name, "ht") == 0) {
423 /* Now setup the HyperTransport host if we found any
425 if (ht && add_bridge(ht) != 0)
428 /* Fixup the IO resources on our host bridges as the common code
429 * does it only for childs of the host bridges
431 maple_fixup_phb_resources();
433 /* Setup the linkage between OF nodes and PHBs */
436 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
437 * assume there is no P2P bridge on the AGP bus, which should be a
438 * safe assumptions hopefully.
441 struct device_node *np = u3_agp->arch_data;
442 PCI_DN(np)->busno = 0xf0;
443 for (np = np->child; np; np = np->sibling)
444 PCI_DN(np)->busno = 0xf0;
447 /* Tell pci.c to not change any resource allocations. */
451 int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel)
453 struct device_node *np;
454 unsigned int defirq = channel ? 15 : 14;
457 if (pdev->vendor != PCI_VENDOR_ID_AMD ||
458 pdev->device != PCI_DEVICE_ID_AMD_8111_IDE)
461 np = pci_device_to_OF_node(pdev);
464 irq = irq_of_parse_and_map(np, channel & 0x1);
466 printk("Failed to map onboard IDE interrupt for channel %d\n",
473 /* XXX: To remove once all firmwares are ok */
474 static void fixup_maple_ide(struct pci_dev* dev)
476 #if 0 /* Enable this to enable IDE port 0 */
480 pci_read_config_byte(dev, 0x40, &v);
482 pci_write_config_byte(dev, 0x40, v);
485 #if 0 /* fix bus master base */
486 pci_write_config_dword(dev, 0x20, 0xcc01);
487 printk("old ide resource: %lx -> %lx \n",
488 dev->resource[4].start, dev->resource[4].end);
489 dev->resource[4].start = 0xcc00;
490 dev->resource[4].end = 0xcc10;
492 #if 1 /* Enable this to fixup IDE sense/polarity of irqs in IO-APICs */
494 struct pci_dev *apicdev;
497 apicdev = pci_get_slot (dev->bus, PCI_DEVFN(5,0));
499 printk("IDE Fixup IRQ: Can't find IO-APIC !\n");
501 pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*14);
502 pci_read_config_dword(apicdev, 0xf4, &v);
504 pci_write_config_dword(apicdev, 0xf4, v);
505 pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*15);
506 pci_read_config_dword(apicdev, 0xf4, &v);
508 pci_write_config_dword(apicdev, 0xf4, v);
509 pci_dev_put(apicdev);
514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE,