2 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
3 * Copyright (c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
6 * Architecture- / platform-specific boot-time initialization code for
7 * the IBM iSeries LPAR. Adapted from original code by Grant Erickson and
8 * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
19 #include <linux/config.h>
20 #include <linux/init.h>
21 #include <linux/threads.h>
22 #include <linux/smp.h>
23 #include <linux/param.h>
24 #include <linux/string.h>
25 #include <linux/initrd.h>
26 #include <linux/seq_file.h>
27 #include <linux/kdev_t.h>
28 #include <linux/major.h>
29 #include <linux/root_dev.h>
31 #include <asm/processor.h>
32 #include <asm/machdep.h>
35 #include <asm/pgtable.h>
36 #include <asm/mmu_context.h>
37 #include <asm/cputable.h>
38 #include <asm/sections.h>
39 #include <asm/iommu.h>
40 #include <asm/firmware.h>
45 #include <asm/cache.h>
46 #include <asm/sections.h>
47 #include <asm/abs_addr.h>
48 #include <asm/iSeries/HvLpConfig.h>
49 #include <asm/iSeries/HvCallEvent.h>
50 #include <asm/iSeries/HvCallXm.h>
51 #include <asm/iSeries/ItLpQueue.h>
52 #include <asm/iSeries/mf.h>
53 #include <asm/iSeries/HvLpEvent.h>
54 #include <asm/iSeries/LparMap.h>
58 #include "vpd_areas.h"
59 #include "processor_vpd.h"
60 #include "main_store.h"
64 extern void hvlog(char *fmt, ...);
67 #define DBG(fmt...) hvlog(fmt)
72 /* Function Prototypes */
73 extern void ppcdbg_initialize(void);
75 static void build_iSeries_Memory_Map(void);
76 static void iseries_shared_idle(void);
77 static void iseries_dedicated_idle(void);
79 extern void iSeries_pci_final_fixup(void);
81 static void iSeries_pci_final_fixup(void) { }
84 /* Global Variables */
85 int piranha_simulator;
87 extern int rd_size; /* Defined in drivers/block/rd.c */
88 extern unsigned long klimit;
89 extern unsigned long embedded_sysmap_start;
90 extern unsigned long embedded_sysmap_end;
92 extern unsigned long iSeries_recal_tb;
93 extern unsigned long iSeries_recal_titan;
95 static int mf_initialized;
98 unsigned long absStart;
100 unsigned long logicalStart;
101 unsigned long logicalEnd;
105 * Process the main store vpd to determine where the holes in memory are
106 * and return the number of physical blocks and fill in the array of
109 static unsigned long iSeries_process_Condor_mainstore_vpd(
110 struct MemoryBlock *mb_array, unsigned long max_entries)
112 unsigned long holeFirstChunk, holeSizeChunks;
113 unsigned long numMemoryBlocks = 1;
114 struct IoHriMainStoreSegment4 *msVpd =
115 (struct IoHriMainStoreSegment4 *)xMsVpd;
116 unsigned long holeStart = msVpd->nonInterleavedBlocksStartAdr;
117 unsigned long holeEnd = msVpd->nonInterleavedBlocksEndAdr;
118 unsigned long holeSize = holeEnd - holeStart;
120 printk("Mainstore_VPD: Condor\n");
122 * Determine if absolute memory has any
123 * holes so that we can interpret the
124 * access map we get back from the hypervisor
127 mb_array[0].logicalStart = 0;
128 mb_array[0].logicalEnd = 0x100000000;
129 mb_array[0].absStart = 0;
130 mb_array[0].absEnd = 0x100000000;
134 holeStart = holeStart & 0x000fffffffffffff;
135 holeStart = addr_to_chunk(holeStart);
136 holeFirstChunk = holeStart;
137 holeSize = addr_to_chunk(holeSize);
138 holeSizeChunks = holeSize;
139 printk( "Main store hole: start chunk = %0lx, size = %0lx chunks\n",
140 holeFirstChunk, holeSizeChunks );
141 mb_array[0].logicalEnd = holeFirstChunk;
142 mb_array[0].absEnd = holeFirstChunk;
143 mb_array[1].logicalStart = holeFirstChunk;
144 mb_array[1].logicalEnd = 0x100000000 - holeSizeChunks;
145 mb_array[1].absStart = holeFirstChunk + holeSizeChunks;
146 mb_array[1].absEnd = 0x100000000;
148 return numMemoryBlocks;
151 #define MaxSegmentAreas 32
152 #define MaxSegmentAdrRangeBlocks 128
153 #define MaxAreaRangeBlocks 4
155 static unsigned long iSeries_process_Regatta_mainstore_vpd(
156 struct MemoryBlock *mb_array, unsigned long max_entries)
158 struct IoHriMainStoreSegment5 *msVpdP =
159 (struct IoHriMainStoreSegment5 *)xMsVpd;
160 unsigned long numSegmentBlocks = 0;
161 u32 existsBits = msVpdP->msAreaExists;
162 unsigned long area_num;
164 printk("Mainstore_VPD: Regatta\n");
166 for (area_num = 0; area_num < MaxSegmentAreas; ++area_num ) {
167 unsigned long numAreaBlocks;
168 struct IoHriMainStoreArea4 *currentArea;
170 if (existsBits & 0x80000000) {
171 unsigned long block_num;
173 currentArea = &msVpdP->msAreaArray[area_num];
174 numAreaBlocks = currentArea->numAdrRangeBlocks;
175 printk("ms_vpd: processing area %2ld blocks=%ld",
176 area_num, numAreaBlocks);
177 for (block_num = 0; block_num < numAreaBlocks;
179 /* Process an address range block */
180 struct MemoryBlock tempBlock;
184 (unsigned long)currentArea->xAdrRangeBlock[block_num].blockStart;
186 (unsigned long)currentArea->xAdrRangeBlock[block_num].blockEnd;
187 tempBlock.logicalStart = 0;
188 tempBlock.logicalEnd = 0;
189 printk("\n block %ld absStart=%016lx absEnd=%016lx",
190 block_num, tempBlock.absStart,
193 for (i = 0; i < numSegmentBlocks; ++i) {
194 if (mb_array[i].absStart ==
198 if (i == numSegmentBlocks) {
199 if (numSegmentBlocks == max_entries)
200 panic("iSeries_process_mainstore_vpd: too many memory blocks");
201 mb_array[numSegmentBlocks] = tempBlock;
204 printk(" (duplicate)");
210 /* Now sort the blocks found into ascending sequence */
211 if (numSegmentBlocks > 1) {
214 for (m = 0; m < numSegmentBlocks - 1; ++m) {
215 for (n = numSegmentBlocks - 1; m < n; --n) {
216 if (mb_array[n].absStart <
217 mb_array[n-1].absStart) {
218 struct MemoryBlock tempBlock;
220 tempBlock = mb_array[n];
221 mb_array[n] = mb_array[n-1];
222 mb_array[n-1] = tempBlock;
228 * Assign "logical" addresses to each block. These
229 * addresses correspond to the hypervisor "bitmap" space.
230 * Convert all addresses into units of 256K chunks.
233 unsigned long i, nextBitmapAddress;
235 printk("ms_vpd: %ld sorted memory blocks\n", numSegmentBlocks);
236 nextBitmapAddress = 0;
237 for (i = 0; i < numSegmentBlocks; ++i) {
238 unsigned long length = mb_array[i].absEnd -
239 mb_array[i].absStart;
241 mb_array[i].logicalStart = nextBitmapAddress;
242 mb_array[i].logicalEnd = nextBitmapAddress + length;
243 nextBitmapAddress += length;
244 printk(" Bitmap range: %016lx - %016lx\n"
245 " Absolute range: %016lx - %016lx\n",
246 mb_array[i].logicalStart,
247 mb_array[i].logicalEnd,
248 mb_array[i].absStart, mb_array[i].absEnd);
249 mb_array[i].absStart = addr_to_chunk(mb_array[i].absStart &
251 mb_array[i].absEnd = addr_to_chunk(mb_array[i].absEnd &
253 mb_array[i].logicalStart =
254 addr_to_chunk(mb_array[i].logicalStart);
255 mb_array[i].logicalEnd = addr_to_chunk(mb_array[i].logicalEnd);
259 return numSegmentBlocks;
262 static unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock *mb_array,
263 unsigned long max_entries)
266 unsigned long mem_blocks = 0;
268 if (cpu_has_feature(CPU_FTR_SLB))
269 mem_blocks = iSeries_process_Regatta_mainstore_vpd(mb_array,
272 mem_blocks = iSeries_process_Condor_mainstore_vpd(mb_array,
275 printk("Mainstore_VPD: numMemoryBlocks = %ld \n", mem_blocks);
276 for (i = 0; i < mem_blocks; ++i) {
277 printk("Mainstore_VPD: block %3ld logical chunks %016lx - %016lx\n"
278 " abs chunks %016lx - %016lx\n",
279 i, mb_array[i].logicalStart, mb_array[i].logicalEnd,
280 mb_array[i].absStart, mb_array[i].absEnd);
285 static void __init iSeries_get_cmdline(void)
289 /* copy the command line parameter from the primary VSP */
290 HvCallEvent_dmaToSp(cmd_line, 2 * 64* 1024, 256,
291 HvLpDma_Direction_RemoteToLocal);
296 if (!*p || *p == '\n')
303 static void __init iSeries_init_early(void)
305 DBG(" -> iSeries_init_early()\n");
307 ppc64_firmware_features = FW_FEATURE_ISERIES;
311 ppc64_interrupt_controller = IC_ISERIES;
313 #if defined(CONFIG_BLK_DEV_INITRD)
315 * If the init RAM disk has been configured and there is
316 * a non-zero starting address for it, set it up
319 initrd_start = (unsigned long)__va(naca.xRamDisk);
320 initrd_end = initrd_start + naca.xRamDiskSize * PAGE_SIZE;
321 initrd_below_start_ok = 1; // ramdisk in kernel space
322 ROOT_DEV = Root_RAM0;
323 if (((rd_size * 1024) / PAGE_SIZE) < naca.xRamDiskSize)
324 rd_size = (naca.xRamDiskSize * PAGE_SIZE) / 1024;
326 #endif /* CONFIG_BLK_DEV_INITRD */
328 /* ROOT_DEV = MKDEV(VIODASD_MAJOR, 1); */
331 iSeries_recal_tb = get_tb();
332 iSeries_recal_titan = HvCallXm_loadTod();
335 * Initialize the hash table management pointers
340 * Initialize the DMA/TCE management
342 iommu_init_early_iSeries();
344 iSeries_get_cmdline();
346 /* Save unparsed command line copy for /proc/cmdline */
347 strlcpy(saved_command_line, cmd_line, COMMAND_LINE_SIZE);
349 /* Parse early parameters, in particular mem=x */
353 if (memory_limit < systemcfg->physicalMemorySize)
354 systemcfg->physicalMemorySize = memory_limit;
356 printk("Ignoring mem=%lu >= ram_top.\n", memory_limit);
361 /* Initialize machine-dependency vectors */
365 if (itLpNaca.xPirEnvironMode == 0)
366 piranha_simulator = 1;
368 /* Associate Lp Event Queue 0 with processor 0 */
369 HvCallEvent_setLpEventQueueInterruptProc(0, 0);
375 /* If we were passed an initrd, set the ROOT_DEV properly if the values
376 * look sensible. If not, clear initrd reference.
378 #ifdef CONFIG_BLK_DEV_INITRD
379 if (initrd_start >= KERNELBASE && initrd_end >= KERNELBASE &&
380 initrd_end > initrd_start)
381 ROOT_DEV = Root_RAM0;
383 initrd_start = initrd_end = 0;
384 #endif /* CONFIG_BLK_DEV_INITRD */
386 DBG(" <- iSeries_init_early()\n");
389 struct mschunks_map mschunks_map = {
390 /* XXX We don't use these, but Piranha might need them. */
391 .chunk_size = MSCHUNKS_CHUNK_SIZE,
392 .chunk_shift = MSCHUNKS_CHUNK_SHIFT,
393 .chunk_mask = MSCHUNKS_OFFSET_MASK,
395 EXPORT_SYMBOL(mschunks_map);
397 void mschunks_alloc(unsigned long num_chunks)
399 klimit = _ALIGN(klimit, sizeof(u32));
400 mschunks_map.mapping = (u32 *)klimit;
401 klimit += num_chunks * sizeof(u32);
402 mschunks_map.num_chunks = num_chunks;
406 * The iSeries may have very large memories ( > 128 GB ) and a partition
407 * may get memory in "chunks" that may be anywhere in the 2**52 real
408 * address space. The chunks are 256K in size. To map this to the
409 * memory model Linux expects, the AS/400 specific code builds a
410 * translation table to translate what Linux thinks are "physical"
411 * addresses to the actual real addresses. This allows us to make
412 * it appear to Linux that we have contiguous memory starting at
413 * physical address zero while in fact this could be far from the truth.
414 * To avoid confusion, I'll let the words physical and/or real address
415 * apply to the Linux addresses while I'll use "absolute address" to
416 * refer to the actual hardware real address.
418 * build_iSeries_Memory_Map gets information from the Hypervisor and
419 * looks at the Main Store VPD to determine the absolute addresses
420 * of the memory that has been assigned to our partition and builds
421 * a table used to translate Linux's physical addresses to these
422 * absolute addresses. Absolute addresses are needed when
423 * communicating with the hypervisor (e.g. to build HPT entries)
426 static void __init build_iSeries_Memory_Map(void)
428 u32 loadAreaFirstChunk, loadAreaLastChunk, loadAreaSize;
430 u32 hptFirstChunk, hptLastChunk, hptSizeChunks, hptSizePages;
431 u32 totalChunks,moreChunks;
432 u32 currChunk, thisChunk, absChunk;
436 struct MemoryBlock mb[32];
437 unsigned long numMemoryBlocks, curBlock;
439 /* Chunk size on iSeries is 256K bytes */
440 totalChunks = (u32)HvLpConfig_getMsChunks();
441 mschunks_alloc(totalChunks);
444 * Get absolute address of our load area
445 * and map it to physical address 0
446 * This guarantees that the loadarea ends up at physical 0
447 * otherwise, it might not be returned by PLIC as the first
451 loadAreaFirstChunk = (u32)addr_to_chunk(itLpNaca.xLoadAreaAddr);
452 loadAreaSize = itLpNaca.xLoadAreaChunks;
455 * Only add the pages already mapped here.
456 * Otherwise we might add the hpt pages
457 * The rest of the pages of the load area
458 * aren't in the HPT yet and can still
459 * be assigned an arbitrary physical address
461 if ((loadAreaSize * 64) > HvPagesToMap)
462 loadAreaSize = HvPagesToMap / 64;
464 loadAreaLastChunk = loadAreaFirstChunk + loadAreaSize - 1;
467 * TODO Do we need to do something if the HPT is in the 64MB load area?
468 * This would be required if the itLpNaca.xLoadAreaChunks includes
472 printk("Mapping load area - physical addr = 0000000000000000\n"
473 " absolute addr = %016lx\n",
474 chunk_to_addr(loadAreaFirstChunk));
475 printk("Load area size %dK\n", loadAreaSize * 256);
477 for (nextPhysChunk = 0; nextPhysChunk < loadAreaSize; ++nextPhysChunk)
478 mschunks_map.mapping[nextPhysChunk] =
479 loadAreaFirstChunk + nextPhysChunk;
482 * Get absolute address of our HPT and remember it so
483 * we won't map it to any physical address
485 hptFirstChunk = (u32)addr_to_chunk(HvCallHpt_getHptAddress());
486 hptSizePages = (u32)HvCallHpt_getHptPages();
487 hptSizeChunks = hptSizePages >> (MSCHUNKS_CHUNK_SHIFT - PAGE_SHIFT);
488 hptLastChunk = hptFirstChunk + hptSizeChunks - 1;
490 printk("HPT absolute addr = %016lx, size = %dK\n",
491 chunk_to_addr(hptFirstChunk), hptSizeChunks * 256);
493 ppc64_pft_size = __ilog2(hptSizePages * PAGE_SIZE);
496 * The actual hashed page table is in the hypervisor,
497 * we have no direct access
502 * Determine if absolute memory has any
503 * holes so that we can interpret the
504 * access map we get back from the hypervisor
507 numMemoryBlocks = iSeries_process_mainstore_vpd(mb, 32);
510 * Process the main store access map from the hypervisor
511 * to build up our physical -> absolute translation table
516 moreChunks = totalChunks;
519 map = HvCallSm_get64BitsOfAccessMap(itLpNaca.xLpIndex,
521 thisChunk = currChunk;
523 chunkBit = map >> 63;
527 while (thisChunk >= mb[curBlock].logicalEnd) {
529 if (curBlock >= numMemoryBlocks)
530 panic("out of memory blocks");
532 if (thisChunk < mb[curBlock].logicalStart)
533 panic("memory block error");
535 absChunk = mb[curBlock].absStart +
536 (thisChunk - mb[curBlock].logicalStart);
537 if (((absChunk < hptFirstChunk) ||
538 (absChunk > hptLastChunk)) &&
539 ((absChunk < loadAreaFirstChunk) ||
540 (absChunk > loadAreaLastChunk))) {
541 mschunks_map.mapping[nextPhysChunk] =
553 * main store size (in chunks) is
554 * totalChunks - hptSizeChunks
555 * which should be equal to
558 systemcfg->physicalMemorySize = chunk_to_addr(nextPhysChunk);
564 static void __init iSeries_setup_arch(void)
566 unsigned procIx = get_paca()->lppaca.dyn_hv_phys_proc_index;
568 if (get_paca()->lppaca.shared_proc) {
569 ppc_md.idle_loop = iseries_shared_idle;
570 printk(KERN_INFO "Using shared processor idle loop\n");
572 ppc_md.idle_loop = iseries_dedicated_idle;
573 printk(KERN_INFO "Using dedicated idle loop\n");
576 /* Setup the Lp Event Queue */
577 setup_hvlpevent_queue();
579 printk("Max logical processors = %d\n",
580 itVpdAreas.xSlicMaxLogicalProcs);
581 printk("Max physical processors = %d\n",
582 itVpdAreas.xSlicMaxPhysicalProcs);
584 systemcfg->processor = xIoHriProcessorVpd[procIx].xPVR;
585 printk("Processor version = %x\n", systemcfg->processor);
588 static void iSeries_show_cpuinfo(struct seq_file *m)
590 seq_printf(m, "machine\t\t: 64-bit iSeries Logical Partition\n");
597 static int iSeries_get_irq(struct pt_regs *regs)
599 /* -2 means ignore this interrupt */
606 static void iSeries_restart(char *cmd)
614 static void iSeries_power_off(void)
622 static void iSeries_halt(void)
627 static void __init iSeries_progress(char * st, unsigned short code)
629 printk("Progress: [%04x] - %s\n", (unsigned)code, st);
630 if (!piranha_simulator && mf_initialized) {
632 mf_display_progress(code);
638 static void __init iSeries_fixup_klimit(void)
641 * Change klimit to take into account any ram disk
642 * that may be included
645 klimit = KERNELBASE + (u64)naca.xRamDisk +
646 (naca.xRamDiskSize * PAGE_SIZE);
649 * No ram disk was included - check and see if there
650 * was an embedded system map. Change klimit to take
651 * into account any embedded system map
653 if (embedded_sysmap_end)
654 klimit = KERNELBASE + ((embedded_sysmap_end + 4095) &
659 static int __init iSeries_src_init(void)
661 /* clear the progress line */
662 ppc_md.progress(" ", 0xffff);
666 late_initcall(iSeries_src_init);
668 static inline void process_iSeries_events(void)
670 asm volatile ("li 0,0x5555; sc" : : : "r0", "r3");
673 static void yield_shared_processor(void)
677 HvCall_setEnabledInterrupts(HvCall_MaskIPI |
683 /* Compute future tb value when yield should expire */
684 HvCall_yieldProcessor(HvCall_YieldTimed, tb+tb_ticks_per_jiffy);
687 * The decrementer stops during the yield. Force a fake decrementer
688 * here and let the timer_interrupt code sort out the actual time.
690 get_paca()->lppaca.int_dword.fields.decr_int = 1;
691 process_iSeries_events();
694 static void iseries_shared_idle(void)
697 while (!need_resched() && !hvlpevent_is_pending()) {
699 ppc64_runlatch_off();
701 /* Recheck with irqs off */
702 if (!need_resched() && !hvlpevent_is_pending())
703 yield_shared_processor();
711 if (hvlpevent_is_pending())
712 process_iSeries_events();
718 static void iseries_dedicated_idle(void)
723 oldval = test_and_clear_thread_flag(TIF_NEED_RESCHED);
726 set_thread_flag(TIF_POLLING_NRFLAG);
728 while (!need_resched()) {
729 ppc64_runlatch_off();
732 if (hvlpevent_is_pending()) {
735 process_iSeries_events();
740 clear_thread_flag(TIF_POLLING_NRFLAG);
751 void __init iSeries_init_IRQ(void) { }
754 static int __init iseries_probe(int platform)
756 return PLATFORM_ISERIES_LPAR == platform;
759 struct machdep_calls __initdata iseries_md = {
760 .setup_arch = iSeries_setup_arch,
761 .show_cpuinfo = iSeries_show_cpuinfo,
762 .init_IRQ = iSeries_init_IRQ,
763 .get_irq = iSeries_get_irq,
764 .init_early = iSeries_init_early,
765 .pcibios_fixup = iSeries_pci_final_fixup,
766 .restart = iSeries_restart,
767 .power_off = iSeries_power_off,
768 .halt = iSeries_halt,
769 .get_boot_time = iSeries_get_boot_time,
770 .set_rtc_time = iSeries_set_rtc_time,
771 .get_rtc_time = iSeries_get_rtc_time,
772 .calibrate_decr = generic_calibrate_decr,
773 .progress = iSeries_progress,
774 .probe = iseries_probe,
775 /* XXX Implement enable_pmcs for iSeries */
779 unsigned char data[PAGE_SIZE];
783 struct iseries_flat_dt {
784 struct boot_param_header header;
790 struct iseries_flat_dt iseries_dt;
792 void dt_init(struct iseries_flat_dt *dt)
794 dt->header.off_mem_rsvmap =
795 offsetof(struct iseries_flat_dt, reserve_map);
796 dt->header.off_dt_struct = offsetof(struct iseries_flat_dt, dt);
797 dt->header.off_dt_strings = offsetof(struct iseries_flat_dt, strings);
798 dt->header.totalsize = sizeof(struct iseries_flat_dt);
799 dt->header.dt_strings_size = sizeof(struct blob);
801 /* There is no notion of hardware cpu id on iSeries */
802 dt->header.boot_cpuid_phys = smp_processor_id();
804 dt->dt.next = (unsigned long)&dt->dt.data;
805 dt->strings.next = (unsigned long)&dt->strings.data;
807 dt->header.magic = OF_DT_HEADER;
808 dt->header.version = 0x10;
809 dt->header.last_comp_version = 0x10;
811 dt->reserve_map[0] = 0;
812 dt->reserve_map[1] = 0;
815 void dt_check_blob(struct blob *b)
817 if (b->next >= (unsigned long)&b->next) {
818 DBG("Ran out of space in flat device tree blob!\n");
823 void dt_push_u32(struct iseries_flat_dt *dt, u32 value)
825 *((u32*)dt->dt.next) = value;
826 dt->dt.next += sizeof(u32);
828 dt_check_blob(&dt->dt);
831 void dt_push_u64(struct iseries_flat_dt *dt, u64 value)
833 *((u64*)dt->dt.next) = value;
834 dt->dt.next += sizeof(u64);
836 dt_check_blob(&dt->dt);
839 unsigned long dt_push_bytes(struct blob *blob, char *data, int len)
841 unsigned long start = blob->next - (unsigned long)blob->data;
843 memcpy((char *)blob->next, data, len);
844 blob->next = _ALIGN(blob->next + len, 4);
851 void dt_start_node(struct iseries_flat_dt *dt, char *name)
853 dt_push_u32(dt, OF_DT_BEGIN_NODE);
854 dt_push_bytes(&dt->dt, name, strlen(name) + 1);
857 #define dt_end_node(dt) dt_push_u32(dt, OF_DT_END_NODE)
859 void dt_prop(struct iseries_flat_dt *dt, char *name, char *data, int len)
861 unsigned long offset;
863 dt_push_u32(dt, OF_DT_PROP);
865 /* Length of the data */
866 dt_push_u32(dt, len);
868 /* Put the property name in the string blob. */
869 offset = dt_push_bytes(&dt->strings, name, strlen(name) + 1);
871 /* The offset of the properties name in the string blob. */
872 dt_push_u32(dt, (u32)offset);
874 /* The actual data. */
875 dt_push_bytes(&dt->dt, data, len);
878 void dt_prop_str(struct iseries_flat_dt *dt, char *name, char *data)
880 dt_prop(dt, name, data, strlen(data) + 1); /* + 1 for NULL */
883 void dt_prop_u32(struct iseries_flat_dt *dt, char *name, u32 data)
885 dt_prop(dt, name, (char *)&data, sizeof(u32));
888 void dt_prop_u64(struct iseries_flat_dt *dt, char *name, u64 data)
890 dt_prop(dt, name, (char *)&data, sizeof(u64));
893 void dt_prop_u64_list(struct iseries_flat_dt *dt, char *name, u64 *data, int n)
895 dt_prop(dt, name, (char *)data, sizeof(u64) * n);
898 void dt_prop_empty(struct iseries_flat_dt *dt, char *name)
900 dt_prop(dt, name, NULL, 0);
903 void dt_cpus(struct iseries_flat_dt *dt)
905 unsigned char buf[32];
907 unsigned int i, index;
908 struct IoHriProcessorVpd *d;
911 snprintf(buf, 32, "PowerPC,%s", cur_cpu_spec->cpu_name);
912 p = strchr(buf, ' ');
913 if (!p) p = buf + strlen(buf);
915 dt_start_node(dt, "cpus");
916 dt_prop_u32(dt, "#address-cells", 1);
917 dt_prop_u32(dt, "#size-cells", 0);
919 for (i = 0; i < NR_CPUS; i++) {
920 if (paca[i].lppaca.dyn_proc_status >= 2)
923 snprintf(p, 32 - (p - buf), "@%d", i);
924 dt_start_node(dt, buf);
926 dt_prop_str(dt, "device_type", "cpu");
928 index = paca[i].lppaca.dyn_hv_phys_proc_index;
929 d = &xIoHriProcessorVpd[index];
931 dt_prop_u32(dt, "i-cache-size", d->xInstCacheSize * 1024);
932 dt_prop_u32(dt, "i-cache-line-size", d->xInstCacheOperandSize);
934 dt_prop_u32(dt, "d-cache-size", d->xDataL1CacheSizeKB * 1024);
935 dt_prop_u32(dt, "d-cache-line-size", d->xDataCacheOperandSize);
937 /* magic conversions to Hz copied from old code */
938 dt_prop_u32(dt, "clock-frequency",
939 ((1UL << 34) * 1000000) / d->xProcFreq);
940 dt_prop_u32(dt, "timebase-frequency",
941 ((1UL << 32) * 1000000) / d->xTimeBaseFreq);
943 dt_prop_u32(dt, "reg", i);
951 void build_flat_dt(struct iseries_flat_dt *dt)
957 dt_start_node(dt, "");
959 dt_prop_u32(dt, "#address-cells", 2);
960 dt_prop_u32(dt, "#size-cells", 2);
963 dt_start_node(dt, "memory@0");
964 dt_prop_str(dt, "name", "memory");
965 dt_prop_str(dt, "device_type", "memory");
967 tmp[1] = systemcfg->physicalMemorySize;
968 dt_prop_u64_list(dt, "reg", tmp, 2);
972 dt_start_node(dt, "chosen");
973 dt_prop_u32(dt, "linux,platform", PLATFORM_ISERIES_LPAR);
980 dt_push_u32(dt, OF_DT_END);
983 void * __init iSeries_early_setup(void)
985 iSeries_fixup_klimit();
988 * Initialize the table which translate Linux physical addresses to
989 * AS/400 absolute addresses
991 build_iSeries_Memory_Map();
993 build_flat_dt(&iseries_dt);
995 return (void *) __pa(&iseries_dt);