2 * Low-level SPU handling
4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
6 * Author: Arnd Bergmann <arndb@de.ibm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/interrupt.h>
26 #include <linux/list.h>
27 #include <linux/module.h>
28 #include <linux/poll.h>
29 #include <linux/ptrace.h>
30 #include <linux/slab.h>
31 #include <linux/wait.h>
35 #include <asm/semaphore.h>
37 #include <asm/mmu_context.h>
39 #include "interrupt.h"
41 static int __spu_trap_invalid_dma(struct spu *spu)
43 pr_debug("%s\n", __FUNCTION__);
44 force_sig(SIGBUS, /* info, */ current);
48 static int __spu_trap_dma_align(struct spu *spu)
50 pr_debug("%s\n", __FUNCTION__);
51 force_sig(SIGBUS, /* info, */ current);
55 static int __spu_trap_error(struct spu *spu)
57 pr_debug("%s\n", __FUNCTION__);
58 force_sig(SIGILL, /* info, */ current);
62 static void spu_restart_dma(struct spu *spu)
64 struct spu_priv2 __iomem *priv2 = spu->priv2;
66 if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags))
67 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
70 static int __spu_trap_data_seg(struct spu *spu, unsigned long ea)
72 struct spu_priv2 __iomem *priv2 = spu->priv2;
73 struct mm_struct *mm = spu->mm;
76 pr_debug("%s\n", __FUNCTION__);
78 if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags)) {
79 /* SLBs are pre-loaded for context switch, so
80 * we should never get here!
82 printk("%s: invalid access during switch!\n", __func__);
85 if (!mm || (REGION_ID(ea) != USER_REGION_ID)) {
86 /* Future: support kernel segments so that drivers
89 pr_debug("invalid region access at %016lx\n", ea);
93 esid = (ea & ESID_MASK) | SLB_ESID_V;
94 vsid = (get_vsid(mm->context.id, ea) << SLB_VSID_SHIFT) | SLB_VSID_USER;
95 if (in_hugepage_area(mm->context, ea))
98 out_be64(&priv2->slb_index_W, spu->slb_replace);
99 out_be64(&priv2->slb_vsid_RW, vsid);
100 out_be64(&priv2->slb_esid_RW, esid);
103 if (spu->slb_replace >= 8)
104 spu->slb_replace = 0;
106 spu_restart_dma(spu);
111 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); //XXX
112 static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr)
114 pr_debug("%s\n", __FUNCTION__);
116 /* Handle kernel space hash faults immediately.
117 User hash faults need to be deferred to process context. */
118 if ((dsisr & MFC_DSISR_PTE_NOT_FOUND)
119 && REGION_ID(ea) != USER_REGION_ID
120 && hash_page(ea, _PAGE_PRESENT, 0x300) == 0) {
121 spu_restart_dma(spu);
125 if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags)) {
126 printk("%s: invalid access during switch!\n", __func__);
133 if (spu->stop_callback)
134 spu->stop_callback(spu);
138 static int __spu_trap_mailbox(struct spu *spu)
140 if (spu->ibox_callback)
141 spu->ibox_callback(spu);
143 /* atomically disable SPU mailbox interrupts */
144 spin_lock(&spu->register_lock);
145 out_be64(&spu->priv1->int_mask_class2_RW,
146 in_be64(&spu->priv1->int_mask_class2_RW) & ~0x1);
147 spin_unlock(&spu->register_lock);
151 static int __spu_trap_stop(struct spu *spu)
153 pr_debug("%s\n", __FUNCTION__);
154 spu->stop_code = in_be32(&spu->problem->spu_status_R);
155 if (spu->stop_callback)
156 spu->stop_callback(spu);
160 static int __spu_trap_halt(struct spu *spu)
162 pr_debug("%s\n", __FUNCTION__);
163 spu->stop_code = in_be32(&spu->problem->spu_status_R);
164 if (spu->stop_callback)
165 spu->stop_callback(spu);
169 static int __spu_trap_tag_group(struct spu *spu)
171 pr_debug("%s\n", __FUNCTION__);
172 /* wake_up(&spu->dma_wq); */
176 static int __spu_trap_spubox(struct spu *spu)
178 if (spu->wbox_callback)
179 spu->wbox_callback(spu);
181 /* atomically disable SPU mailbox interrupts */
182 spin_lock(&spu->register_lock);
183 out_be64(&spu->priv1->int_mask_class2_RW,
184 in_be64(&spu->priv1->int_mask_class2_RW) & ~0x10);
185 spin_unlock(&spu->register_lock);
190 spu_irq_class_0(int irq, void *data, struct pt_regs *regs)
195 spu->class_0_pending = 1;
196 if (spu->stop_callback)
197 spu->stop_callback(spu);
203 spu_irq_class_0_bottom(struct spu *spu)
205 unsigned long stat, mask;
207 spu->class_0_pending = 0;
209 mask = in_be64(&spu->priv1->int_mask_class0_RW);
210 stat = in_be64(&spu->priv1->int_stat_class0_RW);
214 if (stat & 1) /* invalid MFC DMA */
215 __spu_trap_invalid_dma(spu);
217 if (stat & 2) /* invalid DMA alignment */
218 __spu_trap_dma_align(spu);
220 if (stat & 4) /* error on SPU */
221 __spu_trap_error(spu);
223 out_be64(&spu->priv1->int_stat_class0_RW, stat);
225 return (stat & 0x7) ? -EIO : 0;
227 EXPORT_SYMBOL_GPL(spu_irq_class_0_bottom);
230 spu_irq_class_1(int irq, void *data, struct pt_regs *regs)
233 unsigned long stat, mask, dar, dsisr;
237 /* atomically read & clear class1 status. */
238 spin_lock(&spu->register_lock);
239 mask = in_be64(&spu->priv1->int_mask_class1_RW);
240 stat = in_be64(&spu->priv1->int_stat_class1_RW) & mask;
241 dar = in_be64(&spu->priv1->mfc_dar_RW);
242 dsisr = in_be64(&spu->priv1->mfc_dsisr_RW);
243 if (stat & 2) /* mapping fault */
244 out_be64(&spu->priv1->mfc_dsisr_RW, 0UL);
245 out_be64(&spu->priv1->int_stat_class1_RW, stat);
246 spin_unlock(&spu->register_lock);
248 if (stat & 1) /* segment fault */
249 __spu_trap_data_seg(spu, dar);
251 if (stat & 2) { /* mapping fault */
252 __spu_trap_data_map(spu, dar, dsisr);
255 if (stat & 4) /* ls compare & suspend on get */
258 if (stat & 8) /* ls compare & suspend on put */
261 return stat ? IRQ_HANDLED : IRQ_NONE;
263 EXPORT_SYMBOL_GPL(spu_irq_class_1_bottom);
266 spu_irq_class_2(int irq, void *data, struct pt_regs *regs)
273 stat = in_be64(&spu->priv1->int_stat_class2_RW);
274 mask = in_be64(&spu->priv1->int_mask_class2_RW);
276 pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask);
280 if (stat & 1) /* PPC core mailbox */
281 __spu_trap_mailbox(spu);
283 if (stat & 2) /* SPU stop-and-signal */
284 __spu_trap_stop(spu);
286 if (stat & 4) /* SPU halted */
287 __spu_trap_halt(spu);
289 if (stat & 8) /* DMA tag group complete */
290 __spu_trap_tag_group(spu);
292 if (stat & 0x10) /* SPU mailbox threshold */
293 __spu_trap_spubox(spu);
295 out_be64(&spu->priv1->int_stat_class2_RW, stat);
296 return stat ? IRQ_HANDLED : IRQ_NONE;
300 spu_request_irqs(struct spu *spu)
305 irq_base = IIC_NODE_STRIDE * spu->node + IIC_SPE_OFFSET;
307 snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0", spu->number);
308 ret = request_irq(irq_base + spu->isrc,
309 spu_irq_class_0, 0, spu->irq_c0, spu);
312 out_be64(&spu->priv1->int_mask_class0_RW, 0x7);
314 snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1", spu->number);
315 ret = request_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc,
316 spu_irq_class_1, 0, spu->irq_c1, spu);
319 out_be64(&spu->priv1->int_mask_class1_RW, 0x3);
321 snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2", spu->number);
322 ret = request_irq(irq_base + 2*IIC_CLASS_STRIDE + spu->isrc,
323 spu_irq_class_2, 0, spu->irq_c2, spu);
326 out_be64(&spu->priv1->int_mask_class2_RW, 0xe);
330 free_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc, spu);
332 free_irq(irq_base + spu->isrc, spu);
338 spu_free_irqs(struct spu *spu)
342 irq_base = IIC_NODE_STRIDE * spu->node + IIC_SPE_OFFSET;
344 free_irq(irq_base + spu->isrc, spu);
345 free_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc, spu);
346 free_irq(irq_base + 2*IIC_CLASS_STRIDE + spu->isrc, spu);
349 static LIST_HEAD(spu_list);
350 static DECLARE_MUTEX(spu_mutex);
352 static void spu_init_channels(struct spu *spu)
354 static const struct {
358 { 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, },
359 { 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, },
361 { 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, },
362 { 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, },
363 { 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, },
365 struct spu_priv2 *priv2;
370 /* initialize all channel data to zero */
371 for (i = 0; i < ARRAY_SIZE(zero_list); i++) {
374 out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel);
375 for (count = 0; count < zero_list[i].count; count++)
376 out_be64(&priv2->spu_chnldata_RW, 0);
379 /* initialize channel counts to meaningful values */
380 for (i = 0; i < ARRAY_SIZE(count_list); i++) {
381 out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel);
382 out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count);
386 static void spu_init_regs(struct spu *spu)
388 out_be64(&spu->priv1->int_mask_class0_RW, 0x7);
389 out_be64(&spu->priv1->int_mask_class1_RW, 0x3);
390 out_be64(&spu->priv1->int_mask_class2_RW, 0xe);
393 struct spu *spu_alloc(void)
398 if (!list_empty(&spu_list)) {
399 spu = list_entry(spu_list.next, struct spu, list);
400 list_del_init(&spu->list);
401 pr_debug("Got SPU %x %d\n", spu->isrc, spu->number);
403 pr_debug("No SPU left\n");
409 spu_init_channels(spu);
415 EXPORT_SYMBOL_GPL(spu_alloc);
417 void spu_free(struct spu *spu)
420 list_add_tail(&spu->list, &spu_list);
423 EXPORT_SYMBOL_GPL(spu_free);
425 static int spu_handle_mm_fault(struct spu *spu)
427 struct mm_struct *mm = spu->mm;
428 struct vm_area_struct *vma;
429 u64 ea, dsisr, is_write;
435 if (!IS_VALID_EA(ea)) {
442 if (mm->pgd == NULL) {
446 down_read(&mm->mmap_sem);
447 vma = find_vma(mm, ea);
450 if (vma->vm_start <= ea)
452 if (!(vma->vm_flags & VM_GROWSDOWN))
455 if (expand_stack(vma, ea))
459 is_write = dsisr & MFC_DSISR_ACCESS_PUT;
461 if (!(vma->vm_flags & VM_WRITE))
464 if (dsisr & MFC_DSISR_ACCESS_DENIED)
466 if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
470 switch (handle_mm_fault(mm, vma, ea, is_write)) {
477 case VM_FAULT_SIGBUS:
486 up_read(&mm->mmap_sem);
490 up_read(&mm->mmap_sem);
494 int spu_irq_class_1_bottom(struct spu *spu)
496 u64 ea, dsisr, access, error = 0UL;
501 if (dsisr & MFC_DSISR_PTE_NOT_FOUND) {
502 access = (_PAGE_PRESENT | _PAGE_USER);
503 access |= (dsisr & MFC_DSISR_ACCESS_PUT) ? _PAGE_RW : 0UL;
504 if (hash_page(ea, access, 0x300) != 0)
505 error |= CLASS1_ENABLE_STORAGE_FAULT_INTR;
507 if ((error & CLASS1_ENABLE_STORAGE_FAULT_INTR) ||
508 (dsisr & MFC_DSISR_ACCESS_DENIED)) {
509 if ((ret = spu_handle_mm_fault(spu)) != 0)
510 error |= CLASS1_ENABLE_STORAGE_FAULT_INTR;
512 error &= ~CLASS1_ENABLE_STORAGE_FAULT_INTR;
517 spu_restart_dma(spu);
519 __spu_trap_invalid_dma(spu);
524 static void __iomem * __init map_spe_prop(struct device_node *n,
527 struct address_prop {
528 unsigned long address;
530 } __attribute__((packed)) *prop;
535 p = get_property(n, name, &proplen);
536 if (proplen != sizeof (struct address_prop))
541 return ioremap(prop->address, prop->len);
544 static void spu_unmap(struct spu *spu)
548 iounmap(spu->problem);
549 iounmap((u8 __iomem *)spu->local_store);
552 static int __init spu_map_device(struct spu *spu, struct device_node *spe)
558 prop = get_property(spe, "isrc", NULL);
561 spu->isrc = *(unsigned int *)prop;
563 spu->name = get_property(spe, "name", NULL);
567 prop = get_property(spe, "local-store", NULL);
570 spu->local_store_phys = *(unsigned long *)prop;
572 /* we use local store as ram, not io memory */
573 spu->local_store = (void __force *)map_spe_prop(spe, "local-store");
574 if (!spu->local_store)
577 spu->problem= map_spe_prop(spe, "problem");
581 spu->priv1= map_spe_prop(spe, "priv1");
585 spu->priv2= map_spe_prop(spe, "priv2");
597 static int __init find_spu_node_id(struct device_node *spe)
600 struct device_node *cpu;
602 cpu = spe->parent->parent;
603 id = (unsigned int *)get_property(cpu, "node-id", NULL);
608 static int __init create_spu(struct device_node *spe)
615 spu = kmalloc(sizeof (*spu), GFP_KERNEL);
619 ret = spu_map_device(spu, spe);
623 spu->node = find_spu_node_id(spe);
625 spu->slb_replace = 0;
630 spu->class_0_pending = 0;
634 spin_lock_init(&spu->register_lock);
636 out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1));
637 out_be64(&spu->priv1->mfc_sr1_RW, 0x33);
639 spu->ibox_callback = NULL;
640 spu->wbox_callback = NULL;
641 spu->stop_callback = NULL;
644 spu->number = number++;
645 ret = spu_request_irqs(spu);
649 list_add(&spu->list, &spu_list);
652 pr_debug(KERN_DEBUG "Using SPE %s %02x %p %p %p %p %d\n",
653 spu->name, spu->isrc, spu->local_store,
654 spu->problem, spu->priv1, spu->priv2, spu->number);
666 static void destroy_spu(struct spu *spu)
668 list_del_init(&spu->list);
675 static void cleanup_spu_base(void)
677 struct spu *spu, *tmp;
679 list_for_each_entry_safe(spu, tmp, &spu_list, list)
683 module_exit(cleanup_spu_base);
685 static int __init init_spu_base(void)
687 struct device_node *node;
691 for (node = of_find_node_by_type(NULL, "spe");
692 node; node = of_find_node_by_type(node, "spe")) {
693 ret = create_spu(node);
695 printk(KERN_WARNING "%s: Error initializing %s\n",
696 __FUNCTION__, node->name);
701 /* in some old firmware versions, the spe is called 'spc', so we
702 look for that as well */
703 for (node = of_find_node_by_type(NULL, "spc");
704 node; node = of_find_node_by_type(node, "spc")) {
705 ret = create_spu(node);
707 printk(KERN_WARNING "%s: Error initializing %s\n",
708 __FUNCTION__, node->name);
715 module_init(init_spu_base);
717 MODULE_LICENSE("GPL");
718 MODULE_AUTHOR("Arnd Bergmann <arndb@de.ibm.com>");