2 * MPC85xx setup and early boot code plus other random bits.
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
6 * Copyright 2005 Freescale Semiconductor Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/stddef.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/reboot.h>
19 #include <linux/pci.h>
20 #include <linux/kdev_t.h>
21 #include <linux/major.h>
22 #include <linux/console.h>
23 #include <linux/delay.h>
24 #include <linux/seq_file.h>
25 #include <linux/initrd.h>
26 #include <linux/module.h>
27 #include <linux/interrupt.h>
28 #include <linux/fsl_devices.h>
30 #include <asm/system.h>
31 #include <asm/pgtable.h>
33 #include <asm/atomic.h>
36 #include <asm/machdep.h>
38 #include <asm/bootinfo.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/mpc85xx.h>
42 #include <mm/mmu_decl.h>
46 #include <asm/i8259.h>
48 #include <sysdev/fsl_soc.h>
49 #include <sysdev/fsl_pci.h>
52 static int cds_pci_slot = 2;
53 static volatile u8 *cadmus;
57 #define ARCADIA_HOST_BRIDGE_IDSEL 17
58 #define ARCADIA_2ND_BRIDGE_IDSEL 3
60 static int mpc85xx_exclude_device(struct pci_controller *hose,
61 u_char bus, u_char devfn)
63 /* We explicitly do not go past the Tundra 320 Bridge */
64 if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
65 return PCIBIOS_DEVICE_NOT_FOUND;
66 if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
67 return PCIBIOS_DEVICE_NOT_FOUND;
69 return PCIBIOS_SUCCESSFUL;
72 static void mpc85xx_cds_restart(char *cmd)
77 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
80 /* Use the VIA Super Southbridge to force a PCI reset */
81 pci_read_config_byte(dev, 0x47, &tmp);
82 pci_write_config_byte(dev, 0x47, tmp | 1);
84 /* Flush the outbound PCI write queues */
85 pci_read_config_byte(dev, 0x47, &tmp);
88 * At this point, the harware reset should have triggered.
89 * However, if it doesn't work for some mysterious reason,
90 * just fall through to the default reset below.
97 * If we can't find the VIA chip (maybe the P2P bridge is disabled)
98 * or the VIA chip reset didn't work, just use the default reset.
100 mpc85xx_restart(NULL);
103 static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
106 if (dev->vendor == PCI_VENDOR_ID_VIA) {
107 switch (dev->device) {
108 case PCI_DEVICE_ID_VIA_82C586_1:
110 * U-Boot does not set the enable bits
111 * for the IDE device. Force them on here.
113 pci_read_config_byte(dev, 0x40, &c);
114 c |= 0x03; /* IDE: Chip Enable Bits */
115 pci_write_config_byte(dev, 0x40, c);
118 * Since only primary interface works, force the
119 * IDE function to standard primary IDE interrupt
123 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
126 * Force legacy USB interrupt routing
128 case PCI_DEVICE_ID_VIA_82C586_2:
129 /* There are two USB controllers.
130 * Identify them by functon number
132 if (PCI_FUNC(dev->devfn) == 3)
136 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
143 static void __devinit skip_fake_bridge(struct pci_dev *dev)
145 /* Make it an error to skip the fake bridge
146 * in pci_setup_device() in probe.c */
147 dev->hdr_type = 0x7f;
149 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
150 DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
151 DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
153 #ifdef CONFIG_PPC_I8259
154 static void mpc85xx_8259_cascade_handler(unsigned int irq,
155 struct irq_desc *desc)
157 unsigned int cascade_irq = i8259_irq();
159 if (cascade_irq != NO_IRQ)
160 /* handle an interrupt from the 8259 */
161 generic_handle_irq(cascade_irq);
163 /* check for any interrupts from the shared IRQ line */
164 handle_fasteoi_irq(irq, desc);
167 static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
172 static struct irqaction mpc85xxcds_8259_irqaction = {
173 .handler = mpc85xx_8259_cascade_action,
174 .flags = IRQF_SHARED,
175 .mask = CPU_MASK_NONE,
176 .name = "8259 cascade",
178 #endif /* PPC_I8259 */
179 #endif /* CONFIG_PCI */
181 static void __init mpc85xx_cds_pic_init(void)
185 struct device_node *np = NULL;
187 np = of_find_node_by_type(np, "open-pic");
190 printk(KERN_ERR "Could not find open-pic node\n");
194 if (of_address_to_resource(np, 0, &r)) {
195 printk(KERN_ERR "Failed to map mpic register space\n");
200 mpic = mpic_alloc(np, r.start,
201 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
202 0, 256, " OpenPIC ");
203 BUG_ON(mpic == NULL);
205 /* Return the mpic node */
211 #if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
212 static int mpc85xx_cds_8259_attach(void)
215 struct device_node *np = NULL;
216 struct device_node *cascade_node = NULL;
219 if (!machine_is(mpc85xx_cds))
222 /* Initialize the i8259 controller */
223 for_each_node_by_type(np, "interrupt-controller")
224 if (of_device_is_compatible(np, "chrp,iic")) {
229 if (cascade_node == NULL) {
230 printk(KERN_DEBUG "Could not find i8259 PIC\n");
234 cascade_irq = irq_of_parse_and_map(cascade_node, 0);
235 if (cascade_irq == NO_IRQ) {
236 printk(KERN_ERR "Failed to map cascade interrupt\n");
240 i8259_init(cascade_node, 0);
241 of_node_put(cascade_node);
244 * Hook the interrupt to make sure desc->action is never NULL.
245 * This is required to ensure that the interrupt does not get
246 * disabled when the last user of the shared IRQ line frees their
249 if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) {
250 printk(KERN_ERR "Failed to setup cascade interrupt\n");
254 /* Success. Connect our low-level cascade handler. */
255 set_irq_handler(cascade_irq, mpc85xx_8259_cascade_handler);
260 device_initcall(mpc85xx_cds_8259_attach);
262 #endif /* CONFIG_PPC_I8259 */
265 * Setup the architecture
267 static void __init mpc85xx_cds_setup_arch(void)
269 struct device_node *cpu;
271 struct device_node *np;
275 ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
277 cpu = of_find_node_by_type(NULL, "cpu");
279 const unsigned int *fp;
281 fp = of_get_property(cpu, "clock-frequency", NULL);
283 loops_per_jiffy = *fp / HZ;
285 loops_per_jiffy = 500000000 / HZ;
289 cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
290 cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
292 if (ppc_md.progress) {
294 snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
295 cadmus[CM_VER], cds_pci_slot);
296 ppc_md.progress(buf, 0);
300 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
301 struct resource rsrc;
302 of_address_to_resource(np, 0, &rsrc);
303 if ((rsrc.start & 0xfffff) == 0x8000)
304 fsl_add_bridge(np, 1);
306 fsl_add_bridge(np, 0);
308 ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
309 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
313 static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
315 uint pvid, svid, phid1;
316 uint memsize = total_memory;
318 pvid = mfspr(SPRN_PVR);
319 svid = mfspr(SPRN_SVR);
321 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
322 seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
323 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
324 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
326 /* Display cpu Pll setting */
327 phid1 = mfspr(SPRN_HID1);
328 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
330 /* Display the amount of memory */
331 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
336 * Called very early, device-tree isn't unflattened
338 static int __init mpc85xx_cds_probe(void)
340 unsigned long root = of_get_flat_dt_root();
342 return of_flat_dt_is_compatible(root, "MPC85xxCDS");
345 define_machine(mpc85xx_cds) {
346 .name = "MPC85xx CDS",
347 .probe = mpc85xx_cds_probe,
348 .setup_arch = mpc85xx_cds_setup_arch,
349 .init_IRQ = mpc85xx_cds_pic_init,
350 .show_cpuinfo = mpc85xx_cds_show_cpuinfo,
351 .get_irq = mpic_get_irq,
353 .restart = mpc85xx_cds_restart,
355 .restart = mpc85xx_restart,
357 .calibrate_decr = generic_calibrate_decr,
358 .progress = udbg_progress,
359 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,