2 * MPC85xx setup and early boot code plus other random bits.
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
6 * Copyright 2005 Freescale Semiconductor Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/stddef.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/reboot.h>
19 #include <linux/pci.h>
20 #include <linux/kdev_t.h>
21 #include <linux/major.h>
22 #include <linux/console.h>
23 #include <linux/delay.h>
24 #include <linux/seq_file.h>
25 #include <linux/initrd.h>
26 #include <linux/module.h>
27 #include <linux/fsl_devices.h>
29 #include <asm/system.h>
30 #include <asm/pgtable.h>
32 #include <asm/atomic.h>
35 #include <asm/machdep.h>
37 #include <asm/bootinfo.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/mpc85xx.h>
41 #include <mm/mmu_decl.h>
45 #include <asm/i8259.h>
47 #include <sysdev/fsl_soc.h>
50 static int cds_pci_slot = 2;
51 static volatile u8 *cadmus;
55 #define ARCADIA_HOST_BRIDGE_IDSEL 17
56 #define ARCADIA_2ND_BRIDGE_IDSEL 3
58 static int mpc85xx_exclude_device(struct pci_controller *hose,
59 u_char bus, u_char devfn)
61 if ((bus == hose->first_busno) && PCI_SLOT(devfn) == 0)
62 return PCIBIOS_DEVICE_NOT_FOUND;
63 /* We explicitly do not go past the Tundra 320 Bridge */
64 if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
65 return PCIBIOS_DEVICE_NOT_FOUND;
66 if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
67 return PCIBIOS_DEVICE_NOT_FOUND;
69 return PCIBIOS_SUCCESSFUL;
72 static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
75 if (dev->vendor == PCI_VENDOR_ID_VIA) {
76 switch (dev->device) {
77 case PCI_DEVICE_ID_VIA_82C586_1:
79 * U-Boot does not set the enable bits
80 * for the IDE device. Force them on here.
82 pci_read_config_byte(dev, 0x40, &c);
83 c |= 0x03; /* IDE: Chip Enable Bits */
84 pci_write_config_byte(dev, 0x40, c);
87 * Since only primary interface works, force the
88 * IDE function to standard primary IDE interrupt
92 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
95 * Force legacy USB interrupt routing
97 case PCI_DEVICE_ID_VIA_82C586_2:
98 /* There are two USB controllers.
99 * Identify them by functon number
101 if (PCI_FUNC(dev->devfn))
105 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
112 #ifdef CONFIG_PPC_I8259
113 #warning The i8259 PIC support is currently broken
114 static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
116 unsigned int cascade_irq = i8259_irq();
118 if (cascade_irq != NO_IRQ)
119 generic_handle_irq(cascade_irq);
121 desc->chip->eoi(irq);
123 #endif /* PPC_I8259 */
124 #endif /* CONFIG_PCI */
126 static void __init mpc85xx_cds_pic_init(void)
130 struct device_node *np = NULL;
131 #ifdef CONFIG_PPC_I8259
132 struct device_node *cascade_node = NULL;
136 np = of_find_node_by_type(np, "open-pic");
139 printk(KERN_ERR "Could not find open-pic node\n");
143 if (of_address_to_resource(np, 0, &r)) {
144 printk(KERN_ERR "Failed to map mpic register space\n");
149 mpic = mpic_alloc(np, r.start,
150 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
151 0, 256, " OpenPIC ");
152 BUG_ON(mpic == NULL);
154 /* Return the mpic node */
159 #ifdef CONFIG_PPC_I8259
160 /* Initialize the i8259 controller */
161 for_each_node_by_type(np, "interrupt-controller")
162 if (of_device_is_compatible(np, "chrp,iic")) {
167 if (cascade_node == NULL) {
168 printk(KERN_DEBUG "Could not find i8259 PIC\n");
172 cascade_irq = irq_of_parse_and_map(cascade_node, 0);
173 if (cascade_irq == NO_IRQ) {
174 printk(KERN_ERR "Failed to map cascade interrupt\n");
178 i8259_init(cascade_node, 0);
179 of_node_put(cascade_node);
181 set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade);
182 #endif /* CONFIG_PPC_I8259 */
186 * Setup the architecture
188 static void __init mpc85xx_cds_setup_arch(void)
190 struct device_node *cpu;
192 struct device_node *np;
196 ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
198 cpu = of_find_node_by_type(NULL, "cpu");
200 const unsigned int *fp;
202 fp = of_get_property(cpu, "clock-frequency", NULL);
204 loops_per_jiffy = *fp / HZ;
206 loops_per_jiffy = 500000000 / HZ;
210 cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
211 cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
213 if (ppc_md.progress) {
215 snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
216 cadmus[CM_VER], cds_pci_slot);
217 ppc_md.progress(buf, 0);
221 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
222 mpc85xx_add_bridge(np);
224 ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
225 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
229 static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
231 uint pvid, svid, phid1;
232 uint memsize = total_memory;
234 pvid = mfspr(SPRN_PVR);
235 svid = mfspr(SPRN_SVR);
237 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
238 seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
239 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
240 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
242 /* Display cpu Pll setting */
243 phid1 = mfspr(SPRN_HID1);
244 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
246 /* Display the amount of memory */
247 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
252 * Called very early, device-tree isn't unflattened
254 static int __init mpc85xx_cds_probe(void)
256 unsigned long root = of_get_flat_dt_root();
258 return of_flat_dt_is_compatible(root, "MPC85xxCDS");
261 define_machine(mpc85xx_cds) {
262 .name = "MPC85xx CDS",
263 .probe = mpc85xx_cds_probe,
264 .setup_arch = mpc85xx_cds_setup_arch,
265 .init_IRQ = mpc85xx_cds_pic_init,
266 .show_cpuinfo = mpc85xx_cds_show_cpuinfo,
267 .get_irq = mpic_get_irq,
268 .restart = mpc85xx_restart,
269 .calibrate_decr = generic_calibrate_decr,
270 .progress = udbg_progress,