2 * MPC85xx setup and early boot code plus other random bits.
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
6 * Copyright 2005 Freescale Semiconductor Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/config.h>
15 #include <linux/stddef.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/errno.h>
19 #include <linux/reboot.h>
20 #include <linux/pci.h>
21 #include <linux/kdev_t.h>
22 #include <linux/major.h>
23 #include <linux/console.h>
24 #include <linux/delay.h>
25 #include <linux/irq.h>
26 #include <linux/seq_file.h>
27 #include <linux/root_dev.h>
28 #include <linux/serial.h>
29 #include <linux/tty.h> /* for linux/serial_core.h */
30 #include <linux/serial_core.h>
31 #include <linux/initrd.h>
32 #include <linux/module.h>
33 #include <linux/fsl_devices.h>
34 #include <linux/serial_core.h>
35 #include <linux/serial_8250.h>
37 #include <asm/system.h>
38 #include <asm/pgtable.h>
40 #include <asm/atomic.h>
43 #include <asm/machdep.h>
44 #include <asm/bootinfo.h>
45 #include <asm/pci-bridge.h>
46 #include <asm/mpc85xx.h>
48 #include <asm/immap_85xx.h>
51 #include <mm/mmu_decl.h>
54 #include <sysdev/fsl_soc.h>
58 unsigned long isa_io_base = 0;
59 unsigned long isa_mem_base = 0;
64 * Internal interrupts are all Level Sensitive, and Positive Polarity
66 * Note: Likely, this table and the following function should be
67 * obtained and derived from the OF Device Tree.
69 static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
70 MPC85XX_INTERNAL_IRQ_SENSES,
71 0x0, /* External 0: */
72 #if defined(CONFIG_PCI)
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 1: PCI slot 0 */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 2: PCI slot 1 */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 3: PCI slot 2 */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 4: PCI slot 3 */
78 0x0, /* External 1: */
79 0x0, /* External 2: */
80 0x0, /* External 3: */
81 0x0, /* External 4: */
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
84 0x0, /* External 6: */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 7: PHY */
86 0x0, /* External 8: */
87 0x0, /* External 9: */
88 0x0, /* External 10: */
89 0x0, /* External 11: */
93 void __init mpc85xx_ads_pic_init(void)
96 phys_addr_t OpenPIC_PAddr;
98 /* Determine the Physical Address of the OpenPIC regs */
99 OpenPIC_PAddr = get_immrbase() + MPC85xx_OPENPIC_OFFSET;
101 mpic1 = mpic_alloc(OpenPIC_PAddr,
102 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
103 4, MPC85xx_OPENPIC_IRQ_OFFSET, 0, 250,
104 mpc85xx_ads_openpic_initsenses,
105 sizeof(mpc85xx_ads_openpic_initsenses), " OpenPIC ");
106 BUG_ON(mpic1 == NULL);
107 mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200);
108 mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10280);
109 mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10300);
110 mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10380);
111 mpic_assign_isu(mpic1, 4, OpenPIC_PAddr + 0x10400);
112 mpic_assign_isu(mpic1, 5, OpenPIC_PAddr + 0x10480);
113 mpic_assign_isu(mpic1, 6, OpenPIC_PAddr + 0x10500);
114 mpic_assign_isu(mpic1, 7, OpenPIC_PAddr + 0x10580);
116 /* dummy mappings to get to 48 */
117 mpic_assign_isu(mpic1, 8, OpenPIC_PAddr + 0x10600);
118 mpic_assign_isu(mpic1, 9, OpenPIC_PAddr + 0x10680);
119 mpic_assign_isu(mpic1, 10, OpenPIC_PAddr + 0x10700);
120 mpic_assign_isu(mpic1, 11, OpenPIC_PAddr + 0x10780);
123 mpic_assign_isu(mpic1, 12, OpenPIC_PAddr + 0x10000);
124 mpic_assign_isu(mpic1, 13, OpenPIC_PAddr + 0x10080);
125 mpic_assign_isu(mpic1, 14, OpenPIC_PAddr + 0x10100);
131 * Setup the architecture
134 mpc85xx_ads_setup_arch(void)
136 struct device_node *cpu;
139 ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
141 cpu = of_find_node_by_type(NULL, "cpu");
145 fp = (int *)get_property(cpu, "clock-frequency", NULL);
147 loops_per_jiffy = *fp / HZ;
149 loops_per_jiffy = 50000000 / HZ;
153 #ifdef CONFIG_ROOT_NFS
156 ROOT_DEV = Root_HDA1;
162 mpc85xx_ads_show_cpuinfo(struct seq_file *m)
164 uint pvid, svid, phid1;
165 uint memsize = total_memory;
167 pvid = mfspr(SPRN_PVR);
168 svid = mfspr(SPRN_SVR);
170 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
171 seq_printf(m, "Machine\t\t: mpc85xx\n");
172 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
173 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
175 /* Display cpu Pll setting */
176 phid1 = mfspr(SPRN_HID1);
177 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
179 /* Display the amount of memory */
180 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
187 ppc_md.setup_arch = mpc85xx_ads_setup_arch;
188 ppc_md.show_cpuinfo = mpc85xx_ads_show_cpuinfo;
190 ppc_md.init_IRQ = mpc85xx_ads_pic_init;
191 ppc_md.get_irq = mpic_get_irq;
193 ppc_md.restart = mpc85xx_restart;
194 ppc_md.power_off = NULL;
197 ppc_md.time_init = NULL;
198 ppc_md.set_rtc_time = NULL;
199 ppc_md.get_rtc_time = NULL;
200 ppc_md.calibrate_decr = generic_calibrate_decr;
202 ppc_md.progress = udbg_progress;
205 ppc_md.progress("mpc85xx_ads platform_init(): exit", 0);