2 * MPC82xx_ads setup and early boot code plus other random bits.
4 * Author: Vitaly Bordug <vbordug@ru.mvista.com>
5 * m82xx_restart fix by Wade Farnsworth <wfarnsworth@mvista.com>
7 * Copyright (c) 2006 MontaVista Software, Inc.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
15 #include <linux/stddef.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/errno.h>
19 #include <linux/reboot.h>
20 #include <linux/pci.h>
21 #include <linux/interrupt.h>
22 #include <linux/kdev_t.h>
23 #include <linux/major.h>
24 #include <linux/console.h>
25 #include <linux/delay.h>
26 #include <linux/seq_file.h>
27 #include <linux/root_dev.h>
28 #include <linux/initrd.h>
29 #include <linux/module.h>
30 #include <linux/fsl_devices.h>
31 #include <linux/fs_uart_pd.h>
33 #include <asm/system.h>
34 #include <asm/pgtable.h>
36 #include <asm/atomic.h>
39 #include <asm/machdep.h>
40 #include <asm/pci-bridge.h>
41 #include <asm/mpc8260.h>
43 #include <mm/mmu_decl.h>
47 #include <asm/i8259.h>
48 #include <linux/fs_enet_pd.h>
50 #include <sysdev/fsl_soc.h>
51 #include <sysdev/cpm2_pic.h>
56 static uint pci_clk_frq;
58 unsigned long *pci_int_stat_reg;
59 unsigned long *pci_int_mask_reg;
62 static unsigned long pci_int_base;
63 static struct irq_host *pci_pic_host;
66 static void __init mpc82xx_ads_pic_init(void)
68 struct device_node *np = of_find_compatible_node(NULL, "cpm-pic", "CPM2");
73 printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
76 if (of_address_to_resource(np, 0, &r)) {
77 printk(KERN_ERR "PIC init: invalid resource\n");
84 /* Initialize the default interrupt mapping priorities,
85 * in case the boot rom changed something on us.
87 cpm_reg = (cpm2_map_t *) ioremap(get_immrbase(), sizeof(cpm2_map_t));
88 cpm_reg->im_intctl.ic_siprr = 0x05309770;
91 /* Initialize stuff for the 82xx CPLD IC and install demux */
96 static void init_fcc1_ioports(struct fs_platform_info *fpi)
100 cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
101 struct device_node *np;
105 np = of_find_node_by_type(NULL, "memory");
107 printk(KERN_INFO "No memory node in device tree\n");
110 if (of_address_to_resource(np, 1, &r)) {
111 printk(KERN_INFO "No memory reg property [1] in devicetree\n");
115 bcsr = ioremap(r.start + 4, sizeof(u32));
116 io = &immap->im_ioport;
119 clrbits32(bcsr, BCSR1_FETHIEN);
120 setbits32(bcsr, BCSR1_FETH_RST);
122 /* FCC1 pins are on port A/C. */
123 /* Configure port A and C pins for FCC1 Ethernet. */
125 tempval = in_be32(&io->iop_pdira);
126 tempval &= ~PA1_DIRA0;
127 tempval |= PA1_DIRA1;
128 out_be32(&io->iop_pdira, tempval);
130 tempval = in_be32(&io->iop_psora);
131 tempval &= ~PA1_PSORA0;
132 tempval |= PA1_PSORA1;
133 out_be32(&io->iop_psora, tempval);
135 setbits32(&io->iop_ppara, PA1_DIRA0 | PA1_DIRA1);
138 tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
140 clrbits32(&io->iop_psorc, tempval);
141 clrbits32(&io->iop_pdirc, tempval);
142 setbits32(&io->iop_pparc, tempval);
144 cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_rx, CPM_CLK_RX);
145 cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_tx, CPM_CLK_TX);
151 static void init_fcc2_ioports(struct fs_platform_info *fpi)
153 cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
154 struct device_node *np;
161 np = of_find_node_by_type(NULL, "memory");
163 printk(KERN_INFO "No memory node in device tree\n");
166 if (of_address_to_resource(np, 1, &r)) {
167 printk(KERN_INFO "No memory reg property [1] in devicetree\n");
171 io = &immap->im_ioport;
172 bcsr = ioremap(r.start + 12, sizeof(u32));
175 clrbits32(bcsr, BCSR3_FETHIEN2);
176 setbits32(bcsr, BCSR3_FETH2_RST);
178 /* FCC2 are port B/C. */
179 /* Configure port A and C pins for FCC2 Ethernet. */
181 tempval = in_be32(&io->iop_pdirb);
182 tempval &= ~PB2_DIRB0;
183 tempval |= PB2_DIRB1;
184 out_be32(&io->iop_pdirb, tempval);
186 tempval = in_be32(&io->iop_psorb);
187 tempval &= ~PB2_PSORB0;
188 tempval |= PB2_PSORB1;
189 out_be32(&io->iop_psorb, tempval);
191 setbits32(&io->iop_pparb, PB2_DIRB0 | PB2_DIRB1);
193 tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
196 clrbits32(&io->iop_psorc, tempval);
197 clrbits32(&io->iop_pdirc, tempval);
198 setbits32(&io->iop_pparc, tempval);
200 cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_rx, CPM_CLK_RX);
201 cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_tx, CPM_CLK_TX);
207 void init_fcc_ioports(struct fs_platform_info *fpi)
209 int fcc_no = fs_get_fcc_index(fpi->fs_no);
213 init_fcc1_ioports(fpi);
216 init_fcc2_ioports(fpi);
219 printk(KERN_ERR "init_fcc_ioports: invalid FCC number\n");
224 static void init_scc1_uart_ioports(struct fs_uart_platform_info *data)
226 cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
228 /* SCC1 is only on port D */
229 setbits32(&immap->im_ioport.iop_ppard, 0x00000003);
230 clrbits32(&immap->im_ioport.iop_psord, 0x00000001);
231 setbits32(&immap->im_ioport.iop_psord, 0x00000002);
232 clrbits32(&immap->im_ioport.iop_pdird, 0x00000001);
233 setbits32(&immap->im_ioport.iop_pdird, 0x00000002);
235 clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
236 clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
237 setbits32(&immap->im_cpmux.cmx_scr,
238 ((data->clk_tx - 1) << (4 - data->clk_tx)));
239 setbits32(&immap->im_cpmux.cmx_scr,
240 ((data->clk_rx - 1) << (4 - data->clk_rx)));
245 static void init_scc4_uart_ioports(struct fs_uart_platform_info *data)
247 cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
249 setbits32(&immap->im_ioport.iop_ppard, 0x00000600);
250 clrbits32(&immap->im_ioport.iop_psord, 0x00000600);
251 clrbits32(&immap->im_ioport.iop_pdird, 0x00000200);
252 setbits32(&immap->im_ioport.iop_pdird, 0x00000400);
254 clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
255 clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
256 setbits32(&immap->im_cpmux.cmx_scr,
257 ((data->clk_tx - 1) << (4 - data->clk_tx)));
258 setbits32(&immap->im_cpmux.cmx_scr,
259 ((data->clk_rx - 1) << (4 - data->clk_rx)));
264 void init_scc_ioports(struct fs_uart_platform_info *data)
266 int scc_no = fs_get_scc_index(data->fs_no);
270 init_scc1_uart_ioports(data);
271 data->brg = data->clk_rx;
274 init_scc4_uart_ioports(data);
275 data->brg = data->clk_rx;
278 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
283 void __init m82xx_board_setup(void)
285 cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
286 struct device_node *np;
290 np = of_find_node_by_type(NULL, "memory");
292 printk(KERN_INFO "No memory node in device tree\n");
295 if (of_address_to_resource(np, 1, &r)) {
296 printk(KERN_INFO "No memory reg property [1] in devicetree\n");
300 bcsr = ioremap(r.start + 4, sizeof(u32));
301 /* Enable the 2nd UART port */
302 clrbits32(bcsr, BCSR1_RS232_EN2);
304 #ifdef CONFIG_SERIAL_CPM_SCC1
305 clrbits32((u32 *) & immap->im_scc[0].scc_sccm,
306 UART_SCCM_TX | UART_SCCM_RX);
307 clrbits32((u32 *) & immap->im_scc[0].scc_gsmrl,
308 SCC_GSMRL_ENR | SCC_GSMRL_ENT);
311 #ifdef CONFIG_SERIAL_CPM_SCC2
312 clrbits32((u32 *) & immap->im_scc[1].scc_sccm,
313 UART_SCCM_TX | UART_SCCM_RX);
314 clrbits32((u32 *) & immap->im_scc[1].scc_gsmrl,
315 SCC_GSMRL_ENR | SCC_GSMRL_ENT);
318 #ifdef CONFIG_SERIAL_CPM_SCC3
319 clrbits32((u32 *) & immap->im_scc[2].scc_sccm,
320 UART_SCCM_TX | UART_SCCM_RX);
321 clrbits32((u32 *) & immap->im_scc[2].scc_gsmrl,
322 SCC_GSMRL_ENR | SCC_GSMRL_ENT);
325 #ifdef CONFIG_SERIAL_CPM_SCC4
326 clrbits32((u32 *) & immap->im_scc[3].scc_sccm,
327 UART_SCCM_TX | UART_SCCM_RX);
328 clrbits32((u32 *) & immap->im_scc[3].scc_gsmrl,
329 SCC_GSMRL_ENR | SCC_GSMRL_ENT);
337 static void m82xx_pci_mask_irq(unsigned int irq)
339 int bit = irq - pci_int_base;
341 *pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
345 static void m82xx_pci_unmask_irq(unsigned int irq)
347 int bit = irq - pci_int_base;
349 *pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
353 static void m82xx_pci_mask_and_ack(unsigned int irq)
355 int bit = irq - pci_int_base;
357 *pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
361 static void m82xx_pci_end_irq(unsigned int irq)
363 int bit = irq - pci_int_base;
365 *pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
369 struct hw_interrupt_type m82xx_pci_ic = {
370 .typename = "MPC82xx ADS PCI",
371 .name = "MPC82xx ADS PCI",
372 .enable = m82xx_pci_unmask_irq,
373 .disable = m82xx_pci_mask_irq,
374 .ack = m82xx_pci_mask_and_ack,
375 .end = m82xx_pci_end_irq,
376 .mask = m82xx_pci_mask_irq,
377 .mask_ack = m82xx_pci_mask_and_ack,
378 .unmask = m82xx_pci_unmask_irq,
379 .eoi = m82xx_pci_end_irq,
383 m82xx_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
385 unsigned long stat, mask, pend;
389 stat = *pci_regs.pci_int_stat_reg;
390 mask = *pci_regs.pci_int_mask_reg;
391 pend = stat & ~mask & 0xf0000000;
394 for (bit = 0; pend != 0; ++bit, pend <<= 1) {
395 if (pend & 0x80000000)
396 __do_IRQ(pci_int_base + bit);
401 static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
404 get_irq_desc(virq)->status |= IRQ_LEVEL;
405 set_irq_chip(virq, &m82xx_pci_ic);
409 static void pci_host_unmap(struct irq_host *h, unsigned int virq)
411 /* remove chip and handler */
412 set_irq_chip(virq, NULL);
415 static struct irq_host_ops pci_pic_host_ops = {
416 .map = pci_pic_host_map,
417 .unmap = pci_host_unmap,
420 void m82xx_pci_init_irq(void)
424 struct device_node *np;
430 unsigned int irq_max, irq_min;
432 if ((np = of_find_node_by_type(NULL, "soc")) == NULL) {
433 printk(KERN_INFO "No SOC node in device tree\n");
436 memset(&r, 0, sizeof(r));
437 if (of_address_to_resource(np, 0, &r)) {
438 printk(KERN_INFO "No SOC reg property in device tree\n");
441 immap = ioremap(r.start, sizeof(*immap));
444 /* install the demultiplexer for the PCI cascade interrupt */
445 np = of_find_node_by_type(NULL, "pci");
447 printk(KERN_INFO "No pci node on device tree\n");
451 irq_map = of_get_property(np, "interrupt-map", &size);
452 if ((!irq_map) || (size <= 7)) {
453 printk(KERN_INFO "No interrupt-map property of pci node\n");
457 size /= sizeof(irq_map[0]);
458 for (i = 0, irq_max = 0, irq_min = 512; i < size; i += 7, irq_map += 7) {
459 if (irq_map[5] < irq_min)
460 irq_min = irq_map[5];
461 if (irq_map[5] > irq_max)
462 irq_max = irq_map[5];
464 pci_int_base = irq_min;
465 irq = irq_of_parse_and_map(np, 0);
466 set_irq_chained_handler(irq, m82xx_pci_irq_demux);
468 np = of_find_node_by_type(NULL, "pci-pic");
470 printk(KERN_INFO "No pci pic node on device tree\n");
474 /* PCI interrupt controller registers: status and mask */
475 regs = of_get_property(np, "reg", &size);
476 if ((!regs) || (size <= 2)) {
477 printk(KERN_INFO "No reg property in pci pic node\n");
481 pci_regs.pci_int_stat_reg =
482 ioremap(regs[0], sizeof(*pci_regs.pci_int_stat_reg));
483 pci_regs.pci_int_mask_reg =
484 ioremap(regs[1], sizeof(*pci_regs.pci_int_mask_reg));
485 /* configure chip select for PCI interrupt controller */
486 immap->im_memctl.memc_br3 = regs[0] | 0x00001801;
487 immap->im_memctl.memc_or3 = 0xffff8010;
488 /* make PCI IRQ level sensitive */
489 immap->im_intctl.ic_siexr &= ~(1 << (14 - (irq - SIU_INT_IRQ1)));
491 /* mask all PCI interrupts */
492 *pci_regs.pci_int_mask_reg |= 0xfff00000;
495 irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, irq_max - irq_min + 1,
496 &pci_pic_host_ops, irq_max + 1);
500 static int m82xx_pci_exclude_device(struct pci_controller *hose,
501 u_char bus, u_char devfn)
503 if (bus == 0 && PCI_SLOT(devfn) == 0)
504 return PCIBIOS_DEVICE_NOT_FOUND;
506 return PCIBIOS_SUCCESSFUL;
509 static void __init mpc82xx_add_bridge(struct device_node *np)
512 struct pci_controller *hose;
514 const int *bus_range;
517 memset(&r, 0, sizeof(r));
518 if (of_address_to_resource(np, 0, &r)) {
519 printk(KERN_INFO "No PCI reg property in device tree\n");
522 if (!(ptr = of_get_property(np, "clock-frequency", NULL))) {
523 printk(KERN_INFO "No clock-frequency property in PCI node");
528 bus_range = of_get_property(np, "bus-range", &len);
529 if (bus_range == NULL || len < 2 * sizeof(int)) {
530 printk(KERN_WARNING "Can't get bus-range for %s, assume"
531 " bus 0\n", np->full_name);
534 pci_assign_all_buses = 1;
536 hose = pcibios_alloc_controller(np);
541 hose->first_busno = bus_range ? bus_range[0] : 0;
542 hose->last_busno = bus_range ? bus_range[1] : 0xff;
544 setup_indirect_pci(hose,
545 r.start + offsetof(pci_cpm2_t, pci_cfg_addr),
546 r.start + offsetof(pci_cpm2_t, pci_cfg_data),
549 pci_process_bridge_OF_ranges(hose, np, 1);
554 * Setup the architecture
556 static void __init mpc82xx_ads_setup_arch(void)
559 struct device_node *np;
563 ppc_md.progress("mpc82xx_ads_setup_arch()", 0);
566 /* Map I/O region to a 256MB BAT */
571 ppc_md.pci_exclude_device = m82xx_pci_exclude_device;
572 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
573 mpc82xx_add_bridge(np);
578 #ifdef CONFIG_ROOT_NFS
581 ROOT_DEV = Root_HDA1;
585 ppc_md.progress("mpc82xx_ads_setup_arch(), finish", 0);
589 * Called very early, device-tree isn't unflattened
591 static int __init mpc82xx_ads_probe(void)
593 /* We always match for now, eventually we should look at
594 * the flat dev tree to ensure this is the board we are
600 #define RMR_CSRE 0x00000001
601 static void m82xx_restart(char *cmd)
603 __volatile__ unsigned char dummy;
606 ((cpm2_map_t *) cpm2_immr)->im_clkrst.car_rmr |= RMR_CSRE;
608 /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
609 mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
610 dummy = ((cpm2_map_t *) cpm2_immr)->im_clkrst.res[0];
611 printk("Restart failed\n");
615 define_machine(mpc82xx_ads)
617 .name = "MPC82xx ADS",
618 .probe = mpc82xx_ads_probe,
619 .setup_arch = mpc82xx_ads_setup_arch,
620 .init_IRQ = mpc82xx_ads_pic_init,
621 .get_irq = cpm2_get_irq,
622 .calibrate_decr = generic_calibrate_decr,
623 .restart = m82xx_restart,