2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/prctl.h>
30 #include <linux/delay.h>
31 #include <linux/kprobes.h>
32 #include <linux/kexec.h>
33 #include <linux/backlight.h>
34 #include <linux/bug.h>
35 #include <linux/kdebug.h>
36 #include <linux/debugfs.h>
37 #include <linux/ratelimit.h>
39 #include <asm/emulated_ops.h>
40 #include <asm/pgtable.h>
41 #include <asm/uaccess.h>
43 #include <asm/machdep.h>
49 #ifdef CONFIG_PMAC_BACKLIGHT
50 #include <asm/backlight.h>
53 #include <asm/firmware.h>
54 #include <asm/processor.h>
56 #include <asm/kexec.h>
57 #include <asm/ppc-opcode.h>
59 #include <asm/fadump.h>
60 #include <asm/switch_to.h>
61 #include <asm/debug.h>
63 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
64 int (*__debugger)(struct pt_regs *regs) __read_mostly;
65 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
66 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
67 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
68 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
69 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
70 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
72 EXPORT_SYMBOL(__debugger);
73 EXPORT_SYMBOL(__debugger_ipi);
74 EXPORT_SYMBOL(__debugger_bpt);
75 EXPORT_SYMBOL(__debugger_sstep);
76 EXPORT_SYMBOL(__debugger_iabr_match);
77 EXPORT_SYMBOL(__debugger_break_match);
78 EXPORT_SYMBOL(__debugger_fault_handler);
81 /* Transactional Memory trap debug */
83 #define TM_DEBUG(x...) printk(KERN_INFO x)
85 #define TM_DEBUG(x...) do { } while(0)
89 * Trap & Exception support
92 #ifdef CONFIG_PMAC_BACKLIGHT
93 static void pmac_backlight_unblank(void)
95 mutex_lock(&pmac_backlight_mutex);
97 struct backlight_properties *props;
99 props = &pmac_backlight->props;
100 props->brightness = props->max_brightness;
101 props->power = FB_BLANK_UNBLANK;
102 backlight_update_status(pmac_backlight);
104 mutex_unlock(&pmac_backlight_mutex);
107 static inline void pmac_backlight_unblank(void) { }
110 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
111 static int die_owner = -1;
112 static unsigned int die_nest_count;
113 static int die_counter;
115 static unsigned __kprobes long oops_begin(struct pt_regs *regs)
125 /* racy, but better than risking deadlock. */
126 raw_local_irq_save(flags);
127 cpu = smp_processor_id();
128 if (!arch_spin_trylock(&die_lock)) {
129 if (cpu == die_owner)
130 /* nested oops. should stop eventually */;
132 arch_spin_lock(&die_lock);
138 if (machine_is(powermac))
139 pmac_backlight_unblank();
143 static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs,
148 add_taint(TAINT_DIE);
153 /* Nest count reaches zero, release the lock. */
154 arch_spin_unlock(&die_lock);
155 raw_local_irq_restore(flags);
157 crash_fadump(regs, "die oops");
160 * A system reset (0x100) is a request to dump, so we always send
161 * it through the crashdump code.
163 if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) {
167 * We aren't the primary crash CPU. We need to send it
168 * to a holding pattern to avoid it ending up in the panic
171 crash_kexec_secondary(regs);
178 * While our oops output is serialised by a spinlock, output
179 * from panic() called below can race and corrupt it. If we
180 * know we are going to panic, delay for 1 second so we have a
181 * chance to get clean backtraces from all CPUs that are oopsing.
183 if (in_interrupt() || panic_on_oops || !current->pid ||
184 is_global_init(current)) {
185 mdelay(MSEC_PER_SEC);
189 panic("Fatal exception in interrupt");
191 panic("Fatal exception");
195 static int __kprobes __die(const char *str, struct pt_regs *regs, long err)
197 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
198 #ifdef CONFIG_PREEMPT
202 printk("SMP NR_CPUS=%d ", NR_CPUS);
204 #ifdef CONFIG_DEBUG_PAGEALLOC
205 printk("DEBUG_PAGEALLOC ");
210 printk("%s\n", ppc_md.name ? ppc_md.name : "");
212 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
221 void die(const char *str, struct pt_regs *regs, long err)
223 unsigned long flags = oops_begin(regs);
225 if (__die(str, regs, err))
227 oops_end(flags, regs, err);
230 void user_single_step_siginfo(struct task_struct *tsk,
231 struct pt_regs *regs, siginfo_t *info)
233 memset(info, 0, sizeof(*info));
234 info->si_signo = SIGTRAP;
235 info->si_code = TRAP_TRACE;
236 info->si_addr = (void __user *)regs->nip;
239 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
242 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
243 "at %08lx nip %08lx lr %08lx code %x\n";
244 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
245 "at %016lx nip %016lx lr %016lx code %x\n";
247 if (!user_mode(regs)) {
248 die("Exception in kernel mode", regs, signr);
252 if (show_unhandled_signals && unhandled_signal(current, signr)) {
253 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
254 current->comm, current->pid, signr,
255 addr, regs->nip, regs->link, code);
258 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
261 current->thread.trap_nr = code;
262 memset(&info, 0, sizeof(info));
263 info.si_signo = signr;
265 info.si_addr = (void __user *) addr;
266 force_sig_info(signr, &info, current);
270 void system_reset_exception(struct pt_regs *regs)
272 /* See if any machine dependent calls */
273 if (ppc_md.system_reset_exception) {
274 if (ppc_md.system_reset_exception(regs))
278 die("System Reset", regs, SIGABRT);
280 /* Must die if the interrupt is not recoverable */
281 if (!(regs->msr & MSR_RI))
282 panic("Unrecoverable System Reset");
284 /* What should we do here? We could issue a shutdown or hard reset. */
289 * I/O accesses can cause machine checks on powermacs.
290 * Check if the NIP corresponds to the address of a sync
291 * instruction for which there is an entry in the exception
293 * Note that the 601 only takes a machine check on TEA
294 * (transfer error ack) signal assertion, and does not
295 * set any of the top 16 bits of SRR1.
298 static inline int check_io_access(struct pt_regs *regs)
301 unsigned long msr = regs->msr;
302 const struct exception_table_entry *entry;
303 unsigned int *nip = (unsigned int *)regs->nip;
305 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
306 && (entry = search_exception_tables(regs->nip)) != NULL) {
308 * Check that it's a sync instruction, or somewhere
309 * in the twi; isync; nop sequence that inb/inw/inl uses.
310 * As the address is in the exception table
311 * we should be able to read the instr there.
312 * For the debug message, we look at the preceding
315 if (*nip == 0x60000000) /* nop */
317 else if (*nip == 0x4c00012c) /* isync */
319 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
324 rb = (*nip >> 11) & 0x1f;
325 printk(KERN_DEBUG "%s bad port %lx at %p\n",
326 (*nip & 0x100)? "OUT to": "IN from",
327 regs->gpr[rb] - _IO_BASE, nip);
329 regs->nip = entry->fixup;
333 #endif /* CONFIG_PPC32 */
337 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
338 /* On 4xx, the reason for the machine check or program exception
340 #define get_reason(regs) ((regs)->dsisr)
341 #ifndef CONFIG_FSL_BOOKE
342 #define get_mc_reason(regs) ((regs)->dsisr)
344 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
346 #define REASON_FP ESR_FP
347 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
348 #define REASON_PRIVILEGED ESR_PPR
349 #define REASON_TRAP ESR_PTR
351 /* single-step stuff */
352 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
353 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
356 /* On non-4xx, the reason for the machine check or program
357 exception is in the MSR. */
358 #define get_reason(regs) ((regs)->msr)
359 #define get_mc_reason(regs) ((regs)->msr)
360 #define REASON_TM 0x200000
361 #define REASON_FP 0x100000
362 #define REASON_ILLEGAL 0x80000
363 #define REASON_PRIVILEGED 0x40000
364 #define REASON_TRAP 0x20000
366 #define single_stepping(regs) ((regs)->msr & MSR_SE)
367 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
370 #if defined(CONFIG_4xx)
371 int machine_check_4xx(struct pt_regs *regs)
373 unsigned long reason = get_mc_reason(regs);
375 if (reason & ESR_IMCP) {
376 printk("Instruction");
377 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
380 printk(" machine check in kernel mode.\n");
385 int machine_check_440A(struct pt_regs *regs)
387 unsigned long reason = get_mc_reason(regs);
389 printk("Machine check in kernel mode.\n");
390 if (reason & ESR_IMCP){
391 printk("Instruction Synchronous Machine Check exception\n");
392 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
395 u32 mcsr = mfspr(SPRN_MCSR);
397 printk("Instruction Read PLB Error\n");
399 printk("Data Read PLB Error\n");
401 printk("Data Write PLB Error\n");
402 if (mcsr & MCSR_TLBP)
403 printk("TLB Parity Error\n");
404 if (mcsr & MCSR_ICP){
405 flush_instruction_cache();
406 printk("I-Cache Parity Error\n");
408 if (mcsr & MCSR_DCSP)
409 printk("D-Cache Search Parity Error\n");
410 if (mcsr & MCSR_DCFP)
411 printk("D-Cache Flush Parity Error\n");
412 if (mcsr & MCSR_IMPE)
413 printk("Machine Check exception is imprecise\n");
416 mtspr(SPRN_MCSR, mcsr);
421 int machine_check_47x(struct pt_regs *regs)
423 unsigned long reason = get_mc_reason(regs);
426 printk(KERN_ERR "Machine check in kernel mode.\n");
427 if (reason & ESR_IMCP) {
429 "Instruction Synchronous Machine Check exception\n");
430 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
433 mcsr = mfspr(SPRN_MCSR);
435 printk(KERN_ERR "Instruction Read PLB Error\n");
437 printk(KERN_ERR "Data Read PLB Error\n");
439 printk(KERN_ERR "Data Write PLB Error\n");
440 if (mcsr & MCSR_TLBP)
441 printk(KERN_ERR "TLB Parity Error\n");
442 if (mcsr & MCSR_ICP) {
443 flush_instruction_cache();
444 printk(KERN_ERR "I-Cache Parity Error\n");
446 if (mcsr & MCSR_DCSP)
447 printk(KERN_ERR "D-Cache Search Parity Error\n");
448 if (mcsr & PPC47x_MCSR_GPR)
449 printk(KERN_ERR "GPR Parity Error\n");
450 if (mcsr & PPC47x_MCSR_FPR)
451 printk(KERN_ERR "FPR Parity Error\n");
452 if (mcsr & PPC47x_MCSR_IPR)
453 printk(KERN_ERR "Machine Check exception is imprecise\n");
456 mtspr(SPRN_MCSR, mcsr);
460 #elif defined(CONFIG_E500)
461 int machine_check_e500mc(struct pt_regs *regs)
463 unsigned long mcsr = mfspr(SPRN_MCSR);
464 unsigned long reason = mcsr;
467 if (reason & MCSR_LD) {
468 recoverable = fsl_rio_mcheck_exception(regs);
469 if (recoverable == 1)
473 printk("Machine check in kernel mode.\n");
474 printk("Caused by (from MCSR=%lx): ", reason);
476 if (reason & MCSR_MCP)
477 printk("Machine Check Signal\n");
479 if (reason & MCSR_ICPERR) {
480 printk("Instruction Cache Parity Error\n");
483 * This is recoverable by invalidating the i-cache.
485 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
486 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
490 * This will generally be accompanied by an instruction
491 * fetch error report -- only treat MCSR_IF as fatal
492 * if it wasn't due to an L1 parity error.
497 if (reason & MCSR_DCPERR_MC) {
498 printk("Data Cache Parity Error\n");
501 * In write shadow mode we auto-recover from the error, but it
502 * may still get logged and cause a machine check. We should
503 * only treat the non-write shadow case as non-recoverable.
505 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
509 if (reason & MCSR_L2MMU_MHIT) {
510 printk("Hit on multiple TLB entries\n");
514 if (reason & MCSR_NMI)
515 printk("Non-maskable interrupt\n");
517 if (reason & MCSR_IF) {
518 printk("Instruction Fetch Error Report\n");
522 if (reason & MCSR_LD) {
523 printk("Load Error Report\n");
527 if (reason & MCSR_ST) {
528 printk("Store Error Report\n");
532 if (reason & MCSR_LDG) {
533 printk("Guarded Load Error Report\n");
537 if (reason & MCSR_TLBSYNC)
538 printk("Simultaneous tlbsync operations\n");
540 if (reason & MCSR_BSL2_ERR) {
541 printk("Level 2 Cache Error\n");
545 if (reason & MCSR_MAV) {
548 addr = mfspr(SPRN_MCAR);
549 addr |= (u64)mfspr(SPRN_MCARU) << 32;
551 printk("Machine Check %s Address: %#llx\n",
552 reason & MCSR_MEA ? "Effective" : "Physical", addr);
556 mtspr(SPRN_MCSR, mcsr);
557 return mfspr(SPRN_MCSR) == 0 && recoverable;
560 int machine_check_e500(struct pt_regs *regs)
562 unsigned long reason = get_mc_reason(regs);
564 if (reason & MCSR_BUS_RBERR) {
565 if (fsl_rio_mcheck_exception(regs))
569 printk("Machine check in kernel mode.\n");
570 printk("Caused by (from MCSR=%lx): ", reason);
572 if (reason & MCSR_MCP)
573 printk("Machine Check Signal\n");
574 if (reason & MCSR_ICPERR)
575 printk("Instruction Cache Parity Error\n");
576 if (reason & MCSR_DCP_PERR)
577 printk("Data Cache Push Parity Error\n");
578 if (reason & MCSR_DCPERR)
579 printk("Data Cache Parity Error\n");
580 if (reason & MCSR_BUS_IAERR)
581 printk("Bus - Instruction Address Error\n");
582 if (reason & MCSR_BUS_RAERR)
583 printk("Bus - Read Address Error\n");
584 if (reason & MCSR_BUS_WAERR)
585 printk("Bus - Write Address Error\n");
586 if (reason & MCSR_BUS_IBERR)
587 printk("Bus - Instruction Data Error\n");
588 if (reason & MCSR_BUS_RBERR)
589 printk("Bus - Read Data Bus Error\n");
590 if (reason & MCSR_BUS_WBERR)
591 printk("Bus - Read Data Bus Error\n");
592 if (reason & MCSR_BUS_IPERR)
593 printk("Bus - Instruction Parity Error\n");
594 if (reason & MCSR_BUS_RPERR)
595 printk("Bus - Read Parity Error\n");
600 int machine_check_generic(struct pt_regs *regs)
604 #elif defined(CONFIG_E200)
605 int machine_check_e200(struct pt_regs *regs)
607 unsigned long reason = get_mc_reason(regs);
609 printk("Machine check in kernel mode.\n");
610 printk("Caused by (from MCSR=%lx): ", reason);
612 if (reason & MCSR_MCP)
613 printk("Machine Check Signal\n");
614 if (reason & MCSR_CP_PERR)
615 printk("Cache Push Parity Error\n");
616 if (reason & MCSR_CPERR)
617 printk("Cache Parity Error\n");
618 if (reason & MCSR_EXCP_ERR)
619 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
620 if (reason & MCSR_BUS_IRERR)
621 printk("Bus - Read Bus Error on instruction fetch\n");
622 if (reason & MCSR_BUS_DRERR)
623 printk("Bus - Read Bus Error on data load\n");
624 if (reason & MCSR_BUS_WRERR)
625 printk("Bus - Write Bus Error on buffered store or cache line push\n");
630 int machine_check_generic(struct pt_regs *regs)
632 unsigned long reason = get_mc_reason(regs);
634 printk("Machine check in kernel mode.\n");
635 printk("Caused by (from SRR1=%lx): ", reason);
636 switch (reason & 0x601F0000) {
638 printk("Machine check signal\n");
640 case 0: /* for 601 */
642 case 0x140000: /* 7450 MSS error and TEA */
643 printk("Transfer error ack signal\n");
646 printk("Data parity error signal\n");
649 printk("Address parity error signal\n");
652 printk("L1 Data Cache error\n");
655 printk("L1 Instruction Cache error\n");
658 printk("L2 data cache parity error\n");
661 printk("Unknown values in msr\n");
665 #endif /* everything else */
667 void machine_check_exception(struct pt_regs *regs)
671 __get_cpu_var(irq_stat).mce_exceptions++;
673 /* See if any machine dependent calls. In theory, we would want
674 * to call the CPU first, and call the ppc_md. one if the CPU
675 * one returns a positive number. However there is existing code
676 * that assumes the board gets a first chance, so let's keep it
677 * that way for now and fix things later. --BenH.
679 if (ppc_md.machine_check_exception)
680 recover = ppc_md.machine_check_exception(regs);
681 else if (cur_cpu_spec->machine_check)
682 recover = cur_cpu_spec->machine_check(regs);
687 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
688 /* the qspan pci read routines can cause machine checks -- Cort
690 * yuck !!! that totally needs to go away ! There are better ways
691 * to deal with that than having a wart in the mcheck handler.
694 bad_page_fault(regs, regs->dar, SIGBUS);
698 if (debugger_fault_handler(regs))
701 if (check_io_access(regs))
704 die("Machine check", regs, SIGBUS);
706 /* Must die if the interrupt is not recoverable */
707 if (!(regs->msr & MSR_RI))
708 panic("Unrecoverable Machine check");
711 void SMIException(struct pt_regs *regs)
713 die("System Management Interrupt", regs, SIGABRT);
716 void unknown_exception(struct pt_regs *regs)
718 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
719 regs->nip, regs->msr, regs->trap);
721 _exception(SIGTRAP, regs, 0, 0);
724 void instruction_breakpoint_exception(struct pt_regs *regs)
726 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
727 5, SIGTRAP) == NOTIFY_STOP)
729 if (debugger_iabr_match(regs))
731 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
734 void RunModeException(struct pt_regs *regs)
736 _exception(SIGTRAP, regs, 0, 0);
739 void __kprobes single_step_exception(struct pt_regs *regs)
741 clear_single_step(regs);
743 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
744 5, SIGTRAP) == NOTIFY_STOP)
746 if (debugger_sstep(regs))
749 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
753 * After we have successfully emulated an instruction, we have to
754 * check if the instruction was being single-stepped, and if so,
755 * pretend we got a single-step exception. This was pointed out
756 * by Kumar Gala. -- paulus
758 static void emulate_single_step(struct pt_regs *regs)
760 if (single_stepping(regs))
761 single_step_exception(regs);
764 static inline int __parse_fpscr(unsigned long fpscr)
768 /* Invalid operation */
769 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
773 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
777 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
781 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
785 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
791 static void parse_fpe(struct pt_regs *regs)
795 flush_fp_to_thread(current);
797 code = __parse_fpscr(current->thread.fpscr.val);
799 _exception(SIGFPE, regs, code, regs->nip);
803 * Illegal instruction emulation support. Originally written to
804 * provide the PVR to user applications using the mfspr rd, PVR.
805 * Return non-zero if we can't emulate, or -EFAULT if the associated
806 * memory access caused an access fault. Return zero on success.
808 * There are a couple of ways to do this, either "decode" the instruction
809 * or directly match lots of bits. In this case, matching lots of
810 * bits is faster and easier.
813 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
815 u8 rT = (instword >> 21) & 0x1f;
816 u8 rA = (instword >> 16) & 0x1f;
817 u8 NB_RB = (instword >> 11) & 0x1f;
822 /* Early out if we are an invalid form of lswx */
823 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
824 if ((rT == rA) || (rT == NB_RB))
827 EA = (rA == 0) ? 0 : regs->gpr[rA];
829 switch (instword & PPC_INST_STRING_MASK) {
833 num_bytes = regs->xer & 0x7f;
837 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
843 while (num_bytes != 0)
846 u32 shift = 8 * (3 - (pos & 0x3));
848 switch ((instword & PPC_INST_STRING_MASK)) {
851 if (get_user(val, (u8 __user *)EA))
853 /* first time updating this reg,
857 regs->gpr[rT] |= val << shift;
861 val = regs->gpr[rT] >> shift;
862 if (put_user(val, (u8 __user *)EA))
866 /* move EA to next address */
870 /* manage our position within the register */
881 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
886 ra = (instword >> 16) & 0x1f;
887 rs = (instword >> 21) & 0x1f;
890 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
891 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
892 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
898 static int emulate_isel(struct pt_regs *regs, u32 instword)
900 u8 rT = (instword >> 21) & 0x1f;
901 u8 rA = (instword >> 16) & 0x1f;
902 u8 rB = (instword >> 11) & 0x1f;
903 u8 BC = (instword >> 6) & 0x1f;
907 tmp = (rA == 0) ? 0 : regs->gpr[rA];
908 bit = (regs->ccr >> (31 - BC)) & 0x1;
910 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
915 static int emulate_instruction(struct pt_regs *regs)
920 if (!user_mode(regs) || (regs->msr & MSR_LE))
922 CHECK_FULL_REGS(regs);
924 if (get_user(instword, (u32 __user *)(regs->nip)))
927 /* Emulate the mfspr rD, PVR. */
928 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
929 PPC_WARN_EMULATED(mfpvr, regs);
930 rd = (instword >> 21) & 0x1f;
931 regs->gpr[rd] = mfspr(SPRN_PVR);
935 /* Emulating the dcba insn is just a no-op. */
936 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
937 PPC_WARN_EMULATED(dcba, regs);
941 /* Emulate the mcrxr insn. */
942 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
943 int shift = (instword >> 21) & 0x1c;
944 unsigned long msk = 0xf0000000UL >> shift;
946 PPC_WARN_EMULATED(mcrxr, regs);
947 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
948 regs->xer &= ~0xf0000000UL;
952 /* Emulate load/store string insn. */
953 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
954 PPC_WARN_EMULATED(string, regs);
955 return emulate_string_inst(regs, instword);
958 /* Emulate the popcntb (Population Count Bytes) instruction. */
959 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
960 PPC_WARN_EMULATED(popcntb, regs);
961 return emulate_popcntb_inst(regs, instword);
964 /* Emulate isel (Integer Select) instruction */
965 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
966 PPC_WARN_EMULATED(isel, regs);
967 return emulate_isel(regs, instword);
971 /* Emulate the mfspr rD, DSCR. */
972 if (((instword & PPC_INST_MFSPR_DSCR_MASK) == PPC_INST_MFSPR_DSCR) &&
973 cpu_has_feature(CPU_FTR_DSCR)) {
974 PPC_WARN_EMULATED(mfdscr, regs);
975 rd = (instword >> 21) & 0x1f;
976 regs->gpr[rd] = mfspr(SPRN_DSCR);
979 /* Emulate the mtspr DSCR, rD. */
980 if (((instword & PPC_INST_MTSPR_DSCR_MASK) == PPC_INST_MTSPR_DSCR) &&
981 cpu_has_feature(CPU_FTR_DSCR)) {
982 PPC_WARN_EMULATED(mtdscr, regs);
983 rd = (instword >> 21) & 0x1f;
984 current->thread.dscr = regs->gpr[rd];
985 current->thread.dscr_inherit = 1;
986 mtspr(SPRN_DSCR, current->thread.dscr);
994 int is_valid_bugaddr(unsigned long addr)
996 return is_kernel_addr(addr);
999 void __kprobes program_check_exception(struct pt_regs *regs)
1001 unsigned int reason = get_reason(regs);
1002 extern int do_mathemu(struct pt_regs *regs);
1004 /* We can now get here via a FP Unavailable exception if the core
1005 * has no FPU, in that case the reason flags will be 0 */
1007 if (reason & REASON_FP) {
1008 /* IEEE FP exception */
1012 if (reason & REASON_TRAP) {
1013 /* Debugger is first in line to stop recursive faults in
1014 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1015 if (debugger_bpt(regs))
1018 /* trap exception */
1019 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1023 if (!(regs->msr & MSR_PR) && /* not user-mode */
1024 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1028 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1032 /* We restore the interrupt state now */
1033 if (!arch_irq_disabled_regs(regs))
1036 #ifdef CONFIG_MATH_EMULATION
1037 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1038 * but there seems to be a hardware bug on the 405GP (RevD)
1039 * that means ESR is sometimes set incorrectly - either to
1040 * ESR_DST (!?) or 0. In the process of chasing this with the
1041 * hardware people - not sure if it can happen on any illegal
1042 * instruction or only on FP instructions, whether there is a
1043 * pattern to occurrences etc. -dgibson 31/Mar/2003 */
1044 switch (do_mathemu(regs)) {
1046 emulate_single_step(regs);
1050 code = __parse_fpscr(current->thread.fpscr.val);
1051 _exception(SIGFPE, regs, code, regs->nip);
1055 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1058 /* fall through on any other errors */
1059 #endif /* CONFIG_MATH_EMULATION */
1061 /* Try to emulate it if we should. */
1062 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1063 switch (emulate_instruction(regs)) {
1066 emulate_single_step(regs);
1069 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1074 if (reason & REASON_PRIVILEGED)
1075 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1077 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1080 void alignment_exception(struct pt_regs *regs)
1082 int sig, code, fixed = 0;
1084 /* We restore the interrupt state now */
1085 if (!arch_irq_disabled_regs(regs))
1088 /* we don't implement logging of alignment exceptions */
1089 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1090 fixed = fix_alignment(regs);
1093 regs->nip += 4; /* skip over emulated instruction */
1094 emulate_single_step(regs);
1098 /* Operand address was bad */
1099 if (fixed == -EFAULT) {
1106 if (user_mode(regs))
1107 _exception(sig, regs, code, regs->dar);
1109 bad_page_fault(regs, regs->dar, sig);
1112 void StackOverflow(struct pt_regs *regs)
1114 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
1115 current, regs->gpr[1]);
1118 panic("kernel stack overflow");
1121 void nonrecoverable_exception(struct pt_regs *regs)
1123 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1124 regs->nip, regs->msr);
1126 die("nonrecoverable exception", regs, SIGKILL);
1129 void trace_syscall(struct pt_regs *regs)
1131 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
1132 current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0],
1133 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
1136 void kernel_fp_unavailable_exception(struct pt_regs *regs)
1138 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1139 "%lx at %lx\n", regs->trap, regs->nip);
1140 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1143 void altivec_unavailable_exception(struct pt_regs *regs)
1145 if (user_mode(regs)) {
1146 /* A user program has executed an altivec instruction,
1147 but this kernel doesn't support altivec. */
1148 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1152 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1153 "%lx at %lx\n", regs->trap, regs->nip);
1154 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1157 void vsx_unavailable_exception(struct pt_regs *regs)
1159 if (user_mode(regs)) {
1160 /* A user program has executed an vsx instruction,
1161 but this kernel doesn't support vsx. */
1162 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1166 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1167 "%lx at %lx\n", regs->trap, regs->nip);
1168 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1171 void tm_unavailable_exception(struct pt_regs *regs)
1173 /* We restore the interrupt state now */
1174 if (!arch_irq_disabled_regs(regs))
1177 /* Currently we never expect a TMU exception. Catch
1178 * this and kill the process!
1180 printk(KERN_EMERG "Unexpected TM unavailable exception at %lx "
1182 regs->nip, regs->msr);
1184 if (user_mode(regs)) {
1185 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1189 die("Unexpected TM unavailable exception", regs, SIGABRT);
1192 void performance_monitor_exception(struct pt_regs *regs)
1194 __get_cpu_var(irq_stat).pmu_irqs++;
1200 void SoftwareEmulation(struct pt_regs *regs)
1202 extern int do_mathemu(struct pt_regs *);
1203 extern int Soft_emulate_8xx(struct pt_regs *);
1204 #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU)
1208 CHECK_FULL_REGS(regs);
1210 if (!user_mode(regs)) {
1212 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
1215 #ifdef CONFIG_MATH_EMULATION
1216 errcode = do_mathemu(regs);
1218 PPC_WARN_EMULATED(math, regs);
1222 emulate_single_step(regs);
1226 code = __parse_fpscr(current->thread.fpscr.val);
1227 _exception(SIGFPE, regs, code, regs->nip);
1231 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1234 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1238 #elif defined(CONFIG_8XX_MINIMAL_FPEMU)
1239 errcode = Soft_emulate_8xx(regs);
1241 PPC_WARN_EMULATED(8xx, regs);
1245 emulate_single_step(regs);
1248 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1251 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1255 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1258 #endif /* CONFIG_8xx */
1260 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1261 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1265 * Determine the cause of the debug event, clear the
1266 * event flags and send a trap to the handler. Torez
1268 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1269 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1270 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1271 current->thread.dbcr2 &= ~DBCR2_DAC12MODE;
1273 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
1276 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1277 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1278 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
1281 } else if (debug_status & DBSR_IAC1) {
1282 current->thread.dbcr0 &= ~DBCR0_IAC1;
1283 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1284 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
1287 } else if (debug_status & DBSR_IAC2) {
1288 current->thread.dbcr0 &= ~DBCR0_IAC2;
1289 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
1292 } else if (debug_status & DBSR_IAC3) {
1293 current->thread.dbcr0 &= ~DBCR0_IAC3;
1294 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1295 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
1298 } else if (debug_status & DBSR_IAC4) {
1299 current->thread.dbcr0 &= ~DBCR0_IAC4;
1300 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
1305 * At the point this routine was called, the MSR(DE) was turned off.
1306 * Check all other debug flags and see if that bit needs to be turned
1309 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1))
1310 regs->msr |= MSR_DE;
1312 /* Make sure the IDM flag is off */
1313 current->thread.dbcr0 &= ~DBCR0_IDM;
1316 mtspr(SPRN_DBCR0, current->thread.dbcr0);
1319 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
1321 current->thread.dbsr = debug_status;
1323 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1324 * on server, it stops on the target of the branch. In order to simulate
1325 * the server behaviour, we thus restart right away with a single step
1326 * instead of stopping here when hitting a BT
1328 if (debug_status & DBSR_BT) {
1329 regs->msr &= ~MSR_DE;
1332 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1333 /* Clear the BT event */
1334 mtspr(SPRN_DBSR, DBSR_BT);
1336 /* Do the single step trick only when coming from userspace */
1337 if (user_mode(regs)) {
1338 current->thread.dbcr0 &= ~DBCR0_BT;
1339 current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1340 regs->msr |= MSR_DE;
1344 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1345 5, SIGTRAP) == NOTIFY_STOP) {
1348 if (debugger_sstep(regs))
1350 } else if (debug_status & DBSR_IC) { /* Instruction complete */
1351 regs->msr &= ~MSR_DE;
1353 /* Disable instruction completion */
1354 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1355 /* Clear the instruction completion event */
1356 mtspr(SPRN_DBSR, DBSR_IC);
1358 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1359 5, SIGTRAP) == NOTIFY_STOP) {
1363 if (debugger_sstep(regs))
1366 if (user_mode(regs)) {
1367 current->thread.dbcr0 &= ~DBCR0_IC;
1368 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0,
1369 current->thread.dbcr1))
1370 regs->msr |= MSR_DE;
1372 /* Make sure the IDM bit is off */
1373 current->thread.dbcr0 &= ~DBCR0_IDM;
1376 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1378 handle_debug(regs, debug_status);
1380 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1382 #if !defined(CONFIG_TAU_INT)
1383 void TAUException(struct pt_regs *regs)
1385 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1386 regs->nip, regs->msr, regs->trap, print_tainted());
1388 #endif /* CONFIG_INT_TAU */
1390 #ifdef CONFIG_ALTIVEC
1391 void altivec_assist_exception(struct pt_regs *regs)
1395 if (!user_mode(regs)) {
1396 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1397 " at %lx\n", regs->nip);
1398 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1401 flush_altivec_to_thread(current);
1403 PPC_WARN_EMULATED(altivec, regs);
1404 err = emulate_altivec(regs);
1406 regs->nip += 4; /* skip emulated instruction */
1407 emulate_single_step(regs);
1411 if (err == -EFAULT) {
1412 /* got an error reading the instruction */
1413 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1415 /* didn't recognize the instruction */
1416 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1417 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
1418 "in %s at %lx\n", current->comm, regs->nip);
1419 current->thread.vscr.u[3] |= 0x10000;
1422 #endif /* CONFIG_ALTIVEC */
1425 void vsx_assist_exception(struct pt_regs *regs)
1427 if (!user_mode(regs)) {
1428 printk(KERN_EMERG "VSX assist exception in kernel mode"
1429 " at %lx\n", regs->nip);
1430 die("Kernel VSX assist exception", regs, SIGILL);
1433 flush_vsx_to_thread(current);
1434 printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip);
1435 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1437 #endif /* CONFIG_VSX */
1439 #ifdef CONFIG_FSL_BOOKE
1440 void CacheLockingException(struct pt_regs *regs, unsigned long address,
1441 unsigned long error_code)
1443 /* We treat cache locking instructions from the user
1444 * as priv ops, in the future we could try to do
1447 if (error_code & (ESR_DLK|ESR_ILK))
1448 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1451 #endif /* CONFIG_FSL_BOOKE */
1454 void SPEFloatingPointException(struct pt_regs *regs)
1456 extern int do_spe_mathemu(struct pt_regs *regs);
1457 unsigned long spefscr;
1462 flush_spe_to_thread(current);
1464 spefscr = current->thread.spefscr;
1465 fpexc_mode = current->thread.fpexc_mode;
1467 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1470 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1473 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1475 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1478 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1481 err = do_spe_mathemu(regs);
1483 regs->nip += 4; /* skip emulated instruction */
1484 emulate_single_step(regs);
1488 if (err == -EFAULT) {
1489 /* got an error reading the instruction */
1490 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1491 } else if (err == -EINVAL) {
1492 /* didn't recognize the instruction */
1493 printk(KERN_ERR "unrecognized spe instruction "
1494 "in %s at %lx\n", current->comm, regs->nip);
1496 _exception(SIGFPE, regs, code, regs->nip);
1502 void SPEFloatingPointRoundException(struct pt_regs *regs)
1504 extern int speround_handler(struct pt_regs *regs);
1508 if (regs->msr & MSR_SPE)
1509 giveup_spe(current);
1513 err = speround_handler(regs);
1515 regs->nip += 4; /* skip emulated instruction */
1516 emulate_single_step(regs);
1520 if (err == -EFAULT) {
1521 /* got an error reading the instruction */
1522 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1523 } else if (err == -EINVAL) {
1524 /* didn't recognize the instruction */
1525 printk(KERN_ERR "unrecognized spe instruction "
1526 "in %s at %lx\n", current->comm, regs->nip);
1528 _exception(SIGFPE, regs, 0, regs->nip);
1535 * We enter here if we get an unrecoverable exception, that is, one
1536 * that happened at a point where the RI (recoverable interrupt) bit
1537 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1538 * we therefore lost state by taking this exception.
1540 void unrecoverable_exception(struct pt_regs *regs)
1542 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1543 regs->trap, regs->nip);
1544 die("Unrecoverable exception", regs, SIGABRT);
1547 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
1549 * Default handler for a Watchdog exception,
1550 * spins until a reboot occurs
1552 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1554 /* Generic WatchdogHandler, implement your own */
1555 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1559 void WatchdogException(struct pt_regs *regs)
1561 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1562 WatchdogHandler(regs);
1567 * We enter here if we discover during exception entry that we are
1568 * running in supervisor mode with a userspace value in the stack pointer.
1570 void kernel_bad_stack(struct pt_regs *regs)
1572 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1573 regs->gpr[1], regs->nip);
1574 die("Bad kernel stack pointer", regs, SIGABRT);
1577 void __init trap_init(void)
1582 #ifdef CONFIG_PPC_EMULATED_STATS
1584 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1586 struct ppc_emulated ppc_emulated = {
1587 #ifdef CONFIG_ALTIVEC
1588 WARN_EMULATED_SETUP(altivec),
1590 WARN_EMULATED_SETUP(dcba),
1591 WARN_EMULATED_SETUP(dcbz),
1592 WARN_EMULATED_SETUP(fp_pair),
1593 WARN_EMULATED_SETUP(isel),
1594 WARN_EMULATED_SETUP(mcrxr),
1595 WARN_EMULATED_SETUP(mfpvr),
1596 WARN_EMULATED_SETUP(multiple),
1597 WARN_EMULATED_SETUP(popcntb),
1598 WARN_EMULATED_SETUP(spe),
1599 WARN_EMULATED_SETUP(string),
1600 WARN_EMULATED_SETUP(unaligned),
1601 #ifdef CONFIG_MATH_EMULATION
1602 WARN_EMULATED_SETUP(math),
1603 #elif defined(CONFIG_8XX_MINIMAL_FPEMU)
1604 WARN_EMULATED_SETUP(8xx),
1607 WARN_EMULATED_SETUP(vsx),
1610 WARN_EMULATED_SETUP(mfdscr),
1611 WARN_EMULATED_SETUP(mtdscr),
1615 u32 ppc_warn_emulated;
1617 void ppc_warn_emulated_print(const char *type)
1619 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
1623 static int __init ppc_warn_emulated_init(void)
1625 struct dentry *dir, *d;
1627 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
1629 if (!powerpc_debugfs_root)
1632 dir = debugfs_create_dir("emulated_instructions",
1633 powerpc_debugfs_root);
1637 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
1638 &ppc_warn_emulated);
1642 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
1643 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
1644 (u32 *)&entries[i].val.counter);
1652 debugfs_remove_recursive(dir);
1656 device_initcall(ppc_warn_emulated_init);
1658 #endif /* CONFIG_PPC_EMULATED_STATS */