2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/list.h>
29 #include <linux/syscalls.h>
30 #include <linux/irq.h>
31 #include <linux/vmalloc.h>
32 #include <linux/slab.h>
34 #include <asm/processor.h>
37 #include <asm/pci-bridge.h>
38 #include <asm/byteorder.h>
39 #include <asm/machdep.h>
40 #include <asm/ppc-pci.h>
41 #include <asm/firmware.h>
44 static DEFINE_SPINLOCK(hose_spinlock);
47 /* XXX kill that some day ... */
48 static int global_phb_number; /* Global phb counter */
50 /* ISA Memory physical address */
51 resource_size_t isa_mem_base;
53 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
54 unsigned int pci_flags = 0;
57 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
59 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
61 pci_dma_ops = dma_ops;
64 struct dma_map_ops *get_pci_dma_ops(void)
68 EXPORT_SYMBOL(get_pci_dma_ops);
70 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
72 struct pci_controller *phb;
74 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
77 spin_lock(&hose_spinlock);
78 phb->global_number = global_phb_number++;
79 list_add_tail(&phb->list_node, &hose_list);
80 spin_unlock(&hose_spinlock);
82 phb->is_dynamic = mem_init_done;
85 int nid = of_node_to_nid(dev);
87 if (nid < 0 || !node_online(nid))
90 PHB_SET_NODE(phb, nid);
96 void pcibios_free_controller(struct pci_controller *phb)
98 spin_lock(&hose_spinlock);
99 list_del(&phb->list_node);
100 spin_unlock(&hose_spinlock);
106 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
109 return hose->pci_io_size;
111 return resource_size(&hose->io_resource);
115 int pcibios_vaddr_is_ioport(void __iomem *address)
118 struct pci_controller *hose;
119 resource_size_t size;
121 spin_lock(&hose_spinlock);
122 list_for_each_entry(hose, &hose_list, list_node) {
123 size = pcibios_io_size(hose);
124 if (address >= hose->io_base_virt &&
125 address < (hose->io_base_virt + size)) {
130 spin_unlock(&hose_spinlock);
134 unsigned long pci_address_to_pio(phys_addr_t address)
136 struct pci_controller *hose;
137 resource_size_t size;
138 unsigned long ret = ~0;
140 spin_lock(&hose_spinlock);
141 list_for_each_entry(hose, &hose_list, list_node) {
142 size = pcibios_io_size(hose);
143 if (address >= hose->io_base_phys &&
144 address < (hose->io_base_phys + size)) {
146 (unsigned long)hose->io_base_virt - _IO_BASE;
147 ret = base + (address - hose->io_base_phys);
151 spin_unlock(&hose_spinlock);
155 EXPORT_SYMBOL_GPL(pci_address_to_pio);
158 * Return the domain number for this bus.
160 int pci_domain_nr(struct pci_bus *bus)
162 struct pci_controller *hose = pci_bus_to_host(bus);
164 return hose->global_number;
166 EXPORT_SYMBOL(pci_domain_nr);
168 /* This routine is meant to be used early during boot, when the
169 * PCI bus numbers have not yet been assigned, and you need to
170 * issue PCI config cycles to an OF device.
171 * It could also be used to "fix" RTAS config cycles if you want
172 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
175 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
178 struct pci_controller *hose, *tmp;
179 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
180 if (hose->dn == node)
187 static ssize_t pci_show_devspec(struct device *dev,
188 struct device_attribute *attr, char *buf)
190 struct pci_dev *pdev;
191 struct device_node *np;
193 pdev = to_pci_dev (dev);
194 np = pci_device_to_OF_node(pdev);
195 if (np == NULL || np->full_name == NULL)
197 return sprintf(buf, "%s", np->full_name);
199 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
201 /* Add sysfs properties */
202 int pcibios_add_platform_entries(struct pci_dev *pdev)
204 return device_create_file(&pdev->dev, &dev_attr_devspec);
207 char __devinit *pcibios_setup(char *str)
213 * Reads the interrupt pin to determine if interrupt is use by card.
214 * If the interrupt is used, then gets the interrupt line from the
215 * openfirmware and sets it in the pci_dev and pci_config line.
217 static int pci_read_irq_line(struct pci_dev *pci_dev)
222 /* The current device-tree that iSeries generates from the HV
223 * PCI informations doesn't contain proper interrupt routing,
224 * and all the fallback would do is print out crap, so we
225 * don't attempt to resolve the interrupts here at all, some
226 * iSeries specific fixup does it.
228 * In the long run, we will hopefully fix the generated device-tree
231 #ifdef CONFIG_PPC_ISERIES
232 if (firmware_has_feature(FW_FEATURE_ISERIES))
236 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
239 memset(&oirq, 0xff, sizeof(oirq));
241 /* Try to get a mapping from the device-tree */
242 if (of_irq_map_pci(pci_dev, &oirq)) {
245 /* If that fails, lets fallback to what is in the config
246 * space and map that through the default controller. We
247 * also set the type to level low since that's what PCI
248 * interrupts are. If your platform does differently, then
249 * either provide a proper interrupt tree or don't use this
252 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
256 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
257 line == 0xff || line == 0) {
260 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
263 virq = irq_create_mapping(NULL, line);
265 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
267 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
268 oirq.size, oirq.specifier[0], oirq.specifier[1],
269 oirq.controller ? oirq.controller->full_name :
272 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
276 pr_debug(" Failed to map !\n");
280 pr_debug(" Mapped to linux irq %d\n", virq);
288 * Platform support for /proc/bus/pci/X/Y mmap()s,
289 * modelled on the sparc64 implementation by Dave Miller.
294 * Adjust vm_pgoff of VMA such that it is the physical page offset
295 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
297 * Basically, the user finds the base address for his device which he wishes
298 * to mmap. They read the 32-bit value from the config space base register,
299 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
300 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
302 * Returns negative error code on failure, zero on success.
304 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
305 resource_size_t *offset,
306 enum pci_mmap_state mmap_state)
308 struct pci_controller *hose = pci_bus_to_host(dev->bus);
309 unsigned long io_offset = 0;
313 return NULL; /* should never happen */
315 /* If memory, add on the PCI bridge address offset */
316 if (mmap_state == pci_mmap_mem) {
317 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
318 *offset += hose->pci_mem_offset;
320 res_bit = IORESOURCE_MEM;
322 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
323 *offset += io_offset;
324 res_bit = IORESOURCE_IO;
328 * Check that the offset requested corresponds to one of the
329 * resources of the device.
331 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
332 struct resource *rp = &dev->resource[i];
333 int flags = rp->flags;
335 /* treat ROM as memory (should be already) */
336 if (i == PCI_ROM_RESOURCE)
337 flags |= IORESOURCE_MEM;
339 /* Active and same type? */
340 if ((flags & res_bit) == 0)
343 /* In the range of this resource? */
344 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
347 /* found it! construct the final physical address */
348 if (mmap_state == pci_mmap_io)
349 *offset += hose->io_base_phys - io_offset;
357 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
360 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
362 enum pci_mmap_state mmap_state,
365 unsigned long prot = pgprot_val(protection);
367 /* Write combine is always 0 on non-memory space mappings. On
368 * memory space, if the user didn't pass 1, we check for a
369 * "prefetchable" resource. This is a bit hackish, but we use
370 * this to workaround the inability of /sysfs to provide a write
373 if (mmap_state != pci_mmap_mem)
375 else if (write_combine == 0) {
376 if (rp->flags & IORESOURCE_PREFETCH)
380 /* XXX would be nice to have a way to ask for write-through */
382 return pgprot_noncached_wc(prot);
384 return pgprot_noncached(prot);
388 * This one is used by /dev/mem and fbdev who have no clue about the
389 * PCI device, it tries to find the PCI device first and calls the
392 pgprot_t pci_phys_mem_access_prot(struct file *file,
397 struct pci_dev *pdev = NULL;
398 struct resource *found = NULL;
399 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
402 if (page_is_ram(pfn))
405 prot = pgprot_noncached(prot);
406 for_each_pci_dev(pdev) {
407 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
408 struct resource *rp = &pdev->resource[i];
409 int flags = rp->flags;
411 /* Active and same type? */
412 if ((flags & IORESOURCE_MEM) == 0)
414 /* In the range of this resource? */
415 if (offset < (rp->start & PAGE_MASK) ||
425 if (found->flags & IORESOURCE_PREFETCH)
426 prot = pgprot_noncached_wc(prot);
430 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
431 (unsigned long long)offset, pgprot_val(prot));
438 * Perform the actual remap of the pages for a PCI device mapping, as
439 * appropriate for this architecture. The region in the process to map
440 * is described by vm_start and vm_end members of VMA, the base physical
441 * address is found in vm_pgoff.
442 * The pci device structure is provided so that architectures may make mapping
443 * decisions on a per-device or per-bus basis.
445 * Returns a negative error code on failure, zero on success.
447 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
448 enum pci_mmap_state mmap_state, int write_combine)
450 resource_size_t offset =
451 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
455 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
459 vma->vm_pgoff = offset >> PAGE_SHIFT;
460 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
462 mmap_state, write_combine);
464 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
465 vma->vm_end - vma->vm_start, vma->vm_page_prot);
470 /* This provides legacy IO read access on a bus */
471 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
473 unsigned long offset;
474 struct pci_controller *hose = pci_bus_to_host(bus);
475 struct resource *rp = &hose->io_resource;
478 /* Check if port can be supported by that bus. We only check
479 * the ranges of the PHB though, not the bus itself as the rules
480 * for forwarding legacy cycles down bridges are not our problem
481 * here. So if the host bridge supports it, we do it.
483 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
486 if (!(rp->flags & IORESOURCE_IO))
488 if (offset < rp->start || (offset + size) > rp->end)
490 addr = hose->io_base_virt + port;
494 *((u8 *)val) = in_8(addr);
499 *((u16 *)val) = in_le16(addr);
504 *((u32 *)val) = in_le32(addr);
510 /* This provides legacy IO write access on a bus */
511 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
513 unsigned long offset;
514 struct pci_controller *hose = pci_bus_to_host(bus);
515 struct resource *rp = &hose->io_resource;
518 /* Check if port can be supported by that bus. We only check
519 * the ranges of the PHB though, not the bus itself as the rules
520 * for forwarding legacy cycles down bridges are not our problem
521 * here. So if the host bridge supports it, we do it.
523 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
526 if (!(rp->flags & IORESOURCE_IO))
528 if (offset < rp->start || (offset + size) > rp->end)
530 addr = hose->io_base_virt + port;
532 /* WARNING: The generic code is idiotic. It gets passed a pointer
533 * to what can be a 1, 2 or 4 byte quantity and always reads that
534 * as a u32, which means that we have to correct the location of
535 * the data read within those 32 bits for size 1 and 2
539 out_8(addr, val >> 24);
544 out_le16(addr, val >> 16);
555 /* This provides legacy IO or memory mmap access on a bus */
556 int pci_mmap_legacy_page_range(struct pci_bus *bus,
557 struct vm_area_struct *vma,
558 enum pci_mmap_state mmap_state)
560 struct pci_controller *hose = pci_bus_to_host(bus);
561 resource_size_t offset =
562 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
563 resource_size_t size = vma->vm_end - vma->vm_start;
566 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
567 pci_domain_nr(bus), bus->number,
568 mmap_state == pci_mmap_mem ? "MEM" : "IO",
569 (unsigned long long)offset,
570 (unsigned long long)(offset + size - 1));
572 if (mmap_state == pci_mmap_mem) {
575 * Because X is lame and can fail starting if it gets an error trying
576 * to mmap legacy_mem (instead of just moving on without legacy memory
577 * access) we fake it here by giving it anonymous memory, effectively
578 * behaving just like /dev/zero
580 if ((offset + size) > hose->isa_mem_size) {
582 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
583 current->comm, current->pid, pci_domain_nr(bus), bus->number);
584 if (vma->vm_flags & VM_SHARED)
585 return shmem_zero_setup(vma);
588 offset += hose->isa_mem_phys;
590 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
591 unsigned long roffset = offset + io_offset;
592 rp = &hose->io_resource;
593 if (!(rp->flags & IORESOURCE_IO))
595 if (roffset < rp->start || (roffset + size) > rp->end)
597 offset += hose->io_base_phys;
599 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
601 vma->vm_pgoff = offset >> PAGE_SHIFT;
602 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
603 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
604 vma->vm_end - vma->vm_start,
608 void pci_resource_to_user(const struct pci_dev *dev, int bar,
609 const struct resource *rsrc,
610 resource_size_t *start, resource_size_t *end)
612 struct pci_controller *hose = pci_bus_to_host(dev->bus);
613 resource_size_t offset = 0;
618 if (rsrc->flags & IORESOURCE_IO)
619 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
621 /* We pass a fully fixed up address to userland for MMIO instead of
622 * a BAR value because X is lame and expects to be able to use that
623 * to pass to /dev/mem !
625 * That means that we'll have potentially 64 bits values where some
626 * userland apps only expect 32 (like X itself since it thinks only
627 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
630 * Hopefully, the sysfs insterface is immune to that gunk. Once X
631 * has been fixed (and the fix spread enough), we can re-enable the
632 * 2 lines below and pass down a BAR value to userland. In that case
633 * we'll also have to re-enable the matching code in
634 * __pci_mmap_make_offset().
639 else if (rsrc->flags & IORESOURCE_MEM)
640 offset = hose->pci_mem_offset;
643 *start = rsrc->start - offset;
644 *end = rsrc->end - offset;
648 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
649 * @hose: newly allocated pci_controller to be setup
650 * @dev: device node of the host bridge
651 * @primary: set if primary bus (32 bits only, soon to be deprecated)
653 * This function will parse the "ranges" property of a PCI host bridge device
654 * node and setup the resource mapping of a pci controller based on its
657 * Life would be boring if it wasn't for a few issues that we have to deal
660 * - We can only cope with one IO space range and up to 3 Memory space
661 * ranges. However, some machines (thanks Apple !) tend to split their
662 * space into lots of small contiguous ranges. So we have to coalesce.
664 * - We can only cope with all memory ranges having the same offset
665 * between CPU addresses and PCI addresses. Unfortunately, some bridges
666 * are setup for a large 1:1 mapping along with a small "window" which
667 * maps PCI address 0 to some arbitrary high address of the CPU space in
668 * order to give access to the ISA memory hole.
669 * The way out of here that I've chosen for now is to always set the
670 * offset based on the first resource found, then override it if we
671 * have a different offset and the previous was set by an ISA hole.
673 * - Some busses have IO space not starting at 0, which causes trouble with
674 * the way we do our IO resource renumbering. The code somewhat deals with
675 * it for 64 bits but I would expect problems on 32 bits.
677 * - Some 32 bits platforms such as 4xx can have physical space larger than
678 * 32 bits so we need to use 64 bits values for the parsing
680 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
681 struct device_node *dev,
686 int pna = of_n_addr_cells(dev);
688 int memno = 0, isa_hole = -1;
690 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
691 unsigned long long isa_mb = 0;
692 struct resource *res;
694 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
695 dev->full_name, primary ? "(primary)" : "");
697 /* Get ranges property */
698 ranges = of_get_property(dev, "ranges", &rlen);
703 while ((rlen -= np * 4) >= 0) {
704 /* Read next ranges element */
705 pci_space = ranges[0];
706 pci_addr = of_read_number(ranges + 1, 2);
707 cpu_addr = of_translate_address(dev, ranges + 3);
708 size = of_read_number(ranges + pna + 3, 2);
711 /* If we failed translation or got a zero-sized region
712 * (some FW try to feed us with non sensical zero sized regions
713 * such as power3 which look like some kind of attempt at exposing
714 * the VGA memory hole)
716 if (cpu_addr == OF_BAD_ADDR || size == 0)
719 /* Now consume following elements while they are contiguous */
720 for (; rlen >= np * sizeof(u32);
721 ranges += np, rlen -= np * 4) {
722 if (ranges[0] != pci_space)
724 pci_next = of_read_number(ranges + 1, 2);
725 cpu_next = of_translate_address(dev, ranges + 3);
726 if (pci_next != pci_addr + size ||
727 cpu_next != cpu_addr + size)
729 size += of_read_number(ranges + pna + 3, 2);
732 /* Act based on address space type */
734 switch ((pci_space >> 24) & 0x3) {
735 case 1: /* PCI IO space */
737 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
738 cpu_addr, cpu_addr + size - 1, pci_addr);
740 /* We support only one IO range */
741 if (hose->pci_io_size) {
743 " \\--> Skipped (too many) !\n");
747 /* On 32 bits, limit I/O space to 16MB */
748 if (size > 0x01000000)
751 /* 32 bits needs to map IOs here */
752 hose->io_base_virt = ioremap(cpu_addr, size);
754 /* Expect trouble if pci_addr is not 0 */
757 (unsigned long)hose->io_base_virt;
758 #endif /* CONFIG_PPC32 */
759 /* pci_io_size and io_base_phys always represent IO
760 * space starting at 0 so we factor in pci_addr
762 hose->pci_io_size = pci_addr + size;
763 hose->io_base_phys = cpu_addr - pci_addr;
766 res = &hose->io_resource;
767 res->flags = IORESOURCE_IO;
768 res->start = pci_addr;
770 case 2: /* PCI Memory space */
771 case 3: /* PCI 64 bits Memory space */
773 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
774 cpu_addr, cpu_addr + size - 1, pci_addr,
775 (pci_space & 0x40000000) ? "Prefetch" : "");
777 /* We support only 3 memory ranges */
780 " \\--> Skipped (too many) !\n");
783 /* Handles ISA memory hole space here */
787 if (primary || isa_mem_base == 0)
788 isa_mem_base = cpu_addr;
789 hose->isa_mem_phys = cpu_addr;
790 hose->isa_mem_size = size;
793 /* We get the PCI/Mem offset from the first range or
794 * the, current one if the offset came from an ISA
795 * hole. If they don't match, bugger.
798 (isa_hole >= 0 && pci_addr != 0 &&
799 hose->pci_mem_offset == isa_mb))
800 hose->pci_mem_offset = cpu_addr - pci_addr;
801 else if (pci_addr != 0 &&
802 hose->pci_mem_offset != cpu_addr - pci_addr) {
804 " \\--> Skipped (offset mismatch) !\n");
809 res = &hose->mem_resources[memno++];
810 res->flags = IORESOURCE_MEM;
811 if (pci_space & 0x40000000)
812 res->flags |= IORESOURCE_PREFETCH;
813 res->start = cpu_addr;
817 res->name = dev->full_name;
818 res->end = res->start + size - 1;
825 /* If there's an ISA hole and the pci_mem_offset is -not- matching
826 * the ISA hole offset, then we need to remove the ISA hole from
827 * the resource list for that brige
829 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
830 unsigned int next = isa_hole + 1;
831 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb);
833 memmove(&hose->mem_resources[isa_hole],
834 &hose->mem_resources[next],
835 sizeof(struct resource) * (memno - next));
836 hose->mem_resources[--memno].flags = 0;
840 /* Decide whether to display the domain number in /proc */
841 int pci_proc_domain(struct pci_bus *bus)
843 struct pci_controller *hose = pci_bus_to_host(bus);
845 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
847 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
848 return hose->global_number != 0;
852 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
853 struct resource *res)
855 resource_size_t offset = 0, mask = (resource_size_t)-1;
856 struct pci_controller *hose = pci_bus_to_host(dev->bus);
860 if (res->flags & IORESOURCE_IO) {
861 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
863 } else if (res->flags & IORESOURCE_MEM)
864 offset = hose->pci_mem_offset;
866 region->start = (res->start - offset) & mask;
867 region->end = (res->end - offset) & mask;
869 EXPORT_SYMBOL(pcibios_resource_to_bus);
871 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
872 struct pci_bus_region *region)
874 resource_size_t offset = 0, mask = (resource_size_t)-1;
875 struct pci_controller *hose = pci_bus_to_host(dev->bus);
879 if (res->flags & IORESOURCE_IO) {
880 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
882 } else if (res->flags & IORESOURCE_MEM)
883 offset = hose->pci_mem_offset;
884 res->start = (region->start + offset) & mask;
885 res->end = (region->end + offset) & mask;
887 EXPORT_SYMBOL(pcibios_bus_to_resource);
889 /* Fixup a bus resource into a linux resource */
890 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
892 struct pci_controller *hose = pci_bus_to_host(dev->bus);
893 resource_size_t offset = 0, mask = (resource_size_t)-1;
895 if (res->flags & IORESOURCE_IO) {
896 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
898 } else if (res->flags & IORESOURCE_MEM)
899 offset = hose->pci_mem_offset;
901 res->start = (res->start + offset) & mask;
902 res->end = (res->end + offset) & mask;
906 /* This header fixup will do the resource fixup for all devices as they are
907 * probed, but not for bridge ranges
909 static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
911 struct pci_controller *hose = pci_bus_to_host(dev->bus);
915 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
919 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
920 struct resource *res = dev->resource + i;
924 /* If we're going to re-assign everything, we mark all resources
925 * as unset (and 0-base them). In addition, we mark BARs starting
926 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
927 * since in that case, we don't want to re-assign anything
929 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
930 (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
931 /* Only print message if not re-assigning */
932 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
933 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
936 (unsigned long long)res->start,
937 (unsigned long long)res->end,
938 (unsigned int)res->flags);
939 res->end -= res->start;
941 res->flags |= IORESOURCE_UNSET;
945 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
947 (unsigned long long)res->start,\
948 (unsigned long long)res->end,
949 (unsigned int)res->flags);
951 fixup_resource(res, dev);
953 pr_debug("PCI:%s %016llx-%016llx\n",
955 (unsigned long long)res->start,
956 (unsigned long long)res->end);
959 /* Call machine specific resource fixup */
960 if (ppc_md.pcibios_fixup_resources)
961 ppc_md.pcibios_fixup_resources(dev);
963 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
965 /* This function tries to figure out if a bridge resource has been initialized
966 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
967 * things go more smoothly when it gets it right. It should covers cases such
968 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
970 static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
971 struct resource *res)
973 struct pci_controller *hose = pci_bus_to_host(bus);
974 struct pci_dev *dev = bus->self;
975 resource_size_t offset;
979 /* We don't do anything if PCI_PROBE_ONLY is set */
980 if (pci_has_flag(PCI_PROBE_ONLY))
983 /* Job is a bit different between memory and IO */
984 if (res->flags & IORESOURCE_MEM) {
985 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been
986 * initialized by somebody
988 if (res->start != hose->pci_mem_offset)
991 /* The BAR is 0, let's check if memory decoding is enabled on
992 * the bridge. If not, we consider it unassigned
994 pci_read_config_word(dev, PCI_COMMAND, &command);
995 if ((command & PCI_COMMAND_MEMORY) == 0)
998 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
999 * resources covers that starting address (0 then it's good enough for
1002 for (i = 0; i < 3; i++) {
1003 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
1004 hose->mem_resources[i].start == hose->pci_mem_offset)
1008 /* Well, it starts at 0 and we know it will collide so we may as
1009 * well consider it as unassigned. That covers the Apple case.
1013 /* If the BAR is non-0, then we consider it assigned */
1014 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1015 if (((res->start - offset) & 0xfffffffful) != 0)
1018 /* Here, we are a bit different than memory as typically IO space
1019 * starting at low addresses -is- valid. What we do instead if that
1020 * we consider as unassigned anything that doesn't have IO enabled
1021 * in the PCI command register, and that's it.
1023 pci_read_config_word(dev, PCI_COMMAND, &command);
1024 if (command & PCI_COMMAND_IO)
1027 /* It's starting at 0 and IO is disabled in the bridge, consider
1034 /* Fixup resources of a PCI<->PCI bridge */
1035 static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
1037 struct resource *res;
1040 struct pci_dev *dev = bus->self;
1042 pci_bus_for_each_resource(bus, res, i) {
1043 if (!res || !res->flags)
1045 if (i >= 3 && bus->self->transparent)
1048 /* If we are going to re-assign everything, mark the resource
1049 * as unset and move it down to 0
1051 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1052 res->flags |= IORESOURCE_UNSET;
1053 res->end -= res->start;
1058 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1060 (unsigned long long)res->start,\
1061 (unsigned long long)res->end,
1062 (unsigned int)res->flags);
1065 fixup_resource(res, dev);
1067 /* Try to detect uninitialized P2P bridge resources,
1068 * and clear them out so they get re-assigned later
1070 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1072 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
1075 pr_debug("PCI:%s %016llx-%016llx\n",
1077 (unsigned long long)res->start,
1078 (unsigned long long)res->end);
1083 void __devinit pcibios_setup_bus_self(struct pci_bus *bus)
1085 /* Fix up the bus resources for P2P bridges */
1086 if (bus->self != NULL)
1087 pcibios_fixup_bridge(bus);
1089 /* Platform specific bus fixups. This is currently only used
1090 * by fsl_pci and I'm hoping to get rid of it at some point
1092 if (ppc_md.pcibios_fixup_bus)
1093 ppc_md.pcibios_fixup_bus(bus);
1095 /* Setup bus DMA mappings */
1096 if (ppc_md.pci_dma_bus_setup)
1097 ppc_md.pci_dma_bus_setup(bus);
1100 void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
1102 struct pci_dev *dev;
1104 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1105 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1107 list_for_each_entry(dev, &bus->devices, bus_list) {
1108 /* Cardbus can call us to add new devices to a bus, so ignore
1109 * those who are already fully discovered
1114 /* Fixup NUMA node as it may not be setup yet by the generic
1115 * code and is needed by the DMA init
1117 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1119 /* Hook up default DMA ops */
1120 set_dma_ops(&dev->dev, pci_dma_ops);
1121 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
1123 /* Additional platform DMA/iommu setup */
1124 if (ppc_md.pci_dma_dev_setup)
1125 ppc_md.pci_dma_dev_setup(dev);
1127 /* Read default IRQs and fixup if necessary */
1128 pci_read_irq_line(dev);
1129 if (ppc_md.pci_irq_fixup)
1130 ppc_md.pci_irq_fixup(dev);
1134 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1136 /* When called from the generic PCI probe, read PCI<->PCI bridge
1137 * bases. This is -not- called when generating the PCI tree from
1138 * the OF device-tree.
1140 if (bus->self != NULL)
1141 pci_read_bridge_bases(bus);
1143 /* Now fixup the bus bus */
1144 pcibios_setup_bus_self(bus);
1146 /* Now fixup devices on that bus */
1147 pcibios_setup_bus_devices(bus);
1149 EXPORT_SYMBOL(pcibios_fixup_bus);
1151 void __devinit pci_fixup_cardbus(struct pci_bus *bus)
1153 /* Now fixup devices on that bus */
1154 pcibios_setup_bus_devices(bus);
1158 static int skip_isa_ioresource_align(struct pci_dev *dev)
1160 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1161 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1167 * We need to avoid collisions with `mirrored' VGA ports
1168 * and other strange ISA hardware, so we always want the
1169 * addresses to be allocated in the 0x000-0x0ff region
1172 * Why? Because some silly external IO cards only decode
1173 * the low 10 bits of the IO address. The 0x00-0xff region
1174 * is reserved for motherboard devices that decode all 16
1175 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1176 * but we want to try to avoid allocating at 0x2900-0x2bff
1177 * which might have be mirrored at 0x0100-0x03ff..
1179 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1180 resource_size_t size, resource_size_t align)
1182 struct pci_dev *dev = data;
1183 resource_size_t start = res->start;
1185 if (res->flags & IORESOURCE_IO) {
1186 if (skip_isa_ioresource_align(dev))
1189 start = (start + 0x3ff) & ~0x3ff;
1194 EXPORT_SYMBOL(pcibios_align_resource);
1197 * Reparent resource children of pr that conflict with res
1198 * under res, and make res replace those children.
1200 static int reparent_resources(struct resource *parent,
1201 struct resource *res)
1203 struct resource *p, **pp;
1204 struct resource **firstpp = NULL;
1206 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1207 if (p->end < res->start)
1209 if (res->end < p->start)
1211 if (p->start < res->start || p->end > res->end)
1212 return -1; /* not completely contained */
1213 if (firstpp == NULL)
1216 if (firstpp == NULL)
1217 return -1; /* didn't find any conflicting entries? */
1218 res->parent = parent;
1219 res->child = *firstpp;
1223 for (p = res->child; p != NULL; p = p->sibling) {
1225 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1227 (unsigned long long)p->start,
1228 (unsigned long long)p->end, res->name);
1234 * Handle resources of PCI devices. If the world were perfect, we could
1235 * just allocate all the resource regions and do nothing more. It isn't.
1236 * On the other hand, we cannot just re-allocate all devices, as it would
1237 * require us to know lots of host bridge internals. So we attempt to
1238 * keep as much of the original configuration as possible, but tweak it
1239 * when it's found to be wrong.
1241 * Known BIOS problems we have to work around:
1242 * - I/O or memory regions not configured
1243 * - regions configured, but not enabled in the command register
1244 * - bogus I/O addresses above 64K used
1245 * - expansion ROMs left enabled (this may sound harmless, but given
1246 * the fact the PCI specs explicitly allow address decoders to be
1247 * shared between expansion ROMs and other resource regions, it's
1248 * at least dangerous)
1251 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1252 * This gives us fixed barriers on where we can allocate.
1253 * (2) Allocate resources for all enabled devices. If there is
1254 * a collision, just mark the resource as unallocated. Also
1255 * disable expansion ROMs during this step.
1256 * (3) Try to allocate resources for disabled devices. If the
1257 * resources were assigned correctly, everything goes well,
1258 * if they weren't, they won't disturb allocation of other
1260 * (4) Assign new addresses to resources which were either
1261 * not configured at all or misconfigured. If explicitly
1262 * requested by the user, configure expansion ROM address
1266 void pcibios_allocate_bus_resources(struct pci_bus *bus)
1270 struct resource *res, *pr;
1272 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1273 pci_domain_nr(bus), bus->number);
1275 pci_bus_for_each_resource(bus, res, i) {
1276 if (!res || !res->flags || res->start > res->end || res->parent)
1279 /* If the resource was left unset at this point, we clear it */
1280 if (res->flags & IORESOURCE_UNSET)
1281 goto clear_resource;
1283 if (bus->parent == NULL)
1284 pr = (res->flags & IORESOURCE_IO) ?
1285 &ioport_resource : &iomem_resource;
1287 pr = pci_find_parent_resource(bus->self, res);
1289 /* this happens when the generic PCI
1290 * code (wrongly) decides that this
1291 * bridge is transparent -- paulus
1297 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1298 "[0x%x], parent %p (%s)\n",
1299 bus->self ? pci_name(bus->self) : "PHB",
1301 (unsigned long long)res->start,
1302 (unsigned long long)res->end,
1303 (unsigned int)res->flags,
1304 pr, (pr && pr->name) ? pr->name : "nil");
1306 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1307 if (request_resource(pr, res) == 0)
1310 * Must be a conflict with an existing entry.
1311 * Move that entry (or entries) under the
1312 * bridge resource and try again.
1314 if (reparent_resources(pr, res) == 0)
1317 pr_warning("PCI: Cannot allocate resource region "
1318 "%d of PCI bridge %d, will remap\n", i, bus->number);
1320 res->start = res->end = 0;
1324 list_for_each_entry(b, &bus->children, node)
1325 pcibios_allocate_bus_resources(b);
1328 static inline void __devinit alloc_resource(struct pci_dev *dev, int idx)
1330 struct resource *pr, *r = &dev->resource[idx];
1332 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1334 (unsigned long long)r->start,
1335 (unsigned long long)r->end,
1336 (unsigned int)r->flags);
1338 pr = pci_find_parent_resource(dev, r);
1339 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1340 request_resource(pr, r) < 0) {
1341 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1342 " of device %s, will remap\n", idx, pci_name(dev));
1344 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1346 (unsigned long long)pr->start,
1347 (unsigned long long)pr->end,
1348 (unsigned int)pr->flags);
1349 /* We'll assign a new address later */
1350 r->flags |= IORESOURCE_UNSET;
1356 static void __init pcibios_allocate_resources(int pass)
1358 struct pci_dev *dev = NULL;
1363 for_each_pci_dev(dev) {
1364 pci_read_config_word(dev, PCI_COMMAND, &command);
1365 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1366 r = &dev->resource[idx];
1367 if (r->parent) /* Already allocated */
1369 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1370 continue; /* Not assigned at all */
1371 /* We only allocate ROMs on pass 1 just in case they
1372 * have been screwed up by firmware
1374 if (idx == PCI_ROM_RESOURCE )
1376 if (r->flags & IORESOURCE_IO)
1377 disabled = !(command & PCI_COMMAND_IO);
1379 disabled = !(command & PCI_COMMAND_MEMORY);
1380 if (pass == disabled)
1381 alloc_resource(dev, idx);
1385 r = &dev->resource[PCI_ROM_RESOURCE];
1387 /* Turn the ROM off, leave the resource region,
1388 * but keep it unregistered.
1391 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1392 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1393 pr_debug("PCI: Switching off ROM of %s\n",
1395 r->flags &= ~IORESOURCE_ROM_ENABLE;
1396 pci_write_config_dword(dev, dev->rom_base_reg,
1397 reg & ~PCI_ROM_ADDRESS_ENABLE);
1403 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1405 struct pci_controller *hose = pci_bus_to_host(bus);
1406 resource_size_t offset;
1407 struct resource *res, *pres;
1410 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1413 if (!(hose->io_resource.flags & IORESOURCE_IO))
1415 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1416 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1417 BUG_ON(res == NULL);
1418 res->name = "Legacy IO";
1419 res->flags = IORESOURCE_IO;
1420 res->start = offset;
1421 res->end = (offset + 0xfff) & 0xfffffffful;
1422 pr_debug("Candidate legacy IO: %pR\n", res);
1423 if (request_resource(&hose->io_resource, res)) {
1425 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1426 pci_domain_nr(bus), bus->number, res);
1431 /* Check for memory */
1432 offset = hose->pci_mem_offset;
1433 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1434 for (i = 0; i < 3; i++) {
1435 pres = &hose->mem_resources[i];
1436 if (!(pres->flags & IORESOURCE_MEM))
1438 pr_debug("hose mem res: %pR\n", pres);
1439 if ((pres->start - offset) <= 0xa0000 &&
1440 (pres->end - offset) >= 0xbffff)
1445 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1446 BUG_ON(res == NULL);
1447 res->name = "Legacy VGA memory";
1448 res->flags = IORESOURCE_MEM;
1449 res->start = 0xa0000 + offset;
1450 res->end = 0xbffff + offset;
1451 pr_debug("Candidate VGA memory: %pR\n", res);
1452 if (request_resource(pres, res)) {
1454 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1455 pci_domain_nr(bus), bus->number, res);
1460 void __init pcibios_resource_survey(void)
1464 /* Allocate and assign resources */
1465 list_for_each_entry(b, &pci_root_buses, node)
1466 pcibios_allocate_bus_resources(b);
1467 pcibios_allocate_resources(0);
1468 pcibios_allocate_resources(1);
1470 /* Before we start assigning unassigned resource, we try to reserve
1471 * the low IO area and the VGA memory area if they intersect the
1472 * bus available resources to avoid allocating things on top of them
1474 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1475 list_for_each_entry(b, &pci_root_buses, node)
1476 pcibios_reserve_legacy_regions(b);
1479 /* Now, if the platform didn't decide to blindly trust the firmware,
1480 * we proceed to assigning things that were left unassigned
1482 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1483 pr_debug("PCI: Assigning unassigned resources...\n");
1484 pci_assign_unassigned_resources();
1487 /* Call machine dependent fixup */
1488 if (ppc_md.pcibios_fixup)
1489 ppc_md.pcibios_fixup();
1492 #ifdef CONFIG_HOTPLUG
1494 /* This is used by the PCI hotplug driver to allocate resource
1495 * of newly plugged busses. We can try to consolidate with the
1496 * rest of the code later, for now, keep it as-is as our main
1497 * resource allocation function doesn't deal with sub-trees yet.
1499 void pcibios_claim_one_bus(struct pci_bus *bus)
1501 struct pci_dev *dev;
1502 struct pci_bus *child_bus;
1504 list_for_each_entry(dev, &bus->devices, bus_list) {
1507 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1508 struct resource *r = &dev->resource[i];
1510 if (r->parent || !r->start || !r->flags)
1513 pr_debug("PCI: Claiming %s: "
1514 "Resource %d: %016llx..%016llx [%x]\n",
1516 (unsigned long long)r->start,
1517 (unsigned long long)r->end,
1518 (unsigned int)r->flags);
1520 pci_claim_resource(dev, i);
1524 list_for_each_entry(child_bus, &bus->children, node)
1525 pcibios_claim_one_bus(child_bus);
1529 /* pcibios_finish_adding_to_bus
1531 * This is to be called by the hotplug code after devices have been
1532 * added to a bus, this include calling it for a PHB that is just
1535 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1537 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1538 pci_domain_nr(bus), bus->number);
1540 /* Allocate bus and devices resources */
1541 pcibios_allocate_bus_resources(bus);
1542 pcibios_claim_one_bus(bus);
1544 /* Add new devices to global lists. Register in proc, sysfs. */
1545 pci_bus_add_devices(bus);
1548 eeh_add_device_tree_late(bus);
1550 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1552 #endif /* CONFIG_HOTPLUG */
1554 int pcibios_enable_device(struct pci_dev *dev, int mask)
1556 if (ppc_md.pcibios_enable_device_hook)
1557 if (ppc_md.pcibios_enable_device_hook(dev))
1560 return pci_enable_resources(dev, mask);
1563 void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
1565 struct pci_bus *bus = hose->bus;
1566 struct resource *res;
1569 /* Hookup PHB IO resource */
1570 bus->resource[0] = res = &hose->io_resource;
1573 printk(KERN_WARNING "PCI: I/O resource not set for host"
1574 " bridge %s (domain %d)\n",
1575 hose->dn->full_name, hose->global_number);
1577 /* Workaround for lack of IO resource only on 32-bit */
1578 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1579 res->end = res->start + IO_SPACE_LIMIT;
1580 res->flags = IORESOURCE_IO;
1581 #endif /* CONFIG_PPC32 */
1584 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1585 (unsigned long long)res->start,
1586 (unsigned long long)res->end,
1587 (unsigned long)res->flags);
1589 /* Hookup PHB Memory resources */
1590 for (i = 0; i < 3; ++i) {
1591 res = &hose->mem_resources[i];
1595 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1596 "host bridge %s (domain %d)\n",
1597 hose->dn->full_name, hose->global_number);
1599 /* Workaround for lack of MEM resource only on 32-bit */
1600 res->start = hose->pci_mem_offset;
1601 res->end = (resource_size_t)-1LL;
1602 res->flags = IORESOURCE_MEM;
1603 #endif /* CONFIG_PPC32 */
1605 bus->resource[i+1] = res;
1607 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i,
1608 (unsigned long long)res->start,
1609 (unsigned long long)res->end,
1610 (unsigned long)res->flags);
1613 pr_debug("PCI: PHB MEM offset = %016llx\n",
1614 (unsigned long long)hose->pci_mem_offset);
1615 pr_debug("PCI: PHB IO offset = %08lx\n",
1616 (unsigned long)hose->io_base_virt - _IO_BASE);
1621 * Null PCI config access functions, for the case when we can't
1624 #define NULL_PCI_OP(rw, size, type) \
1626 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1628 return PCIBIOS_DEVICE_NOT_FOUND; \
1632 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1635 return PCIBIOS_DEVICE_NOT_FOUND;
1639 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1642 return PCIBIOS_DEVICE_NOT_FOUND;
1645 static struct pci_ops null_pci_ops =
1647 .read = null_read_config,
1648 .write = null_write_config,
1652 * These functions are used early on before PCI scanning is done
1653 * and all of the pci_dev and pci_bus structures have been created.
1655 static struct pci_bus *
1656 fake_pci_bus(struct pci_controller *hose, int busnr)
1658 static struct pci_bus bus;
1661 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1665 bus.ops = hose? hose->ops: &null_pci_ops;
1669 #define EARLY_PCI_OP(rw, size, type) \
1670 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1671 int devfn, int offset, type value) \
1673 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1674 devfn, offset, value); \
1677 EARLY_PCI_OP(read, byte, u8 *)
1678 EARLY_PCI_OP(read, word, u16 *)
1679 EARLY_PCI_OP(read, dword, u32 *)
1680 EARLY_PCI_OP(write, byte, u8)
1681 EARLY_PCI_OP(write, word, u16)
1682 EARLY_PCI_OP(write, dword, u32)
1684 extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
1685 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1688 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1691 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1693 struct pci_controller *hose = bus->sysdata;
1695 return of_node_get(hose->dn);
1699 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1700 * @hose: Pointer to the PCI host controller instance structure
1702 void __devinit pcibios_scan_phb(struct pci_controller *hose)
1704 struct pci_bus *bus;
1705 struct device_node *node = hose->dn;
1708 pr_debug("PCI: Scanning PHB %s\n",
1709 node ? node->full_name : "<NO NAME>");
1711 /* Create an empty bus for the toplevel */
1712 bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, hose);
1714 pr_err("Failed to create bus for PCI domain %04x\n",
1715 hose->global_number);
1718 bus->secondary = hose->first_busno;
1721 /* Get some IO space for the new PHB */
1722 pcibios_setup_phb_io_space(hose);
1724 /* Wire up PHB bus resources */
1725 pcibios_setup_phb_resources(hose);
1727 /* Get probe mode and perform scan */
1728 mode = PCI_PROBE_NORMAL;
1729 if (node && ppc_md.pci_probe_mode)
1730 mode = ppc_md.pci_probe_mode(bus);
1731 pr_debug(" probe mode: %d\n", mode);
1732 if (mode == PCI_PROBE_DEVTREE) {
1733 bus->subordinate = hose->last_busno;
1734 of_scan_bus(node, bus);
1737 if (mode == PCI_PROBE_NORMAL)
1738 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
1740 /* Platform gets a chance to do some global fixups before
1741 * we proceed to resource allocation
1743 if (ppc_md.pcibios_fixup_phb)
1744 ppc_md.pcibios_fixup_phb(hose);
1746 /* Configure PCI Express settings */
1747 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1748 struct pci_bus *child;
1749 list_for_each_entry(child, &bus->children, node) {
1750 struct pci_dev *self = child->self;
1753 pcie_bus_configure_settings(child, self->pcie_mpss);
1758 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1760 int i, class = dev->class >> 8;
1761 /* When configured as agent, programing interface = 1 */
1762 int prog_if = dev->class & 0xf;
1764 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1765 class == PCI_CLASS_BRIDGE_OTHER) &&
1766 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1768 (dev->bus->parent == NULL)) {
1769 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1770 dev->resource[i].start = 0;
1771 dev->resource[i].end = 0;
1772 dev->resource[i].flags = 0;
1776 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1777 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);