2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
9 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
10 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
19 #include <linux/sys.h>
20 #include <asm/unistd.h>
21 #include <asm/errno.h>
24 #include <asm/cache.h>
25 #include <asm/cputable.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/processor.h>
31 #include <asm/kexec.h>
36 * This returns the high 64 bits of the product of two 64-bit numbers.
48 1: beqlr cr1 /* all done if high part of A is 0 */
63 * sub_reloc_offset(x) returns x - reloc_offset().
65 _GLOBAL(sub_reloc_offset)
77 * reloc_got2 runs through the .got2 section adding an offset
82 lis r7,__got2_start@ha
83 addi r7,r7,__got2_start@l
85 addi r8,r8,__got2_end@l
105 * call_setup_cpu - call the setup_cpu function for this cpu
106 * r3 = data offset, r24 = cpu number
108 * Setup function is called with:
110 * r4 = ptr to CPU spec (relocated)
112 _GLOBAL(call_setup_cpu)
113 addis r4,r3,cur_cpu_spec@ha
114 addi r4,r4,cur_cpu_spec@l
117 lwz r5,CPU_SPEC_SETUP(r4)
124 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
126 /* This gets called by via-pmu.c to switch the PLL selection
127 * on 750fx CPU. This function should really be moved to some
128 * other place (as most of the cpufreq code in via-pmu
130 _GLOBAL(low_choose_750fx_pll)
136 /* If switching to PLL1, disable HID0:BTIC */
147 /* Calc new HID1 value */
148 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
149 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
150 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
154 /* Store new HID1 image */
158 addis r6,r6,nap_save_hid1@ha
159 stw r4,nap_save_hid1@l(r6)
161 /* If switching to PLL0, enable HID0:BTIC */
176 _GLOBAL(low_choose_7447a_dfs)
182 /* Calc new HID1 value */
184 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
194 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
197 * complement mask on the msr then "or" some values on.
198 * _nmask_and_or_msr(nmask, value_to_or)
200 _GLOBAL(_nmask_and_or_msr)
201 mfmsr r0 /* Get current msr */
202 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
203 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
204 SYNC /* Some chip revs have problems here... */
205 mtmsr r0 /* Update machine state */
214 #if defined(CONFIG_40x)
215 sync /* Flush to memory before changing mapping */
217 isync /* Flush shadow TLB */
218 #elif defined(CONFIG_44x)
222 /* Load high watermark */
223 lis r4,tlb_44x_hwater@ha
224 lwz r5,tlb_44x_hwater@l(r4)
226 1: tlbwe r3,r3,PPC44x_TLB_PAGEID
232 #elif defined(CONFIG_FSL_BOOKE)
233 /* Invalidate all entries in TLB0 */
236 /* Invalidate all entries in TLB1 */
239 /* Invalidate all entries in TLB2 */
242 /* Invalidate all entries in TLB3 */
248 #endif /* CONFIG_SMP */
249 #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
250 #if defined(CONFIG_SMP)
256 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
257 rlwinm r0,r0,0,28,26 /* clear DR */
261 lis r9,mmu_hash_lock@h
262 ori r9,r9,mmu_hash_lock@l
274 stw r0,0(r9) /* clear mmu_hash_lock */
278 #else /* CONFIG_SMP */
282 #endif /* CONFIG_SMP */
283 #endif /* ! defined(CONFIG_40x) */
287 * Flush MMU TLB for a particular address
290 #if defined(CONFIG_40x)
294 /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
295 * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate
297 tlbwe r3, r3, TLB_TAG
300 #elif defined(CONFIG_44x)
302 mfspr r5,SPRN_PID /* Get PID */
303 rlwimi r4,r5,0,24,31 /* Set TID */
309 /* There are only 64 TLB entries, so r3 < 64,
310 * which means bit 22, is clear. Since 22 is
311 * the V bit in the TLB_PAGEID, loading this
312 * value will invalidate the TLB entry.
314 tlbwe r3, r3, PPC44x_TLB_PAGEID
317 #elif defined(CONFIG_FSL_BOOKE)
318 rlwinm r4, r3, 0, 0, 19
319 ori r5, r4, 0x08 /* TLBSEL = 1 */
320 ori r6, r4, 0x10 /* TLBSEL = 2 */
321 ori r7, r4, 0x18 /* TLBSEL = 3 */
327 #if defined(CONFIG_SMP)
329 #endif /* CONFIG_SMP */
330 #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
331 #if defined(CONFIG_SMP)
337 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
338 rlwinm r0,r0,0,28,26 /* clear DR */
342 lis r9,mmu_hash_lock@h
343 ori r9,r9,mmu_hash_lock@l
355 stw r0,0(r9) /* clear mmu_hash_lock */
359 #else /* CONFIG_SMP */
362 #endif /* CONFIG_SMP */
363 #endif /* ! CONFIG_40x */
367 * Flush instruction cache.
368 * This is a no-op on the 601.
370 _GLOBAL(flush_instruction_cache)
371 #if defined(CONFIG_8xx)
374 mtspr SPRN_IC_CST, r5
375 #elif defined(CONFIG_4xx)
387 #elif CONFIG_FSL_BOOKE
390 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
391 /* msync; isync recommended here */
395 END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
397 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
401 rlwinm r3,r3,16,16,31
403 beqlr /* for 601, do nothing */
404 /* 603/604 processor - use invalidate-all bit in HID0 */
408 #endif /* CONFIG_8xx/4xx */
413 * Write any modified data cache blocks out to memory
414 * and invalidate the corresponding instruction cache blocks.
415 * This is a no-op on the 601.
417 * flush_icache_range(unsigned long start, unsigned long stop)
419 _GLOBAL(__flush_icache_range)
421 blr /* for 601, do nothing */
422 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
423 li r5,L1_CACHE_BYTES-1
427 srwi. r4,r4,L1_CACHE_SHIFT
432 addi r3,r3,L1_CACHE_BYTES
434 sync /* wait for dcbst's to get to ram */
437 addi r6,r6,L1_CACHE_BYTES
439 sync /* additional sync needed on g4 */
443 * Write any modified data cache blocks out to memory.
444 * Does not invalidate the corresponding cache lines (especially for
445 * any corresponding instruction cache).
447 * clean_dcache_range(unsigned long start, unsigned long stop)
449 _GLOBAL(clean_dcache_range)
450 li r5,L1_CACHE_BYTES-1
454 srwi. r4,r4,L1_CACHE_SHIFT
459 addi r3,r3,L1_CACHE_BYTES
461 sync /* wait for dcbst's to get to ram */
465 * Write any modified data cache blocks out to memory and invalidate them.
466 * Does not invalidate the corresponding instruction cache blocks.
468 * flush_dcache_range(unsigned long start, unsigned long stop)
470 _GLOBAL(flush_dcache_range)
471 li r5,L1_CACHE_BYTES-1
475 srwi. r4,r4,L1_CACHE_SHIFT
480 addi r3,r3,L1_CACHE_BYTES
482 sync /* wait for dcbst's to get to ram */
486 * Like above, but invalidate the D-cache. This is used by the 8xx
487 * to invalidate the cache so the PPC core doesn't get stale data
488 * from the CPM (no cache snooping here :-).
490 * invalidate_dcache_range(unsigned long start, unsigned long stop)
492 _GLOBAL(invalidate_dcache_range)
493 li r5,L1_CACHE_BYTES-1
497 srwi. r4,r4,L1_CACHE_SHIFT
502 addi r3,r3,L1_CACHE_BYTES
504 sync /* wait for dcbi's to get to ram */
508 * Flush a particular page from the data cache to RAM.
509 * Note: this is necessary because the instruction cache does *not*
510 * snoop from the data cache.
511 * This is a no-op on the 601 which has a unified cache.
513 * void __flush_dcache_icache(void *page)
515 _GLOBAL(__flush_dcache_icache)
518 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
519 rlwinm r3,r3,0,0,19 /* Get page base address */
520 li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
523 0: dcbst 0,r3 /* Write line to ram */
524 addi r3,r3,L1_CACHE_BYTES
529 addi r6,r6,L1_CACHE_BYTES
536 * Flush a particular page from the data cache to RAM, identified
537 * by its physical address. We turn off the MMU so we can just use
538 * the physical address (this may be a highmem page without a kernel
541 * void __flush_dcache_icache_phys(unsigned long physaddr)
543 _GLOBAL(__flush_dcache_icache_phys)
545 blr /* for 601, do nothing */
546 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
548 rlwinm r0,r10,0,28,26 /* clear DR */
551 rlwinm r3,r3,0,0,19 /* Get page base address */
552 li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
555 0: dcbst 0,r3 /* Write line to ram */
556 addi r3,r3,L1_CACHE_BYTES
561 addi r6,r6,L1_CACHE_BYTES
564 mtmsr r10 /* restore DR */
569 * Clear pages using the dcbz instruction, which doesn't cause any
570 * memory traffic (except to write out any cache lines which get
571 * displaced). This only works on cacheable memory.
573 * void clear_pages(void *page, int order) ;
576 li r0,4096/L1_CACHE_BYTES
588 addi r3,r3,L1_CACHE_BYTES
593 * Copy a whole page. We use the dcbz instruction on the destination
594 * to reduce memory traffic (it eliminates the unnecessary reads of
595 * the destination into cache). This requires that the destination
598 #define COPY_16_BYTES \
613 /* don't use prefetch on 8xx */
614 li r0,4096/L1_CACHE_BYTES
620 #else /* not 8xx, we can prefetch */
623 #if MAX_COPY_PREFETCH > 1
624 li r0,MAX_COPY_PREFETCH
628 addi r11,r11,L1_CACHE_BYTES
630 #else /* MAX_COPY_PREFETCH == 1 */
632 li r11,L1_CACHE_BYTES+4
633 #endif /* MAX_COPY_PREFETCH */
634 li r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH
642 #if L1_CACHE_BYTES >= 32
644 #if L1_CACHE_BYTES >= 64
647 #if L1_CACHE_BYTES >= 128
657 crnot 4*cr0+eq,4*cr0+eq
658 li r0,MAX_COPY_PREFETCH
661 #endif /* CONFIG_8xx */
664 * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
665 * void atomic_set_mask(atomic_t mask, atomic_t *addr);
667 _GLOBAL(atomic_clear_mask)
674 _GLOBAL(atomic_set_mask)
683 * Extended precision shifts.
685 * Updated to be valid for shift counts from 0 to 63 inclusive.
688 * R3/R4 has 64 bit value
692 * ashrdi3: arithmetic right shift (sign propagation)
693 * lshrdi3: logical right shift
694 * ashldi3: left shift
698 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
699 addi r7,r5,32 # could be xori, or addi with -32
700 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
701 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
702 sraw r7,r3,r7 # t2 = MSW >> (count-32)
703 or r4,r4,r6 # LSW |= t1
704 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
705 sraw r3,r3,r5 # MSW = MSW >> count
706 or r4,r4,r7 # LSW |= t2
711 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
712 addi r7,r5,32 # could be xori, or addi with -32
713 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
714 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
715 or r3,r3,r6 # MSW |= t1
716 slw r4,r4,r5 # LSW = LSW << count
717 or r3,r3,r7 # MSW |= t2
722 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
723 addi r7,r5,32 # could be xori, or addi with -32
724 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
725 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
726 or r4,r4,r6 # LSW |= t1
727 srw r3,r3,r5 # MSW = MSW >> count
728 or r4,r4,r7 # LSW |= t2
738 * Create a kernel thread
739 * kernel_thread(fn, arg, flags)
741 _GLOBAL(kernel_thread)
745 mr r30,r3 /* function */
746 mr r31,r4 /* argument */
747 ori r3,r5,CLONE_VM /* flags */
748 oris r3,r3,CLONE_UNTRACED>>16
749 li r4,0 /* new sp (unused) */
752 cmpwi 0,r3,0 /* parent or child? */
753 bne 1f /* return if parent */
754 li r0,0 /* make top-level stack frame */
756 mtlr r30 /* fn addr in lr */
757 mr r3,r31 /* load arg and call fn */
760 li r0,__NR_exit /* exit if function returns */
768 _GLOBAL(kernel_execve)
776 * This routine is just here to keep GCC happy - sigh...
783 * Must be relocatable PIC code callable as a C function.
785 .globl relocate_new_kernel
788 /* r4 = reboot_code_buffer */
789 /* r5 = start_address */
794 * Set Machine Status Register to a known status,
795 * switch the MMU off and jump to 1: in a single step.
799 ori r8, r8, MSR_RI|MSR_ME
801 addi r8, r4, 1f - relocate_new_kernel
807 /* from this point address translation is turned off */
808 /* and interrupts are disabled */
810 /* set a new stack at the bottom of our page... */
811 /* (not really needed now) */
812 addi r1, r4, KEXEC_CONTROL_CODE_SIZE - 8 /* for LR Save+Back Chain */
816 li r6, 0 /* checksum */
820 0: /* top, read another word for the indirection page */
824 /* is it a destination page? (r8) */
825 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
828 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
831 2: /* is it an indirection page? (r3) */
832 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
835 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
839 2: /* are we done? */
840 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
844 2: /* is it a source page? (r9) */
845 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
848 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
855 lwzu r0, 4(r9) /* do the copy */
869 /* To be certain of avoiding problems with self-modifying code
870 * execute a serializing instruction here.
875 /* jump to the entry point, usually the setup routine */
881 relocate_new_kernel_end:
883 .globl relocate_new_kernel_size
884 relocate_new_kernel_size:
885 .long relocate_new_kernel_end - relocate_new_kernel