2 * This file contains the 64-bit "server" PowerPC variant
3 * of the low level exception handling including exception
4 * vectors, exception return, part of the slb and stab
5 * handling and other fixed offset specific things.
7 * This file is meant to be #included from head_64.S due to
8 * position dependent assembly.
10 * Most of this originates from head_64.S and thus has the same
15 #include <asm/exception-64s.h>
16 #include <asm/ptrace.h>
19 * We layout physical memory as follows:
20 * 0x0000 - 0x00ff : Secondary processor spin code
21 * 0x0100 - 0x2fff : pSeries Interrupt prologs
22 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
23 * 0x6000 - 0x6fff : Initial (CPU0) segment table
24 * 0x7000 - 0x7fff : FWNMI data area
25 * 0x8000 - : Early init and support code
29 * This is the start of the interrupt handlers for pSeries
30 * This code runs with relocation off.
31 * Code from here to __end_interrupts gets copied down to real
32 * address 0x100 when we are running a relocatable kernel.
33 * Therefore any relative branches in this section must only
34 * branch to labels in this section.
37 .globl __start_interrupts
40 STD_EXCEPTION_PSERIES(0x100, 0x100, system_reset)
43 _machine_check_pSeries:
47 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common, EXC_STD)
50 .globl data_access_pSeries
57 std r9,PACA_EXSLB+EX_R9(r13)
58 std r10,PACA_EXSLB+EX_R10(r13)
65 beq do_stab_bolted_pSeries
66 ld r10,PACA_EXSLB+EX_R10(r13)
67 std r11,PACA_EXGEN+EX_R11(r13)
68 ld r11,PACA_EXSLB+EX_R9(r13)
69 std r12,PACA_EXGEN+EX_R12(r13)
71 std r10,PACA_EXGEN+EX_R10(r13)
72 std r11,PACA_EXGEN+EX_R9(r13)
73 std r12,PACA_EXGEN+EX_R13(r13)
74 EXCEPTION_PROLOG_PSERIES_1(data_access_common, EXC_STD)
76 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common, EXC_STD)
77 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
80 .globl data_access_slb_pSeries
81 data_access_slb_pSeries:
86 std r3,PACA_EXSLB+EX_R3(r13)
88 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
91 /* Keep that around for when we re-implement dynamic VSIDs */
93 bge slb_miss_user_pseries
94 #endif /* __DISABLED__ */
95 std r10,PACA_EXSLB+EX_R10(r13)
96 std r11,PACA_EXSLB+EX_R11(r13)
97 std r12,PACA_EXSLB+EX_R12(r13)
99 std r10,PACA_EXSLB+EX_R13(r13)
100 mfspr r12,SPRN_SRR1 /* and SRR1 */
101 #ifndef CONFIG_RELOCATABLE
105 * We can't just use a direct branch to .slb_miss_realmode
106 * because the distance from here to there depends on where
107 * the kernel ends up being put.
110 ld r10,PACAKBASE(r13)
111 LOAD_HANDLER(r10, .slb_miss_realmode)
116 STD_EXCEPTION_PSERIES(0x400, 0x400, instruction_access)
119 .globl instruction_access_slb_pSeries
120 instruction_access_slb_pSeries:
125 std r3,PACA_EXSLB+EX_R3(r13)
126 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
127 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
130 /* Keep that around for when we re-implement dynamic VSIDs */
132 bge slb_miss_user_pseries
133 #endif /* __DISABLED__ */
134 std r10,PACA_EXSLB+EX_R10(r13)
135 std r11,PACA_EXSLB+EX_R11(r13)
136 std r12,PACA_EXSLB+EX_R12(r13)
138 std r10,PACA_EXSLB+EX_R13(r13)
139 mfspr r12,SPRN_SRR1 /* and SRR1 */
140 #ifndef CONFIG_RELOCATABLE
144 ld r10,PACAKBASE(r13)
145 LOAD_HANDLER(r10, .slb_miss_realmode)
150 /* We open code these as we can't have a ". = x" (even with
151 * x = "." within a feature section
154 .globl hardware_interrupt_pSeries;
155 .globl hardware_interrupt_hv;
156 hardware_interrupt_pSeries:
157 hardware_interrupt_hv:
159 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt, EXC_STD)
161 _MASKABLE_EXCEPTION_PSERIES(0x502, hardware_interrupt, EXC_HV)
162 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_HVMODE_206)
164 STD_EXCEPTION_PSERIES(0x600, 0x600, alignment)
165 STD_EXCEPTION_PSERIES(0x700, 0x700, program_check)
166 STD_EXCEPTION_PSERIES(0x800, 0x800, fp_unavailable)
168 MASKABLE_EXCEPTION_PSERIES(0x900, 0x900, decrementer)
169 MASKABLE_EXCEPTION_HV(0x980, 0x980, decrementer)
171 STD_EXCEPTION_PSERIES(0xa00, 0xa00, trap_0a)
172 STD_EXCEPTION_PSERIES(0xb00, 0xb00, trap_0b)
175 .globl system_call_pSeries
182 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
186 ld r12,PACAKBASE(r13)
188 LOAD_HANDLER(r12, system_call_entry)
193 b . /* prevent speculative execution */
195 /* Fast LE/BE switch system call */
196 1: mfspr r12,SPRN_SRR1
199 rfid /* return to userspace */
202 STD_EXCEPTION_PSERIES(0xd00, 0xd00, single_step)
204 /* At 0xe??? we have a bunch of hypervisor exceptions, we branch
205 * out of line to handle them
212 b emulation_assist_hv
218 /* We need to deal with the Altivec unavailable exception
219 * here which is at 0xf20, thus in the middle of the
220 * prolog code of the PerformanceMonitor one. A little
221 * trickery is thus necessary
223 performance_monitor_pSeries_1:
225 b performance_monitor_pSeries
227 altivec_unavailable_pSeries_1:
229 b altivec_unavailable_pSeries
231 vsx_unavailable_pSeries_1:
233 b vsx_unavailable_pSeries
235 #ifdef CONFIG_CBE_RAS
236 STD_EXCEPTION_HV(0x1200, 0x1202, cbe_system_error)
237 #endif /* CONFIG_CBE_RAS */
238 STD_EXCEPTION_PSERIES(0x1300, 0x1300, instruction_breakpoint)
239 #ifdef CONFIG_CBE_RAS
240 STD_EXCEPTION_HV(0x1600, 0x1602, cbe_maintenance)
241 #endif /* CONFIG_CBE_RAS */
242 STD_EXCEPTION_PSERIES(0x1700, 0x1700, altivec_assist)
243 #ifdef CONFIG_CBE_RAS
244 STD_EXCEPTION_HV(0x1800, 0x1802, cbe_thermal)
245 #endif /* CONFIG_CBE_RAS */
249 /*** Out of line interrupts support ***/
251 /* moved from 0xe00 */
252 STD_EXCEPTION_HV(., 0xe00, h_data_storage)
253 STD_EXCEPTION_HV(., 0xe20, h_instr_storage)
254 STD_EXCEPTION_HV(., 0xe40, emulation_assist)
255 STD_EXCEPTION_HV(., 0xe60, hmi_exception) /* need to flush cache ? */
257 /* moved from 0xf00 */
258 STD_EXCEPTION_PSERIES(., 0xf00, performance_monitor)
259 STD_EXCEPTION_PSERIES(., 0xf20, altivec_unavailable)
260 STD_EXCEPTION_PSERIES(., 0xf40, vsx_unavailable)
263 * An interrupt came in while soft-disabled; clear EE in SRR1,
264 * clear paca->hard_enabled and return.
267 stb r10,PACAHARDIRQEN(r13)
269 ld r9,PACA_EXGEN+EX_R9(r13)
271 rldicl r10,r10,48,1 /* clear MSR_EE */
274 ld r10,PACA_EXGEN+EX_R10(r13)
280 stb r10,PACAHARDIRQEN(r13)
282 ld r9,PACA_EXGEN+EX_R9(r13)
284 rldicl r10,r10,48,1 /* clear MSR_EE */
287 ld r10,PACA_EXGEN+EX_R10(r13)
293 do_stab_bolted_pSeries:
294 std r11,PACA_EXSLB+EX_R11(r13)
295 std r12,PACA_EXSLB+EX_R12(r13)
297 std r10,PACA_EXSLB+EX_R13(r13)
298 EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted, EXC_STD)
300 #ifdef CONFIG_PPC_PSERIES
302 * Vectors for the FWNMI option. Share common code.
304 .globl system_reset_fwnmi
308 SET_SCRATCH0(r13) /* save r13 */
309 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD)
311 .globl machine_check_fwnmi
315 SET_SCRATCH0(r13) /* save r13 */
316 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common, EXC_STD)
318 #endif /* CONFIG_PPC_PSERIES */
322 * This is used for when the SLB miss handler has to go virtual,
323 * which doesn't happen for now anymore but will once we re-implement
324 * dynamic VSIDs for shared page tables
326 slb_miss_user_pseries:
327 std r10,PACA_EXGEN+EX_R10(r13)
328 std r11,PACA_EXGEN+EX_R11(r13)
329 std r12,PACA_EXGEN+EX_R12(r13)
331 ld r11,PACA_EXSLB+EX_R9(r13)
332 ld r12,PACA_EXSLB+EX_R3(r13)
333 std r10,PACA_EXGEN+EX_R13(r13)
334 std r11,PACA_EXGEN+EX_R9(r13)
335 std r12,PACA_EXGEN+EX_R3(r13)
338 mfspr r11,SRR0 /* save SRR0 */
339 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
340 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
342 mfspr r12,SRR1 /* and SRR1 */
345 b . /* prevent spec. execution */
346 #endif /* __DISABLED__ */
348 /* KVM's trampoline code needs to be close to the interrupt handlers */
350 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
351 #include "../kvm/book3s_rmhandlers.S"
355 .globl __end_interrupts
359 * Code from here down to __end_handlers is invoked from the
360 * exception prologs above. Because the prologs assemble the
361 * addresses of these handlers using the LOAD_HANDLER macro,
362 * which uses an addi instruction, these handlers must be in
363 * the first 32k of the kernel image.
366 /*** Common interrupt handlers ***/
368 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
371 * Machine check is different because we use a different
372 * save area: PACA_EXMC instead of PACA_EXGEN.
375 .globl machine_check_common
376 machine_check_common:
377 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
381 addi r3,r1,STACK_FRAME_OVERHEAD
382 bl .machine_check_exception
385 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
386 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
387 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
388 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
389 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
390 STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception)
391 STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception)
392 STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
393 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
394 #ifdef CONFIG_ALTIVEC
395 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
397 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
399 #ifdef CONFIG_CBE_RAS
400 STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
401 STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
402 STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
403 #endif /* CONFIG_CBE_RAS */
410 * Here we have detected that the kernel stack pointer is bad.
411 * R9 contains the saved CR, r13 points to the paca,
412 * r10 contains the (bad) kernel stack pointer,
413 * r11 and r12 contain the saved SRR0 and SRR1.
414 * We switch to using an emergency stack, save the registers there,
415 * and call kernel_bad_stack(), which panics.
418 ld r1,PACAEMERGSP(r13)
419 subi r1,r1,64+INT_FRAME_SIZE
440 lhz r12,PACA_TRAP_SAVE(r13)
442 addi r11,r1,INT_FRAME_SIZE
447 1: addi r3,r1,STACK_FRAME_OVERHEAD
452 * Here r13 points to the paca, r9 contains the saved CR,
453 * SRR0 and SRR1 are saved in r11 and r12,
454 * r9 - r13 are saved in paca->exgen.
457 .globl data_access_common
460 std r10,PACA_EXGEN+EX_DAR(r13)
462 stw r10,PACA_EXGEN+EX_DSISR(r13)
463 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
464 ld r3,PACA_EXGEN+EX_DAR(r13)
465 lwz r4,PACA_EXGEN+EX_DSISR(r13)
467 b .do_hash_page /* Try to handle as hpte fault */
470 .globl h_data_storage_common
471 h_data_storage_common:
473 std r10,PACA_EXGEN+EX_DAR(r13)
474 mfspr r10,SPRN_HDSISR
475 stw r10,PACA_EXGEN+EX_DSISR(r13)
476 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
478 addi r3,r1,STACK_FRAME_OVERHEAD
479 bl .unknown_exception
483 .globl instruction_access_common
484 instruction_access_common:
485 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
489 b .do_hash_page /* Try to handle as hpte fault */
491 STD_EXCEPTION_COMMON(0xe20, h_instr_storage, .unknown_exception)
494 * Here is the common SLB miss user that is used when going to virtual
495 * mode for SLB misses, that is currently not used
499 .globl slb_miss_user_common
500 slb_miss_user_common:
502 std r3,PACA_EXGEN+EX_DAR(r13)
503 stw r9,PACA_EXGEN+EX_CCR(r13)
504 std r10,PACA_EXGEN+EX_LR(r13)
505 std r11,PACA_EXGEN+EX_SRR0(r13)
506 bl .slb_allocate_user
508 ld r10,PACA_EXGEN+EX_LR(r13)
509 ld r3,PACA_EXGEN+EX_R3(r13)
510 lwz r9,PACA_EXGEN+EX_CCR(r13)
511 ld r11,PACA_EXGEN+EX_SRR0(r13)
515 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
516 beq- unrecov_user_slb
524 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
530 ld r9,PACA_EXGEN+EX_R9(r13)
531 ld r10,PACA_EXGEN+EX_R10(r13)
532 ld r11,PACA_EXGEN+EX_R11(r13)
533 ld r12,PACA_EXGEN+EX_R12(r13)
534 ld r13,PACA_EXGEN+EX_R13(r13)
539 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
540 ld r4,PACA_EXGEN+EX_DAR(r13)
547 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
550 1: addi r3,r1,STACK_FRAME_OVERHEAD
551 bl .unrecoverable_exception
554 #endif /* __DISABLED__ */
558 * r13 points to the PACA, r9 contains the saved CR,
559 * r12 contain the saved SRR1, SRR0 is still ready for return
560 * r3 has the faulting address
561 * r9 - r13 are saved in paca->exslb.
562 * r3 is saved in paca->slb_r3
563 * We assume we aren't going to take any exceptions during this procedure.
565 _GLOBAL(slb_miss_realmode)
567 #ifdef CONFIG_RELOCATABLE
571 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
572 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
574 bl .slb_allocate_realmode
576 /* All done -- return from exception. */
578 ld r10,PACA_EXSLB+EX_LR(r13)
579 ld r3,PACA_EXSLB+EX_R3(r13)
580 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
581 #ifdef CONFIG_PPC_ISERIES
583 ld r11,PACALPPACAPTR(r13)
584 ld r11,LPPACASRR0(r11) /* get SRR0 value */
585 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
586 #endif /* CONFIG_PPC_ISERIES */
590 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
596 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
599 #ifdef CONFIG_PPC_ISERIES
603 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
604 #endif /* CONFIG_PPC_ISERIES */
605 ld r9,PACA_EXSLB+EX_R9(r13)
606 ld r10,PACA_EXSLB+EX_R10(r13)
607 ld r11,PACA_EXSLB+EX_R11(r13)
608 ld r12,PACA_EXSLB+EX_R12(r13)
609 ld r13,PACA_EXSLB+EX_R13(r13)
611 b . /* prevent speculative execution */
614 #ifdef CONFIG_PPC_ISERIES
617 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
618 #endif /* CONFIG_PPC_ISERIES */
620 ld r10,PACAKBASE(r13)
621 LOAD_HANDLER(r10,unrecov_slb)
629 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
632 1: addi r3,r1,STACK_FRAME_OVERHEAD
633 bl .unrecoverable_exception
637 .globl hardware_interrupt_common
638 .globl hardware_interrupt_entry
639 hardware_interrupt_common:
640 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
642 hardware_interrupt_entry:
645 bl .ppc64_runlatch_on
646 END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
647 addi r3,r1,STACK_FRAME_OVERHEAD
649 b .ret_from_except_lite
651 #ifdef CONFIG_PPC_970_NAP
654 std r9,TI_LOCAL_FLAGS(r11)
655 ld r10,_LINK(r1) /* make idle task do the */
656 std r10,_NIP(r1) /* equivalent of a blr */
661 .globl alignment_common
664 std r10,PACA_EXGEN+EX_DAR(r13)
666 stw r10,PACA_EXGEN+EX_DSISR(r13)
667 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
668 ld r3,PACA_EXGEN+EX_DAR(r13)
669 lwz r4,PACA_EXGEN+EX_DSISR(r13)
673 addi r3,r1,STACK_FRAME_OVERHEAD
675 bl .alignment_exception
679 .globl program_check_common
680 program_check_common:
681 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
683 addi r3,r1,STACK_FRAME_OVERHEAD
685 bl .program_check_exception
689 .globl fp_unavailable_common
690 fp_unavailable_common:
691 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
692 bne 1f /* if from user, just load it up */
694 addi r3,r1,STACK_FRAME_OVERHEAD
696 bl .kernel_fp_unavailable_exception
699 b fast_exception_return
702 .globl altivec_unavailable_common
703 altivec_unavailable_common:
704 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
705 #ifdef CONFIG_ALTIVEC
709 b fast_exception_return
711 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
714 addi r3,r1,STACK_FRAME_OVERHEAD
716 bl .altivec_unavailable_exception
720 .globl vsx_unavailable_common
721 vsx_unavailable_common:
722 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
727 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
730 addi r3,r1,STACK_FRAME_OVERHEAD
732 bl .vsx_unavailable_exception
736 .globl __end_handlers
740 * Return from an exception with minimal checks.
741 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
742 * If interrupts have been enabled, or anything has been
743 * done that might have changed the scheduling status of
744 * any task or sent any task a signal, you should use
745 * ret_from_except or ret_from_except_lite instead of this.
747 fast_exc_return_irq: /* restores irq state too */
749 TRACE_AND_RESTORE_IRQ(r3);
751 rldicl r4,r12,49,63 /* get MSR_EE to LSB */
752 stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */
755 .globl fast_exception_return
756 fast_exception_return:
759 andi. r3,r12,MSR_RI /* check if RI is set */
762 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
765 ACCOUNT_CPU_USER_EXIT(r3, r4)
781 rldicl r10,r10,48,1 /* clear EE */
782 rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */
790 b . /* prevent speculative execution */
794 1: addi r3,r1,STACK_FRAME_OVERHEAD
795 bl .unrecoverable_exception
803 _STATIC(do_hash_page)
807 andis. r0,r4,0xa410 /* weird error? */
808 bne- handle_page_fault /* if not, try to insert a HPTE */
809 andis. r0,r4,DSISR_DABRMATCH@h
810 bne- handle_dabr_fault
813 andis. r0,r4,0x0020 /* Is it a segment table fault? */
814 bne- do_ste_alloc /* If so handle it */
815 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
817 clrrdi r11,r1,THREAD_SHIFT
818 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
819 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
820 bne 77f /* then don't call hash_page now */
823 * On iSeries, we soft-disable interrupts here, then
824 * hard-enable interrupts so that the hash_page code can spin on
825 * the hash_table_lock without problems on a shared processor.
830 * Currently, trace_hardirqs_off() will be called by DISABLE_INTS
831 * and will clobber volatile registers when irq tracing is enabled
832 * so we need to reload them. It may be possible to be smarter here
833 * and move the irq tracing elsewhere but let's keep it simple for
836 #ifdef CONFIG_TRACE_IRQFLAGS
842 #endif /* CONFIG_TRACE_IRQFLAGS */
844 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
845 * accessing a userspace segment (even from the kernel). We assume
846 * kernel addresses always have the high bit set.
848 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
849 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
850 orc r0,r12,r0 /* MSR_PR | ~high_bit */
851 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
852 ori r4,r4,1 /* add _PAGE_PRESENT */
853 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
856 * r3 contains the faulting address
857 * r4 contains the required access permissions
858 * r5 contains the trap number
860 * at return r3 = 0 for success
862 bl .hash_page /* build HPTE if possible */
863 cmpdi r3,0 /* see if hash_page succeeded */
867 * If we had interrupts soft-enabled at the point where the
868 * DSI/ISI occurred, and an interrupt came in during hash_page,
870 * We jump to ret_from_except_lite rather than fast_exception_return
871 * because ret_from_except_lite will check for and handle pending
872 * interrupts if necessary.
875 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
879 * Here we have interrupts hard-disabled, so it is sufficient
880 * to restore paca->{soft,hard}_enable and get out.
882 beq fast_exc_return_irq /* Return from exception on success */
883 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
885 /* For a hash failure, we don't bother re-enabling interrupts */
889 * hash_page couldn't handle it, set soft interrupt enable back
890 * to what it was before the trap. Note that .arch_local_irq_restore
891 * handles any interrupts pending at this point.
894 TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f)
895 bl .arch_local_irq_restore
898 /* We have a data breakpoint exception - handle it */
903 addi r3,r1,STACK_FRAME_OVERHEAD
905 b .ret_from_except_lite
907 /* Here we have a page fault that hash_page can't handle. */
912 addi r3,r1,STACK_FRAME_OVERHEAD
918 addi r3,r1,STACK_FRAME_OVERHEAD
923 13: b .ret_from_except_lite
925 /* We have a page fault that hash_page could handle but HV refused
930 addi r3,r1,STACK_FRAME_OVERHEAD
936 * We come here as a result of a DSI at a point where we don't want
937 * to call hash_page, such as when we are accessing memory (possibly
938 * user memory) inside a PMU interrupt that occurred while interrupts
939 * were soft-disabled. We want to invoke the exception handler for
940 * the access, or panic if there isn't a handler.
944 addi r3,r1,STACK_FRAME_OVERHEAD
949 /* here we have a segment miss */
951 bl .ste_allocate /* try to insert stab entry */
953 bne- handle_page_fault
954 b fast_exception_return
957 * r13 points to the PACA, r9 contains the saved CR,
958 * r11 and r12 contain the saved SRR0 and SRR1.
959 * r9 - r13 are saved in paca->exslb.
960 * We assume we aren't going to take any exceptions during this procedure.
961 * We assume (DAR >> 60) == 0xc.
964 _GLOBAL(do_stab_bolted)
965 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
966 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
968 /* Hash to the primary group */
969 ld r10,PACASTABVIRT(r13)
972 rldimi r10,r11,7,52 /* r10 = first ste of the group */
975 /* This is a kernel address, so protovsid = ESID */
976 ASM_VSID_SCRAMBLE(r11, r9, 256M)
977 rldic r9,r11,12,16 /* r9 = vsid << 12 */
979 /* Search the primary group for a free entry */
980 1: ld r11,0(r10) /* Test valid bit of the current ste */
987 /* Stick for only searching the primary group for now. */
988 /* At least for now, we use a very simple random castout scheme */
989 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
991 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
994 /* r10 currently points to an ste one past the group of interest */
995 /* make it point to the randomly selected entry */
997 or r10,r10,r11 /* r10 is the entry to invalidate */
999 isync /* mark the entry invalid */
1001 rldicl r11,r11,56,1 /* clear the valid bit */
1006 clrrdi r11,r11,28 /* Get the esid part of the ste */
1009 2: std r9,8(r10) /* Store the vsid part of the ste */
1012 mfspr r11,SPRN_DAR /* Get the new esid */
1013 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1014 ori r11,r11,0x90 /* Turn on valid and kp */
1015 std r11,0(r10) /* Put new entry back into the stab */
1019 /* All done -- return from exception. */
1020 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1021 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1023 andi. r10,r12,MSR_RI
1026 mtcrf 0x80,r9 /* restore CR */
1034 ld r9,PACA_EXSLB+EX_R9(r13)
1035 ld r10,PACA_EXSLB+EX_R10(r13)
1036 ld r11,PACA_EXSLB+EX_R11(r13)
1037 ld r12,PACA_EXSLB+EX_R12(r13)
1038 ld r13,PACA_EXSLB+EX_R13(r13)
1040 b . /* prevent speculative execution */
1042 #ifdef CONFIG_PPC_PSERIES
1044 * Data area reserved for FWNMI option.
1045 * This address (0x7000) is fixed by the RPA.
1048 .globl fwnmi_data_area
1050 #endif /* CONFIG_PPC_PSERIES */
1052 /* iSeries does not use the FWNMI stuff, so it is safe to put
1053 * this here, even if we later allow kernels that will boot on
1054 * both pSeries and iSeries */
1055 #ifdef CONFIG_PPC_ISERIES
1059 .quad HvEsidsToMap /* xNumberEsids */
1060 .quad HvRangesToMap /* xNumberRanges */
1061 .quad STAB0_PAGE /* xSegmentTableOffs */
1062 .zero 40 /* xRsvd */
1063 /* xEsids (HvEsidsToMap entries of 2 quads) */
1064 .quad PAGE_OFFSET_ESID /* xKernelEsid */
1065 .quad PAGE_OFFSET_VSID /* xKernelVsid */
1066 .quad VMALLOC_START_ESID /* xKernelEsid */
1067 .quad VMALLOC_START_VSID /* xKernelVsid */
1068 /* xRanges (HvRangesToMap entries of 3 quads) */
1069 .quad HvPagesToMap /* xPages */
1070 .quad 0 /* xOffset */
1071 .quad PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */
1073 #endif /* CONFIG_PPC_ISERIES */
1075 #ifdef CONFIG_PPC_PSERIES
1077 #endif /* CONFIG_PPC_PSERIES */
1080 * Space for CPU0's segment table.
1082 * On iSeries, the hypervisor must fill in at least one entry before
1083 * we get control (with relocate on). The address is given to the hv
1084 * as a page number (see xLparMap above), so this must be at a
1085 * fixed address (the linker can't compute (u64)&initial_stab >>
1088 . = STAB0_OFFSET /* 0x8000 */