3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/errno.h>
22 #include <asm/unistd.h>
23 #include <asm/processor.h>
26 #include <asm/thread_info.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/cputable.h>
30 #include <asm/firmware.h>
32 #include <asm/ptrace.h>
33 #include <asm/irqflags.h>
34 #include <asm/ftrace.h>
41 .tc .sys_call_table[TC],.sys_call_table
43 /* This value is used to mark exception frames on the stack. */
45 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
52 .globl system_call_common
56 addi r1,r1,-INT_FRAME_SIZE
64 ACCOUNT_CPU_USER_ENTRY(r10, r11)
66 * This "crclr so" clears CR0.SO, which is the error indication on
67 * return from this system call. There must be no cmp instruction
68 * between it and the "mfcr r9" below, otherwise if XER.SO is set,
69 * CR0.SO will get set, causing all system calls to appear to fail.
97 addi r9,r1,STACK_FRAME_OVERHEAD
98 ld r11,exception_marker@toc(r2)
99 std r11,-16(r9) /* "regshere" marker */
100 #if defined(CONFIG_VIRT_CPU_ACCOUNTING) && defined(CONFIG_PPC_SPLPAR)
103 /* if from user, see if there are any DTL entries to process */
104 ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */
105 ld r11,PACA_DTL_RIDX(r13) /* get log read index */
106 ld r10,LPPACA_DTLIDX(r10) /* get log write index */
109 bl .accumulate_stolen_time
113 addi r9,r1,STACK_FRAME_OVERHEAD
115 END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
116 #endif /* CONFIG_VIRT_CPU_ACCOUNTING && CONFIG_PPC_SPLPAR */
118 #ifdef CONFIG_TRACE_IRQFLAGS
119 bl .trace_hardirqs_on
123 addi r9,r1,STACK_FRAME_OVERHEAD
125 #endif /* CONFIG_TRACE_IRQFLAGS */
127 stb r10,PACASOFTIRQEN(r13)
128 stb r10,PACAHARDIRQEN(r13)
131 /* Hard enable interrupts */
132 #ifdef CONFIG_PPC_BOOK3E
138 #endif /* CONFIG_PPC_BOOK3E */
145 addi r9,r1,STACK_FRAME_OVERHEAD
147 clrrdi r11,r1,THREAD_SHIFT
149 andi. r11,r10,_TIF_SYSCALL_T_OR_A
151 syscall_dotrace_cont:
152 cmpldi 0,r0,NR_syscalls
155 system_call: /* label this so stack traces look sane */
157 * Need to vector to 32 Bit or default sys_call_table here,
158 * based on caller's run-mode / personality.
160 ld r11,.SYS_CALL_TABLE@toc(2)
161 andi. r10,r10,_TIF_32BIT
163 addi r11,r11,8 /* use 32-bit syscall entries */
172 ldx r10,r11,r0 /* Fetch system call handler [ptr] */
174 bctrl /* Call handler */
179 bl .do_show_syscall_exit
182 clrrdi r12,r1,THREAD_SHIFT
185 #ifdef CONFIG_PPC_BOOK3S
186 /* No MSR:RI on BookE */
191 /* Disable interrupts so current_thread_info()->flags can't change,
192 * and so that we don't get interrupted after loading SRR0/1.
194 #ifdef CONFIG_PPC_BOOK3E
201 #endif /* CONFIG_PPC_BOOK3E */
205 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
206 bne- syscall_exit_work
213 stdcx. r0,0,r1 /* to clear the reservation */
214 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
218 * Clear RI before restoring r13. If we are returning to
219 * userspace and we take an exception after restoring r13,
220 * we end up corrupting the userspace r13 value.
222 #ifdef CONFIG_PPC_BOOK3S
223 /* No MSR:RI on BookE */
226 mtmsrd r11,1 /* clear MSR.RI */
227 #endif /* CONFIG_PPC_BOOK3S */
230 ACCOUNT_CPU_USER_EXIT(r11, r12)
231 ld r13,GPR13(r1) /* only restore r13 if returning to usermode */
239 b . /* prevent speculative execution */
242 oris r5,r5,0x1000 /* Set SO bit in CR */
247 /* Traced system call support */
250 addi r3,r1,STACK_FRAME_OVERHEAD
251 bl .do_syscall_trace_enter
253 * Restore argument registers possibly just changed.
254 * We use the return value of do_syscall_trace_enter
255 * for the call number to look up in the table (r0).
264 addi r9,r1,STACK_FRAME_OVERHEAD
265 clrrdi r10,r1,THREAD_SHIFT
267 b syscall_dotrace_cont
274 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
275 If TIF_NOERROR is set, just save r3 as it is. */
277 andi. r0,r9,_TIF_RESTOREALL
281 0: cmpld r3,r11 /* r10 is -LAST_ERRNO */
283 andi. r0,r9,_TIF_NOERROR
287 oris r5,r5,0x1000 /* Set SO bit in CR */
290 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
293 /* Clear per-syscall TIF flags if any are set. */
295 li r11,_TIF_PERSYSCALL_MASK
296 addi r12,r12,TI_FLAGS
301 subi r12,r12,TI_FLAGS
303 4: /* Anything else left to do? */
304 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
305 beq .ret_from_except_lite
307 /* Re-enable interrupts */
308 #ifdef CONFIG_PPC_BOOK3E
314 #endif /* CONFIG_PPC_BOOK3E */
317 addi r3,r1,STACK_FRAME_OVERHEAD
318 bl .do_syscall_trace_leave
321 /* Save non-volatile GPRs, if not already saved. */
333 * The sigsuspend and rt_sigsuspend system calls can call do_signal
334 * and thus put the process into the stopped state where we might
335 * want to examine its user state with ptrace. Therefore we need
336 * to save all the nonvolatile registers (r14 - r31) before calling
337 * the C code. Similarly, fork, vfork and clone need the full
338 * register state on the stack so that it can be copied to the child.
356 _GLOBAL(ppc32_swapcontext)
358 bl .compat_sys_swapcontext
361 _GLOBAL(ppc64_swapcontext)
366 _GLOBAL(ret_from_fork)
373 * This routine switches between two different tasks. The process
374 * state of one is saved on its kernel stack. Then the state
375 * of the other is restored from its kernel stack. The memory
376 * management hardware is updated to the second process's state.
377 * Finally, we can return to the second process, via ret_from_except.
378 * On entry, r3 points to the THREAD for the current task, r4
379 * points to the THREAD for the new task.
381 * Note: there are two ways to get to the "going out" portion
382 * of this code; either by coming in via the entry (_switch)
383 * or via "fork" which must set up an environment equivalent
384 * to the "_switch" path. If you change this you'll have to change
385 * the fork code also.
387 * The code which creates the new task context is in 'copy_thread'
388 * in arch/powerpc/kernel/process.c
394 stdu r1,-SWITCH_FRAME_SIZE(r1)
395 /* r3-r13 are caller saved -- Cort */
398 mflr r20 /* Return to switch caller */
403 oris r0,r0,MSR_VSX@h /* Disable VSX */
404 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
405 #endif /* CONFIG_VSX */
406 #ifdef CONFIG_ALTIVEC
408 oris r0,r0,MSR_VEC@h /* Disable altivec */
409 mfspr r24,SPRN_VRSAVE /* save vrsave register value */
410 std r24,THREAD_VRSAVE(r3)
411 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
412 #endif /* CONFIG_ALTIVEC */
416 std r25,THREAD_DSCR(r3)
417 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
427 std r1,KSP(r3) /* Set old stack pointer */
430 /* We need a sync somewhere here to make sure that if the
431 * previous task gets rescheduled on another CPU, it sees all
432 * stores it has performed on this one.
435 #endif /* CONFIG_SMP */
438 * If we optimise away the clear of the reservation in system
439 * calls because we know the CPU tracks the address of the
440 * reservation, then we need to clear it here to cover the
441 * case that the kernel context switch path has no larx
446 END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
448 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
449 std r6,PACACURRENT(r13) /* Set new 'current' */
451 ld r8,KSP(r4) /* new stack pointer */
452 #ifdef CONFIG_PPC_BOOK3S
454 BEGIN_FTR_SECTION_NESTED(95)
455 clrrdi r6,r8,28 /* get its ESID */
456 clrrdi r9,r1,28 /* get current sp ESID */
457 FTR_SECTION_ELSE_NESTED(95)
458 clrrdi r6,r8,40 /* get its 1T ESID */
459 clrrdi r9,r1,40 /* get current sp 1T ESID */
460 ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)
463 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)
464 clrldi. r0,r6,2 /* is new ESID c00000000? */
465 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
467 beq 2f /* if yes, don't slbie it */
469 /* Bolt in the new stack SLB entry */
470 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
471 oris r0,r6,(SLB_ESID_V)@h
472 ori r0,r0,(SLB_NUM_BOLTED-1)@l
474 li r9,MMU_SEGSIZE_1T /* insert B field */
475 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
476 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
477 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
479 /* Update the last bolted SLB. No write barriers are needed
480 * here, provided we only update the current CPU's SLB shadow
483 ld r9,PACA_SLBSHADOWPTR(r13)
485 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
486 std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
487 std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
489 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
490 * we have 1TB segments, the only CPUs known to have the errata
491 * only support less than 1TB of system memory and we'll never
492 * actually hit this code path.
496 slbie r6 /* Workaround POWER5 < DD2.1 issue */
500 #endif /* !CONFIG_PPC_BOOK3S */
502 clrrdi r7,r8,THREAD_SHIFT /* base of new stack */
503 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
504 because we don't need to leave the 288-byte ABI gap at the
505 top of the kernel stack. */
506 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
508 mr r1,r8 /* start using new stack pointer */
509 std r7,PACAKSAVE(r13)
514 #ifdef CONFIG_ALTIVEC
516 ld r0,THREAD_VRSAVE(r4)
517 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
518 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
519 #endif /* CONFIG_ALTIVEC */
522 ld r0,THREAD_DSCR(r4)
527 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
530 /* r3-r13 are destroyed -- Cort */
534 /* convert old thread to its task_struct for return value */
536 ld r7,_NIP(r1) /* Return to _switch caller in new task */
538 addi r1,r1,SWITCH_FRAME_SIZE
542 _GLOBAL(ret_from_except)
545 bne .ret_from_except_lite
548 _GLOBAL(ret_from_except_lite)
550 * Disable interrupts so that current_thread_info()->flags
551 * can't change between when we test it and when we return
552 * from the interrupt.
554 #ifdef CONFIG_PPC_BOOK3E
557 mfmsr r10 /* Get current interrupt state */
558 rldicl r9,r10,48,1 /* clear MSR_EE */
560 mtmsrd r9,1 /* Update machine state */
561 #endif /* CONFIG_PPC_BOOK3E */
563 #ifdef CONFIG_PREEMPT
564 clrrdi r9,r1,THREAD_SHIFT /* current_thread_info() */
565 li r0,_TIF_NEED_RESCHED /* bits to check */
568 /* Move MSR_PR bit in r3 to _TIF_SIGPENDING position in r0 */
569 rlwimi r0,r3,32+TIF_SIGPENDING-MSR_PR_LG,_TIF_SIGPENDING
570 and. r0,r4,r0 /* check NEED_RESCHED and maybe SIGPENDING */
573 #else /* !CONFIG_PREEMPT */
574 ld r3,_MSR(r1) /* Returning to user mode? */
576 beq restore /* if not, just restore regs and return */
578 /* Check current_thread_info()->flags */
579 clrrdi r9,r1,THREAD_SHIFT
581 andi. r0,r4,_TIF_USER_WORK_MASK
583 #endif /* !CONFIG_PREEMPT */
587 TRACE_AND_RESTORE_IRQ(r5);
589 /* extract EE bit and use it to restore paca->hard_enabled */
591 rldicl r4,r3,49,63 /* r0 = (r3 >> 15) & 1 */
592 stb r4,PACAHARDIRQEN(r13)
594 #ifdef CONFIG_PPC_BOOK3E
595 b .exception_return_book3e
610 * Clear the reservation. If we know the CPU tracks the address of
611 * the reservation then we can potentially save some cycles and use
612 * a larx. On POWER6 and POWER7 this is significantly faster.
615 stdcx. r0,0,r1 /* to clear the reservation */
618 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
621 * Clear RI before restoring r13. If we are returning to
622 * userspace and we take an exception after restoring r13,
623 * we end up corrupting the userspace r13 value.
626 andc r4,r4,r0 /* r0 contains MSR_RI here */
630 * r13 is our per cpu area, only restore it if we are returning to
635 ACCOUNT_CPU_USER_EXIT(r2, r4)
652 b . /* prevent speculative execution */
654 #endif /* CONFIG_PPC_BOOK3E */
657 #ifdef CONFIG_PREEMPT
658 andi. r0,r3,MSR_PR /* Returning to user mode? */
660 /* Check that preempt_count() == 0 and interrupts are enabled */
661 lwz r8,TI_PREEMPT(r9)
665 crandc eq,cr1*4+eq,eq
668 /* Here we are preempting the current task.
670 * Ensure interrupts are soft-disabled. We also properly mark
671 * the PACA to reflect the fact that they are hard-disabled
672 * and trace the change
675 stb r0,PACASOFTIRQEN(r13)
676 stb r0,PACAHARDIRQEN(r13)
679 /* Call the scheduler with soft IRQs off */
680 1: bl .preempt_schedule_irq
682 /* Hard-disable interrupts again (and update PACA) */
683 #ifdef CONFIG_PPC_BOOK3E
690 #endif /* CONFIG_PPC_BOOK3E */
692 stb r0,PACAHARDIRQEN(r13)
694 /* Re-test flags and eventually loop */
695 clrrdi r9,r1,THREAD_SHIFT
697 andi. r0,r4,_TIF_NEED_RESCHED
702 #endif /* CONFIG_PREEMPT */
704 /* Enable interrupts */
705 #ifdef CONFIG_PPC_BOOK3E
710 #endif /* CONFIG_PPC_BOOK3E */
712 andi. r0,r4,_TIF_NEED_RESCHED
715 TRACE_AND_RESTORE_IRQ(r5);
717 b .ret_from_except_lite
721 TRACE_AND_RESTORE_IRQ(r5);
722 addi r3,r1,STACK_FRAME_OVERHEAD
727 addi r3,r1,STACK_FRAME_OVERHEAD
728 bl .unrecoverable_exception
731 #ifdef CONFIG_PPC_RTAS
733 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
734 * called with the MMU off.
736 * In addition, we need to be in 32b mode, at least for now.
738 * Note: r3 is an input parameter to rtas, so don't trash it...
743 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
745 /* Because RTAS is running in 32b mode, it clobbers the high order half
746 * of all registers that it saves. We therefore save those registers
747 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
749 SAVE_GPR(2, r1) /* Save the TOC */
750 SAVE_GPR(13, r1) /* Save paca */
751 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
752 SAVE_10GPRS(22, r1) /* ditto */
765 /* Temporary workaround to clear CR until RTAS can be modified to
772 /* There is no way it is acceptable to get here with interrupts enabled,
773 * check it with the asm equivalent of WARN_ON
775 lbz r0,PACASOFTIRQEN(r13)
777 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
780 /* Hard-disable interrupts */
786 /* Unfortunately, the stack pointer and the MSR are also clobbered,
787 * so they are saved in the PACA which allows us to restore
788 * our original state after RTAS returns.
791 std r6,PACASAVEDMSR(r13)
793 /* Setup our real return addr */
794 LOAD_REG_ADDR(r4,.rtas_return_loc)
795 clrldi r4,r4,2 /* convert to realmode address */
799 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
803 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
804 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI
806 sync /* disable interrupts so SRR0/1 */
807 mtmsrd r0 /* don't get trashed */
809 LOAD_REG_ADDR(r4, rtas)
810 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
811 ld r4,RTASBASE(r4) /* get the rtas->base value */
816 b . /* prevent speculative execution */
818 _STATIC(rtas_return_loc)
819 /* relocation is off at this point */
821 clrldi r4,r4,2 /* convert to realmode address */
825 ld r3,(1f-0b)(r3) /* get &.rtas_restore_regs */
833 ld r1,PACAR1(r4) /* Restore our SP */
834 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
839 b . /* prevent speculative execution */
842 1: .llong .rtas_restore_regs
844 _STATIC(rtas_restore_regs)
845 /* relocation is on at this point */
846 REST_GPR(2, r1) /* Restore the TOC */
847 REST_GPR(13, r1) /* Restore paca */
848 REST_8GPRS(14, r1) /* Restore the non-volatiles */
849 REST_10GPRS(22, r1) /* ditto */
864 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
865 ld r0,16(r1) /* get return address */
868 blr /* return to caller */
870 #endif /* CONFIG_PPC_RTAS */
875 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
877 /* Because PROM is running in 32b mode, it clobbers the high order half
878 * of all registers that it saves. We therefore save those registers
879 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
890 /* Get the PROM entrypoint */
893 /* Switch MSR to 32 bits mode
895 #ifdef CONFIG_PPC_BOOK3E
896 rlwinm r11,r11,0,1,31
898 #else /* CONFIG_PPC_BOOK3E */
901 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
904 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
907 #endif /* CONFIG_PPC_BOOK3E */
910 /* Enter PROM here... */
913 /* Just make sure that r1 top 32 bits didn't get
918 /* Restore the MSR (back to 64 bits) */
923 /* Restore other registers */
931 addi r1,r1,PROM_FRAME_SIZE
936 #ifdef CONFIG_FUNCTION_TRACER
937 #ifdef CONFIG_DYNAMIC_FTRACE
942 _GLOBAL(ftrace_caller)
943 /* Taken from output of objdump from lib64/glibc */
949 subi r3, r3, MCOUNT_INSN_SIZE
954 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
955 .globl ftrace_graph_call
958 _GLOBAL(ftrace_graph_stub)
970 /* Taken from output of objdump from lib64/glibc */
977 subi r3, r3, MCOUNT_INSN_SIZE
978 LOAD_REG_ADDR(r5,ftrace_trace_function)
986 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
987 b ftrace_graph_caller
995 #endif /* CONFIG_DYNAMIC_FTRACE */
997 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
998 _GLOBAL(ftrace_graph_caller)
999 /* load r4 with local address */
1001 subi r4, r4, MCOUNT_INSN_SIZE
1003 /* get the parent address */
1007 bl .prepare_ftrace_return
1015 _GLOBAL(return_to_handler)
1016 /* need to save return values */
1023 bl .ftrace_return_to_handler
1026 /* return value has real return address */
1034 /* Jump back to real return address */
1037 _GLOBAL(mod_return_to_handler)
1038 /* need to save return values */
1048 * We are in a module using the module's TOC.
1049 * Switch to our TOC to run inside the core kernel.
1053 bl .ftrace_return_to_handler
1056 /* return value has real return address */
1065 /* Jump back to real return address */
1067 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1068 #endif /* CONFIG_FUNCTION_TRACER */