3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/errno.h>
23 #include <linux/sys.h>
24 #include <linux/threads.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/unistd.h>
33 #include <asm/ftrace.h>
34 #include <asm/ptrace.h>
37 #undef SHOW_SYSCALLS_TASK
40 * MSR_KERNEL is > 0x10000 on 4xx/Book-E since it include MSR_CE.
42 #if MSR_KERNEL >= 0x10000
43 #define LOAD_MSR_KERNEL(r, x) lis r,(x)@h; ori r,r,(x)@l
45 #define LOAD_MSR_KERNEL(r, x) li r,(x)
49 .globl mcheck_transfer_to_handler
50 mcheck_transfer_to_handler:
57 .globl debug_transfer_to_handler
58 debug_transfer_to_handler:
65 .globl crit_transfer_to_handler
66 crit_transfer_to_handler:
67 #ifdef CONFIG_PPC_BOOK3E_MMU
78 #ifdef CONFIG_PHYS_64BIT
81 #endif /* CONFIG_PHYS_64BIT */
82 #endif /* CONFIG_PPC_BOOK3E_MMU */
92 mfspr r8,SPRN_SPRG_THREAD
94 stw r0,SAVED_KSP_LIMIT(r11)
95 CURRENT_THREAD_INFO(r0, r1)
101 .globl crit_transfer_to_handler
102 crit_transfer_to_handler:
108 stw r0,crit_srr0@l(0)
110 stw r0,crit_srr1@l(0)
112 mfspr r8,SPRN_SPRG_THREAD
114 stw r0,saved_ksp_limit@l(0)
115 CURRENT_THREAD_INFO(r0, r1)
121 * This code finishes saving the registers to the exception frame
122 * and jumps to the appropriate handler for the exception, turning
123 * on address translation.
124 * Note that we rely on the caller having set cr0.eq iff the exception
125 * occurred in kernel mode (i.e. MSR:PR = 0).
127 .globl transfer_to_handler_full
128 transfer_to_handler_full:
132 .globl transfer_to_handler
142 mfspr r12,SPRN_SPRG_THREAD
144 tovirt(r2,r2) /* set r2 to current */
145 beq 2f /* if from user, fix up THREAD.regs */
146 addi r11,r1,STACK_FRAME_OVERHEAD
148 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
149 /* Check to see if the dbcr0 register is set up to debug. Use the
150 internal debug mode bit to do this. */
151 lwz r12,THREAD_DBCR0(r12)
152 andis. r12,r12,DBCR0_IDM@h
154 /* From user and task is ptraced - load up global dbcr0 */
155 li r12,-1 /* clear all pending debug events */
157 lis r11,global_dbcr0@ha
159 addi r11,r11,global_dbcr0@l
161 CURRENT_THREAD_INFO(r9, r1)
174 2: /* if from kernel, check interrupted DOZE/NAP mode and
175 * check for stack overflow
177 lwz r9,KSP_LIMIT(r12)
178 cmplw r1,r9 /* if r1 <= ksp_limit */
179 ble- stack_ovf /* then the kernel stack overflowed */
181 #if defined(CONFIG_6xx) || defined(CONFIG_E500)
182 CURRENT_THREAD_INFO(r9, r1)
183 tophys(r9,r9) /* check local flags */
184 lwz r12,TI_LOCAL_FLAGS(r9)
186 bt- 31-TLF_NAPPING,4f
187 bt- 31-TLF_SLEEPING,7f
188 #endif /* CONFIG_6xx || CONFIG_E500 */
189 .globl transfer_to_handler_cont
190 transfer_to_handler_cont:
193 lwz r11,0(r9) /* virtual address of handler */
194 lwz r9,4(r9) /* where to go when done */
195 #ifdef CONFIG_TRACE_IRQFLAGS
196 lis r12,reenable_mmu@h
197 ori r12,r12,reenable_mmu@l
202 reenable_mmu: /* re-enable mmu so we can */
206 andi. r10,r10,MSR_EE /* Did EE change? */
210 * The trace_hardirqs_off will use CALLER_ADDR0 and CALLER_ADDR1.
211 * If from user mode there is only one stack frame on the stack, and
212 * accessing CALLER_ADDR1 will cause oops. So we need create a dummy
213 * stack frame to make trace_hardirqs_off happy.
215 * This is handy because we also need to save a bunch of GPRs,
216 * r3 can be different from GPR3(r1) at this point, r9 and r11
217 * contains the old MSR and handler address respectively,
218 * r4 & r5 can contain page fault arguments that need to be passed
219 * along as well. r12, CCR, CTR, XER etc... are left clobbered as
220 * they aren't useful past this point (aren't syscall arguments),
221 * the rest is restored from the exception frame.
229 bl trace_hardirqs_off
242 bctr /* jump to handler */
243 #else /* CONFIG_TRACE_IRQFLAGS */
248 RFI /* jump to handler, enable MMU */
249 #endif /* CONFIG_TRACE_IRQFLAGS */
251 #if defined (CONFIG_6xx) || defined(CONFIG_E500)
252 4: rlwinm r12,r12,0,~_TLF_NAPPING
253 stw r12,TI_LOCAL_FLAGS(r9)
254 b power_save_ppc32_restore
256 7: rlwinm r12,r12,0,~_TLF_SLEEPING
257 stw r12,TI_LOCAL_FLAGS(r9)
258 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */
259 rlwinm r9,r9,0,~MSR_EE
260 lwz r12,_LINK(r11) /* and return to address in LR */
261 b fast_exception_return
265 * On kernel stack overflow, load up an initial stack pointer
266 * and call StackOverflow(regs), which should not return.
269 /* sometimes we use a statically-allocated stack, which is OK. */
273 ble 5b /* r1 <= &_end is OK */
275 addi r3,r1,STACK_FRAME_OVERHEAD
276 lis r1,init_thread_union@ha
277 addi r1,r1,init_thread_union@l
278 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
279 lis r9,StackOverflow@ha
280 addi r9,r9,StackOverflow@l
281 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
289 * Handle a system call.
291 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
292 .stabs "entry_32.S",N_SO,0,0,0f
299 lwz r11,_CCR(r1) /* Clear SO bit in CR */
304 #endif /* SHOW_SYSCALLS */
305 #ifdef CONFIG_TRACE_IRQFLAGS
306 /* Return from syscalls can (and generally will) hard enable
307 * interrupts. You aren't supposed to call a syscall with
308 * interrupts disabled in the first place. However, to ensure
309 * that we get it right vs. lockdep if it happens, we force
310 * that hard enable here with appropriate tracing if we see
311 * that we have been called with interrupts off
316 /* We came in with interrupts disabled, we enable them now */
329 #endif /* CONFIG_TRACE_IRQFLAGS */
330 CURRENT_THREAD_INFO(r10, r1)
331 lwz r11,TI_FLAGS(r10)
332 andi. r11,r11,_TIF_SYSCALL_T_OR_A
334 syscall_dotrace_cont:
335 cmplwi 0,r0,NR_syscalls
336 lis r10,sys_call_table@h
337 ori r10,r10,sys_call_table@l
340 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */
342 addi r9,r1,STACK_FRAME_OVERHEAD
344 blrl /* Call handler */
345 .globl ret_from_syscall
348 bl do_show_syscall_exit
351 CURRENT_THREAD_INFO(r12, r1)
352 /* disable interrupts so current_thread_info()->flags can't change */
353 LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
354 /* Note: We don't bother telling lockdep about it */
359 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
360 bne- syscall_exit_work
362 blt+ syscall_exit_cont
363 lwz r11,_CCR(r1) /* Load CR */
365 oris r11,r11,0x1000 /* Set SO bit in CR */
369 #ifdef CONFIG_TRACE_IRQFLAGS
370 /* If we are going to return from the syscall with interrupts
371 * off, we trace that here. It shouldn't happen though but we
372 * want to catch the bugger if it does right ?
377 bl trace_hardirqs_off
380 #endif /* CONFIG_TRACE_IRQFLAGS */
381 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
382 /* If the process has its own DBCR0 value, load it up. The internal
383 debug mode bit tells us that dbcr0 should be loaded. */
384 lwz r0,THREAD+THREAD_DBCR0(r2)
385 andis. r10,r0,DBCR0_IDM@h
389 BEGIN_MMU_FTR_SECTION
390 lis r4,icache_44x_need_flush@ha
391 lwz r5,icache_44x_need_flush@l(r4)
395 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x)
396 #endif /* CONFIG_44x */
399 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
400 stwcx. r0,0,r1 /* to clear the reservation */
416 stw r7,icache_44x_need_flush@l(r4)
418 #endif /* CONFIG_44x */
430 /* Traced system call support */
435 addi r3,r1,STACK_FRAME_OVERHEAD
436 bl do_syscall_trace_enter
438 * Restore argument registers possibly just changed.
439 * We use the return value of do_syscall_trace_enter
440 * for call number to look up in the table (r0).
450 b syscall_dotrace_cont
453 andi. r0,r9,_TIF_RESTOREALL
459 andi. r0,r9,_TIF_NOERROR
461 lwz r11,_CCR(r1) /* Load CR */
463 oris r11,r11,0x1000 /* Set SO bit in CR */
466 1: stw r6,RESULT(r1) /* Save result */
467 stw r3,GPR3(r1) /* Update return value */
468 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
471 /* Clear per-syscall TIF flags if any are set. */
473 li r11,_TIF_PERSYSCALL_MASK
474 addi r12,r12,TI_FLAGS
477 #ifdef CONFIG_IBM405_ERR77
482 subi r12,r12,TI_FLAGS
484 4: /* Anything which requires enabling interrupts? */
485 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
488 /* Re-enable interrupts. There is no need to trace that with
489 * lockdep as we are supposed to have IRQs on at this point
495 /* Save NVGPRS if they're not saved already */
503 addi r3,r1,STACK_FRAME_OVERHEAD
504 bl do_syscall_trace_leave
505 b ret_from_except_full
509 #ifdef SHOW_SYSCALLS_TASK
510 lis r11,show_syscalls_task@ha
511 lwz r11,show_syscalls_task@l(r11)
542 do_show_syscall_exit:
543 #ifdef SHOW_SYSCALLS_TASK
544 lis r11,show_syscalls_task@ha
545 lwz r11,show_syscalls_task@l(r11)
551 stw r3,RESULT(r1) /* Save result */
561 7: .string "syscall %d(%x, %x, %x, %x, %x, "
562 77: .string "%x), current=%p\n"
563 79: .string " -> %x\n"
566 #ifdef SHOW_SYSCALLS_TASK
568 .globl show_syscalls_task
573 #endif /* SHOW_SYSCALLS */
576 * The fork/clone functions need to copy the full register set into
577 * the child process. Therefore we need to save all the nonvolatile
578 * registers (r13 - r31) before calling the C code.
584 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
585 stw r0,_TRAP(r1) /* register set saved */
592 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
593 stw r0,_TRAP(r1) /* register set saved */
600 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
601 stw r0,_TRAP(r1) /* register set saved */
604 .globl ppc_swapcontext
608 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */
609 stw r0,_TRAP(r1) /* register set saved */
613 * Top-level page fault handling.
614 * This is in assembler because if do_page_fault tells us that
615 * it is a bad kernel page fault, we want to save the non-volatile
616 * registers before calling bad_page_fault.
618 .globl handle_page_fault
621 addi r3,r1,STACK_FRAME_OVERHEAD
630 addi r3,r1,STACK_FRAME_OVERHEAD
633 b ret_from_except_full
636 * This routine switches between two different tasks. The process
637 * state of one is saved on its kernel stack. Then the state
638 * of the other is restored from its kernel stack. The memory
639 * management hardware is updated to the second process's state.
640 * Finally, we can return to the second process.
641 * On entry, r3 points to the THREAD for the current task, r4
642 * points to the THREAD for the new task.
644 * This routine is always called with interrupts disabled.
646 * Note: there are two ways to get to the "going out" portion
647 * of this code; either by coming in via the entry (_switch)
648 * or via "fork" which must set up an environment equivalent
649 * to the "_switch" path. If you change this , you'll have to
650 * change the fork code also.
652 * The code which creates the new task context is in 'copy_thread'
653 * in arch/ppc/kernel/process.c
656 stwu r1,-INT_FRAME_SIZE(r1)
658 stw r0,INT_FRAME_SIZE+4(r1)
659 /* r3-r12 are caller saved -- Cort */
661 stw r0,_NIP(r1) /* Return to switch caller */
663 li r0,MSR_FP /* Disable floating-point */
664 #ifdef CONFIG_ALTIVEC
666 oris r0,r0,MSR_VEC@h /* Disable altivec */
667 mfspr r12,SPRN_VRSAVE /* save vrsave register value */
668 stw r12,THREAD+THREAD_VRSAVE(r2)
669 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
670 #endif /* CONFIG_ALTIVEC */
673 oris r0,r0,MSR_SPE@h /* Disable SPE */
674 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
675 stw r12,THREAD+THREAD_SPEFSCR(r2)
676 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
677 #endif /* CONFIG_SPE */
678 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
686 stw r1,KSP(r3) /* Set old stack pointer */
689 /* We need a sync somewhere here to make sure that if the
690 * previous task gets rescheduled on another CPU, it sees all
691 * stores it has performed on this one.
694 #endif /* CONFIG_SMP */
698 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */
699 lwz r1,KSP(r4) /* Load new stack pointer */
701 /* save the old current 'last' for return value */
703 addi r2,r4,-THREAD /* Update current */
705 #ifdef CONFIG_ALTIVEC
707 lwz r0,THREAD+THREAD_VRSAVE(r2)
708 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
709 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
710 #endif /* CONFIG_ALTIVEC */
713 lwz r0,THREAD+THREAD_SPEFSCR(r2)
714 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
715 END_FTR_SECTION_IFSET(CPU_FTR_SPE)
716 #endif /* CONFIG_SPE */
720 /* r3-r12 are destroyed -- Cort */
723 lwz r4,_NIP(r1) /* Return to _switch caller in new task */
725 addi r1,r1,INT_FRAME_SIZE
728 .globl fast_exception_return
729 fast_exception_return:
730 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
731 andi. r10,r9,MSR_RI /* check for recoverable interrupt */
732 beq 1f /* if not, we've got problems */
735 2: REST_4GPRS(3, r11)
750 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
751 /* check if the exception happened in a restartable section */
752 1: lis r3,exc_exit_restart_end@ha
753 addi r3,r3,exc_exit_restart_end@l
756 lis r4,exc_exit_restart@ha
757 addi r4,r4,exc_exit_restart@l
760 lis r3,fee_restarts@ha
762 lwz r5,fee_restarts@l(r3)
764 stw r5,fee_restarts@l(r3)
765 mr r12,r4 /* restart at exc_exit_restart */
774 /* aargh, a nonrecoverable interrupt, panic */
775 /* aargh, we don't know which trap this is */
776 /* but the 601 doesn't implement the RI bit, so assume it's OK */
780 END_FTR_SECTION_IFSET(CPU_FTR_601)
783 addi r3,r1,STACK_FRAME_OVERHEAD
785 ori r10,r10,MSR_KERNEL@l
786 bl transfer_to_handler_full
787 .long nonrecoverable_exception
788 .long ret_from_except
791 .globl ret_from_except_full
792 ret_from_except_full:
796 .globl ret_from_except
798 /* Hard-disable interrupts so that current_thread_info()->flags
799 * can't change between when we test it and when we return
800 * from the interrupt. */
801 /* Note: We don't bother telling lockdep about it */
802 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
803 SYNC /* Some chip revs have problems here... */
804 MTMSRD(r10) /* disable interrupts */
806 lwz r3,_MSR(r1) /* Returning to user mode? */
810 user_exc_return: /* r10 contains MSR_KERNEL here */
811 /* Check current_thread_info()->flags */
812 CURRENT_THREAD_INFO(r9, r1)
814 andi. r0,r9,_TIF_USER_WORK_MASK
818 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
819 /* Check whether this process has its own DBCR0 value. The internal
820 debug mode bit tells us that dbcr0 should be loaded. */
821 lwz r0,THREAD+THREAD_DBCR0(r2)
822 andis. r10,r0,DBCR0_IDM@h
826 #ifdef CONFIG_PREEMPT
829 /* N.B. the only way to get here is from the beq following ret_from_except. */
831 /* check current_thread_info->preempt_count */
832 CURRENT_THREAD_INFO(r9, r1)
833 lwz r0,TI_PREEMPT(r9)
834 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
837 andi. r0,r0,_TIF_NEED_RESCHED
839 andi. r0,r3,MSR_EE /* interrupts off? */
840 beq restore /* don't schedule if so */
841 #ifdef CONFIG_TRACE_IRQFLAGS
842 /* Lockdep thinks irqs are enabled, we need to call
843 * preempt_schedule_irq with IRQs off, so we inform lockdep
844 * now that we -did- turn them off already
846 bl trace_hardirqs_off
848 1: bl preempt_schedule_irq
849 CURRENT_THREAD_INFO(r9, r1)
851 andi. r0,r3,_TIF_NEED_RESCHED
853 #ifdef CONFIG_TRACE_IRQFLAGS
854 /* And now, to properly rebalance the above, we tell lockdep they
855 * are being turned back on, which will happen when we return
861 #endif /* CONFIG_PREEMPT */
863 /* interrupts are hard-disabled at this point */
866 BEGIN_MMU_FTR_SECTION
868 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
869 lis r4,icache_44x_need_flush@ha
870 lwz r5,icache_44x_need_flush@l(r4)
875 stw r6,icache_44x_need_flush@l(r4)
877 #endif /* CONFIG_44x */
880 #ifdef CONFIG_TRACE_IRQFLAGS
881 /* Lockdep doesn't know about the fact that IRQs are temporarily turned
882 * off in this assembly code while peeking at TI_FLAGS() and such. However
883 * we need to inform it if the exception turned interrupts off, and we
884 * are about to trun them back on.
886 * The problem here sadly is that we don't know whether the exceptions was
887 * one that turned interrupts off or not. So we always tell lockdep about
888 * turning them on here when we go back to wherever we came from with EE
889 * on, even if that may meen some redudant calls being tracked. Maybe later
890 * we could encode what the exception did somewhere or test the exception
891 * type in the pt_regs but that sounds overkill
896 * Since the ftrace irqsoff latency trace checks CALLER_ADDR1,
897 * which is the stack frame here, we need to force a stack frame
898 * in case we came from user space.
909 #endif /* CONFIG_TRACE_IRQFLAGS */
924 END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
925 stwcx. r0,0,r1 /* to clear the reservation */
927 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
928 andi. r10,r9,MSR_RI /* check if this exception occurred */
929 beql nonrecoverable /* at a bad place (MSR:RI = 0) */
937 * Once we put values in SRR0 and SRR1, we are in a state
938 * where exceptions are not recoverable, since taking an
939 * exception will trash SRR0 and SRR1. Therefore we clear the
940 * MSR:RI bit to indicate this. If we do take an exception,
941 * we can't return to the point of the exception but we
942 * can restart the exception exit path at the label
943 * exc_exit_restart below. -- paulus
945 LOAD_MSR_KERNEL(r10,MSR_KERNEL & ~MSR_RI)
947 MTMSRD(r10) /* clear the RI bit */
948 .globl exc_exit_restart
956 .globl exc_exit_restart_end
957 exc_exit_restart_end:
961 #else /* !(CONFIG_4xx || CONFIG_BOOKE) */
963 * This is a bit different on 4xx/Book-E because it doesn't have
964 * the RI bit in the MSR.
965 * The TLB miss handler checks if we have interrupted
966 * the exception exit path and restarts it if so
967 * (well maybe one day it will... :).
974 .globl exc_exit_restart
983 .globl exc_exit_restart_end
984 exc_exit_restart_end:
987 b . /* prevent prefetch past rfi */
990 * Returning from a critical interrupt in user mode doesn't need
991 * to be any different from a normal exception. For a critical
992 * interrupt in the kernel, we just return (without checking for
993 * preemption) since the interrupt may have happened at some crucial
994 * place (e.g. inside the TLB miss handler), and because we will be
995 * running with r1 pointing into critical_stack, not the current
996 * process's kernel stack (and therefore current_thread_info() will
997 * give the wrong answer).
998 * We have to restore various SPRs that may have been in use at the
999 * time of the critical interrupt.
1003 #define PPC_40x_TURN_OFF_MSR_DR \
1004 /* avoid any possible TLB misses here by turning off MSR.DR, we \
1005 * assume the instructions here are mapped by a pinned TLB entry */ \
1011 #define PPC_40x_TURN_OFF_MSR_DR
1014 #define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \
1017 andi. r3,r3,MSR_PR; \
1018 LOAD_MSR_KERNEL(r10,MSR_KERNEL); \
1019 bne user_exc_return; \
1022 REST_4GPRS(3, r1); \
1023 REST_2GPRS(7, r1); \
1026 mtspr SPRN_XER,r10; \
1028 PPC405_ERR77(0,r1); \
1029 stwcx. r0,0,r1; /* to clear the reservation */ \
1030 lwz r11,_LINK(r1); \
1034 PPC_40x_TURN_OFF_MSR_DR; \
1037 mtspr SPRN_DEAR,r9; \
1038 mtspr SPRN_ESR,r10; \
1041 mtspr exc_lvl_srr0,r11; \
1042 mtspr exc_lvl_srr1,r12; \
1044 lwz r12,GPR12(r1); \
1045 lwz r10,GPR10(r1); \
1046 lwz r11,GPR11(r1); \
1048 PPC405_ERR77_SYNC; \
1050 b .; /* prevent prefetch past exc_lvl_rfi */
1052 #define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \
1053 lwz r9,_##exc_lvl_srr0(r1); \
1054 lwz r10,_##exc_lvl_srr1(r1); \
1055 mtspr SPRN_##exc_lvl_srr0,r9; \
1056 mtspr SPRN_##exc_lvl_srr1,r10;
1058 #if defined(CONFIG_PPC_BOOK3E_MMU)
1059 #ifdef CONFIG_PHYS_64BIT
1060 #define RESTORE_MAS7 \
1062 mtspr SPRN_MAS7,r11;
1064 #define RESTORE_MAS7
1065 #endif /* CONFIG_PHYS_64BIT */
1066 #define RESTORE_MMU_REGS \
1070 mtspr SPRN_MAS0,r9; \
1072 mtspr SPRN_MAS1,r10; \
1074 mtspr SPRN_MAS2,r11; \
1075 mtspr SPRN_MAS3,r9; \
1076 mtspr SPRN_MAS6,r10; \
1078 #elif defined(CONFIG_44x)
1079 #define RESTORE_MMU_REGS \
1081 mtspr SPRN_MMUCR,r9;
1083 #define RESTORE_MMU_REGS
1087 .globl ret_from_crit_exc
1089 mfspr r9,SPRN_SPRG_THREAD
1090 lis r10,saved_ksp_limit@ha;
1091 lwz r10,saved_ksp_limit@l(r10);
1093 stw r10,KSP_LIMIT(r9)
1094 lis r9,crit_srr0@ha;
1095 lwz r9,crit_srr0@l(r9);
1096 lis r10,crit_srr1@ha;
1097 lwz r10,crit_srr1@l(r10);
1099 mtspr SPRN_SRR1,r10;
1100 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1101 #endif /* CONFIG_40x */
1104 .globl ret_from_crit_exc
1106 mfspr r9,SPRN_SPRG_THREAD
1107 lwz r10,SAVED_KSP_LIMIT(r1)
1108 stw r10,KSP_LIMIT(r9)
1109 RESTORE_xSRR(SRR0,SRR1);
1111 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
1113 .globl ret_from_debug_exc
1115 mfspr r9,SPRN_SPRG_THREAD
1116 lwz r10,SAVED_KSP_LIMIT(r1)
1117 stw r10,KSP_LIMIT(r9)
1118 lwz r9,THREAD_INFO-THREAD(r9)
1119 CURRENT_THREAD_INFO(r10, r1)
1120 lwz r10,TI_PREEMPT(r10)
1121 stw r10,TI_PREEMPT(r9)
1122 RESTORE_xSRR(SRR0,SRR1);
1123 RESTORE_xSRR(CSRR0,CSRR1);
1125 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
1127 .globl ret_from_mcheck_exc
1128 ret_from_mcheck_exc:
1129 mfspr r9,SPRN_SPRG_THREAD
1130 lwz r10,SAVED_KSP_LIMIT(r1)
1131 stw r10,KSP_LIMIT(r9)
1132 RESTORE_xSRR(SRR0,SRR1);
1133 RESTORE_xSRR(CSRR0,CSRR1);
1134 RESTORE_xSRR(DSRR0,DSRR1);
1136 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
1137 #endif /* CONFIG_BOOKE */
1140 * Load the DBCR0 value for a task that is being ptraced,
1141 * having first saved away the global DBCR0. Note that r0
1142 * has the dbcr0 value to set upon entry to this.
1145 mfmsr r10 /* first disable debug exceptions */
1146 rlwinm r10,r10,0,~MSR_DE
1149 mfspr r10,SPRN_DBCR0
1150 lis r11,global_dbcr0@ha
1151 addi r11,r11,global_dbcr0@l
1153 CURRENT_THREAD_INFO(r9, r1)
1164 mtspr SPRN_DBSR,r11 /* clear all pending debug events */
1172 #endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
1174 do_work: /* r10 contains MSR_KERNEL here */
1175 andi. r0,r9,_TIF_NEED_RESCHED
1178 do_resched: /* r10 contains MSR_KERNEL here */
1179 /* Note: We don't need to inform lockdep that we are enabling
1180 * interrupts here. As far as it knows, they are already enabled
1184 MTMSRD(r10) /* hard-enable interrupts */
1187 /* Note: And we don't tell it we are disabling them again
1188 * neither. Those disable/enable cycles used to peek at
1189 * TI_FLAGS aren't advertised.
1191 LOAD_MSR_KERNEL(r10,MSR_KERNEL)
1193 MTMSRD(r10) /* disable interrupts */
1194 CURRENT_THREAD_INFO(r9, r1)
1196 andi. r0,r9,_TIF_NEED_RESCHED
1198 andi. r0,r9,_TIF_USER_WORK_MASK
1200 do_user_signal: /* r10 contains MSR_KERNEL here */
1203 MTMSRD(r10) /* hard-enable interrupts */
1204 /* save r13-r31 in the exception frame, if not already done */
1211 2: addi r3,r1,STACK_FRAME_OVERHEAD
1218 * We come here when we are at the end of handling an exception
1219 * that occurred at a place where taking an exception will lose
1220 * state information, such as the contents of SRR0 and SRR1.
1223 lis r10,exc_exit_restart_end@ha
1224 addi r10,r10,exc_exit_restart_end@l
1227 lis r11,exc_exit_restart@ha
1228 addi r11,r11,exc_exit_restart@l
1231 lis r10,ee_restarts@ha
1232 lwz r12,ee_restarts@l(r10)
1234 stw r12,ee_restarts@l(r10)
1235 mr r12,r11 /* restart at exc_exit_restart */
1237 3: /* OK, we can't recover, kill this process */
1238 /* but the 601 doesn't implement the RI bit, so assume it's OK */
1241 END_FTR_SECTION_IFSET(CPU_FTR_601)
1248 4: addi r3,r1,STACK_FRAME_OVERHEAD
1249 bl nonrecoverable_exception
1250 /* shouldn't return */
1260 * PROM code for specific machines follows. Put it
1261 * here so it's easy to add arch-specific sections later.
1264 #ifdef CONFIG_PPC_RTAS
1266 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
1267 * called with the MMU off.
1270 stwu r1,-INT_FRAME_SIZE(r1)
1272 stw r0,INT_FRAME_SIZE+4(r1)
1273 LOAD_REG_ADDR(r4, rtas)
1274 lis r6,1f@ha /* physical return address for rtas */
1278 lwz r8,RTASENTRY(r4)
1282 LOAD_MSR_KERNEL(r0,MSR_KERNEL)
1283 SYNC /* disable interrupts so SRR0/1 */
1284 MTMSRD(r0) /* don't get trashed */
1285 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1287 mtspr SPRN_SPRG_RTAS,r7
1292 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */
1293 lwz r9,8(r9) /* original msr value */
1295 addi r1,r1,INT_FRAME_SIZE
1297 mtspr SPRN_SPRG_RTAS,r0
1300 RFI /* return to caller */
1302 .globl machine_check_in_rtas
1303 machine_check_in_rtas:
1305 /* XXX load up BATs and panic */
1307 #endif /* CONFIG_PPC_RTAS */
1309 #ifdef CONFIG_FUNCTION_TRACER
1310 #ifdef CONFIG_DYNAMIC_FTRACE
1314 * It is required that _mcount on PPC32 must preserve the
1315 * link register. But we have r0 to play with. We use r0
1316 * to push the return address back to the caller of mcount
1317 * into the ctr register, restore the link register and
1318 * then jump back using the ctr register.
1326 _GLOBAL(ftrace_caller)
1328 /* r3 ends up with link register */
1329 subi r3, r3, MCOUNT_INSN_SIZE
1334 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1335 .globl ftrace_graph_call
1338 _GLOBAL(ftrace_graph_stub)
1340 MCOUNT_RESTORE_FRAME
1341 /* old link register ends up in ctr reg */
1349 subi r3, r3, MCOUNT_INSN_SIZE
1350 LOAD_REG_ADDR(r5, ftrace_trace_function)
1357 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1358 b ftrace_graph_caller
1360 MCOUNT_RESTORE_FRAME
1364 _GLOBAL(ftrace_stub)
1367 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1368 _GLOBAL(ftrace_graph_caller)
1369 /* load r4 with local address */
1371 subi r4, r4, MCOUNT_INSN_SIZE
1373 /* get the parent address */
1376 bl prepare_ftrace_return
1379 MCOUNT_RESTORE_FRAME
1380 /* old link register ends up in ctr reg */
1383 _GLOBAL(return_to_handler)
1384 /* need to save return values */
1391 bl ftrace_return_to_handler
1394 /* return value has real return address */
1402 /* Jump back to real return address */
1404 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
1406 #endif /* CONFIG_MCOUNT */