4 #include <linux/compiler.h>
5 #include <linux/types.h>
6 #include <linux/errno.h>
10 * USB Controller pram common to QE and CPM.
24 /* Fields down below are QE-only */
29 } __attribute__ ((packed));
32 * Function code bits, usually generic to devices.
35 #define CPMFCR_GBL ((u_char)0x00) /* Flag doesn't exist in CPM1 */
36 #define CPMFCR_TC2 ((u_char)0x00) /* Flag doesn't exist in CPM1 */
37 #define CPMFCR_DTB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
38 #define CPMFCR_BDB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
40 #define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
41 #define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
42 #define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
43 #define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
45 #define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
47 /* Opcodes common to CPM1 and CPM2
49 #define CPM_CR_INIT_TRX ((ushort)0x0000)
50 #define CPM_CR_INIT_RX ((ushort)0x0001)
51 #define CPM_CR_INIT_TX ((ushort)0x0002)
52 #define CPM_CR_HUNT_MODE ((ushort)0x0003)
53 #define CPM_CR_STOP_TX ((ushort)0x0004)
54 #define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
55 #define CPM_CR_RESTART_TX ((ushort)0x0006)
56 #define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
57 #define CPM_CR_SET_GADDR ((ushort)0x0008)
58 #define CPM_CR_SET_TIMER ((ushort)0x0008)
59 #define CPM_CR_STOP_IDMA ((ushort)0x000b)
61 /* Buffer descriptors used by many of the CPM protocols. */
62 typedef struct cpm_buf_desc {
63 ushort cbd_sc; /* Status and Control */
64 ushort cbd_datlen; /* Data length in buffer */
65 uint cbd_bufaddr; /* Buffer address in host memory */
68 /* Buffer descriptor control/status used by serial
71 #define BD_SC_EMPTY (0x8000) /* Receive is empty */
72 #define BD_SC_READY (0x8000) /* Transmit is ready */
73 #define BD_SC_WRAP (0x2000) /* Last buffer descriptor */
74 #define BD_SC_INTRPT (0x1000) /* Interrupt on change */
75 #define BD_SC_LAST (0x0800) /* Last buffer in frame */
76 #define BD_SC_TC (0x0400) /* Transmit CRC */
77 #define BD_SC_CM (0x0200) /* Continous mode */
78 #define BD_SC_ID (0x0100) /* Rec'd too many idles */
79 #define BD_SC_P (0x0100) /* xmt preamble */
80 #define BD_SC_BR (0x0020) /* Break received */
81 #define BD_SC_FR (0x0010) /* Framing error */
82 #define BD_SC_PR (0x0008) /* Parity error */
83 #define BD_SC_NAK (0x0004) /* NAK - did not respond */
84 #define BD_SC_OV (0x0002) /* Overrun */
85 #define BD_SC_UN (0x0002) /* Underrun */
86 #define BD_SC_CD (0x0001) /* */
87 #define BD_SC_CL (0x0001) /* Collision */
89 /* Buffer descriptor control/status used by Ethernet receive.
90 * Common to SCC and FCC.
92 #define BD_ENET_RX_EMPTY (0x8000)
93 #define BD_ENET_RX_WRAP (0x2000)
94 #define BD_ENET_RX_INTR (0x1000)
95 #define BD_ENET_RX_LAST (0x0800)
96 #define BD_ENET_RX_FIRST (0x0400)
97 #define BD_ENET_RX_MISS (0x0100)
98 #define BD_ENET_RX_BC (0x0080) /* FCC Only */
99 #define BD_ENET_RX_MC (0x0040) /* FCC Only */
100 #define BD_ENET_RX_LG (0x0020)
101 #define BD_ENET_RX_NO (0x0010)
102 #define BD_ENET_RX_SH (0x0008)
103 #define BD_ENET_RX_CR (0x0004)
104 #define BD_ENET_RX_OV (0x0002)
105 #define BD_ENET_RX_CL (0x0001)
106 #define BD_ENET_RX_STATS (0x01ff) /* All status bits */
108 /* Buffer descriptor control/status used by Ethernet transmit.
109 * Common to SCC and FCC.
111 #define BD_ENET_TX_READY (0x8000)
112 #define BD_ENET_TX_PAD (0x4000)
113 #define BD_ENET_TX_WRAP (0x2000)
114 #define BD_ENET_TX_INTR (0x1000)
115 #define BD_ENET_TX_LAST (0x0800)
116 #define BD_ENET_TX_TC (0x0400)
117 #define BD_ENET_TX_DEF (0x0200)
118 #define BD_ENET_TX_HB (0x0100)
119 #define BD_ENET_TX_LC (0x0080)
120 #define BD_ENET_TX_RL (0x0040)
121 #define BD_ENET_TX_RCMASK (0x003c)
122 #define BD_ENET_TX_UN (0x0002)
123 #define BD_ENET_TX_CSL (0x0001)
124 #define BD_ENET_TX_STATS (0x03ff) /* All status bits */
126 /* Buffer descriptor control/status used by Transparent mode SCC.
128 #define BD_SCC_TX_LAST (0x0800)
130 /* Buffer descriptor control/status used by I2C.
132 #define BD_I2C_START (0x0400)
134 int cpm_muram_init(void);
136 #if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
137 unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
138 int cpm_muram_free(unsigned long offset);
139 unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
140 void __iomem *cpm_muram_addr(unsigned long offset);
141 unsigned long cpm_muram_offset(void __iomem *addr);
142 dma_addr_t cpm_muram_dma(void __iomem *addr);
144 static inline unsigned long cpm_muram_alloc(unsigned long size,
150 static inline int cpm_muram_free(unsigned long offset)
155 static inline unsigned long cpm_muram_alloc_fixed(unsigned long offset,
161 static inline void __iomem *cpm_muram_addr(unsigned long offset)
166 static inline unsigned long cpm_muram_offset(void __iomem *addr)
171 static inline dma_addr_t cpm_muram_dma(void __iomem *addr)
175 #endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */
178 int cpm_command(u32 command, u8 opcode);
180 static inline int cpm_command(u32 command, u8 opcode)
184 #endif /* CONFIG_CPM */
186 int cpm2_gpiochip_add32(struct device_node *np);