2 * Cell Broadband Engine Performance Monitor
4 * (C) Copyright IBM Corporation 2006
7 * David Erb (djerb@us.ibm.com)
8 * Kevin Corry (kevcorry@us.ibm.com)
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #ifndef __ASM_CELL_PMU_H__
26 #define __ASM_CELL_PMU_H__
28 /* The Cell PMU has four hardware performance counters, which can be
29 * configured as four 32-bit counters or eight 16-bit counters.
31 #define NR_PHYS_CTRS 4
32 #define NR_CTRS (NR_PHYS_CTRS * 2)
34 /* Macros for the pm_control register. */
35 #define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
36 #define CBE_PM_ENABLE_PERF_MON 0x80000000
37 #define CBE_PM_STOP_AT_MAX 0x40000000
38 #define CBE_PM_TRACE_MODE_GET(pm_control) (((pm_control) >> 28) & 0x3)
39 #define CBE_PM_TRACE_MODE_SET(mode) (((mode) & 0x3) << 28)
40 #define CBE_PM_COUNT_MODE_SET(count) (((count) & 0x3) << 18)
41 #define CBE_PM_FREEZE_ALL_CTRS 0x00100000
42 #define CBE_PM_ENABLE_EXT_TRACE 0x00008000
44 /* Macros for the trace_address register. */
45 #define CBE_PM_TRACE_BUF_FULL 0x00000800
46 #define CBE_PM_TRACE_BUF_EMPTY 0x00000400
47 #define CBE_PM_TRACE_BUF_DATA_COUNT(ta) ((ta) & 0x3ff)
48 #define CBE_PM_TRACE_BUF_MAX_COUNT 0x400
50 /* Macros for the pm07_control registers. */
51 #define CBE_PM_CTR_INPUT_MUX(pm07_control) (((pm07_control) >> 26) & 0x3f)
52 #define CBE_PM_CTR_INPUT_CONTROL 0x02000000
53 #define CBE_PM_CTR_POLARITY 0x01000000
54 #define CBE_PM_CTR_COUNT_CYCLES 0x00800000
55 #define CBE_PM_CTR_ENABLE 0x00400000
56 #define PM07_CTR_INPUT_MUX(x) (((x) & 0x3F) << 26)
57 #define PM07_CTR_INPUT_CONTROL(x) (((x) & 1) << 25)
58 #define PM07_CTR_POLARITY(x) (((x) & 1) << 24)
59 #define PM07_CTR_COUNT_CYCLES(x) (((x) & 1) << 23)
60 #define PM07_CTR_ENABLE(x) (((x) & 1) << 22)
62 /* Macros for the pm_status register. */
63 #define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7)))
76 /* Routines for reading/writing the PMU registers. */
77 extern u32 cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);
78 extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
79 extern u32 cbe_read_ctr(u32 cpu, u32 ctr);
80 extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
82 extern u32 cbe_read_pm07_control(u32 cpu, u32 ctr);
83 extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
84 extern u32 cbe_read_pm(u32 cpu, enum pm_reg_name reg);
85 extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
87 extern u32 cbe_get_ctr_size(u32 cpu, u32 phys_ctr);
88 extern void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
90 extern void cbe_enable_pm(u32 cpu);
91 extern void cbe_disable_pm(u32 cpu);
93 extern void cbe_read_trace_buffer(u32 cpu, u64 *buf);
95 extern void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
96 extern void cbe_disable_pm_interrupts(u32 cpu);
97 extern u32 cbe_get_and_clear_pm_interrupts(u32 cpu);
98 extern void cbe_sync_irq(int node);
100 #define CBE_COUNT_SUPERVISOR_MODE 0
101 #define CBE_COUNT_HYPERVISOR_MODE 1
102 #define CBE_COUNT_PROBLEM_MODE 2
103 #define CBE_COUNT_ALL_MODES 3
105 #endif /* __ASM_CELL_PMU_H__ */