2 * P5020 Silicon Device Tree Source
4 * Copyright 2010-2011 Freescale Semiconductor Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
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12 * documentation and/or other materials provided with the distribution.
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14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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38 compatible = "fsl,P5020";
41 interrupt-parent = <&mpic>;
84 cpu0: PowerPC,e5500@0 {
87 next-level-cache = <&L2_0>;
89 next-level-cache = <&cpc>;
92 cpu1: PowerPC,e5500@1 {
95 next-level-cache = <&L2_1>;
97 next-level-cache = <&cpc>;
102 dcsr: dcsr@f00000000 {
103 #address-cells = <1>;
105 compatible = "fsl,dcsr", "simple-bus";
108 compatible = "fsl,dcsr-epu";
109 interrupts = <52 2 0 0
112 interrupt-parent = <&mpic>;
116 compatible = "fsl,dcsr-npc";
117 reg = <0x1000 0x1000 0x1000000 0x8000>;
120 compatible = "fsl,dcsr-nxc";
121 reg = <0x2000 0x1000>;
124 compatible = "fsl,dcsr-corenet";
125 reg = <0x8000 0x1000 0xB0000 0x1000>;
128 compatible = "fsl,p5020-dcsr-dpaa", "fsl,dcsr-dpaa";
129 reg = <0x9000 0x1000>;
132 compatible = "fsl,p5020-dcsr-ocn", "fsl,dcsr-ocn";
133 reg = <0x11000 0x1000>;
136 compatible = "fsl,dcsr-ddr";
137 dev-handle = <&ddr1>;
138 reg = <0x12000 0x1000>;
141 compatible = "fsl,dcsr-ddr";
142 dev-handle = <&ddr2>;
143 reg = <0x13000 0x1000>;
146 compatible = "fsl,p5020-dcsr-nal", "fsl,dcsr-nal";
147 reg = <0x18000 0x1000>;
150 compatible = "fsl,p5020-dcsr-rcpm", "fsl,dcsr-rcpm";
151 reg = <0x22000 0x1000>;
153 dcsr-cpu-sb-proxy@40000 {
154 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
155 cpu-handle = <&cpu0>;
156 reg = <0x40000 0x1000>;
158 dcsr-cpu-sb-proxy@41000 {
159 compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
160 cpu-handle = <&cpu1>;
161 reg = <0x41000 0x1000>;
166 #address-cells = <1>;
169 compatible = "simple-bus";
170 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
171 reg = <0xf 0xfe000000 0 0x00001000>;
174 compatible = "fsl,soc-sram-error";
175 interrupts = <16 2 1 29>;
179 compatible = "fsl,corenet-law";
184 ddr1: memory-controller@8000 {
185 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
186 reg = <0x8000 0x1000>;
187 interrupts = <16 2 1 23>;
190 ddr2: memory-controller@9000 {
191 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
192 reg = <0x9000 0x1000>;
193 interrupts = <16 2 1 22>;
196 cpc: l3-cache-controller@10000 {
197 compatible = "fsl,p5020-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
198 reg = <0x10000 0x1000
200 interrupts = <16 2 1 27
205 compatible = "fsl,corenet-cf";
206 reg = <0x18000 0x1000>;
207 interrupts = <16 2 1 31>;
208 fsl,ccf-num-csdids = <32>;
209 fsl,ccf-num-snoopids = <32>;
213 compatible = "fsl,pamu-v1.0", "fsl,pamu";
214 reg = <0x20000 0x4000>;
221 clock-frequency = <0>;
222 interrupt-controller;
223 #address-cells = <0>;
224 #interrupt-cells = <4>;
225 reg = <0x40000 0x40000>;
226 compatible = "fsl,mpic", "chrp,open-pic";
227 device_type = "open-pic";
231 compatible = "fsl,mpic-msi";
232 reg = <0x41600 0x200>;
233 msi-available-ranges = <0 0x100>;
246 compatible = "fsl,mpic-msi";
247 reg = <0x41800 0x200>;
248 msi-available-ranges = <0 0x100>;
261 compatible = "fsl,mpic-msi";
262 reg = <0x41a00 0x200>;
263 msi-available-ranges = <0 0x100>;
275 guts: global-utilities@e0000 {
276 compatible = "fsl,qoriq-device-config-1.0";
277 reg = <0xe0000 0xe00>;
280 fsl,liodn-bits = <12>;
283 pins: global-utilities@e0e00 {
284 compatible = "fsl,qoriq-pin-control-1.0";
285 reg = <0xe0e00 0x200>;
289 clockgen: global-utilities@e1000 {
290 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
291 reg = <0xe1000 0x1000>;
292 clock-frequency = <0>;
295 rcpm: global-utilities@e2000 {
296 compatible = "fsl,qoriq-rcpm-1.0";
297 reg = <0xe2000 0x1000>;
302 compatible = "fsl,p5020-sfp", "fsl,qoriq-sfp-1.0";
303 reg = <0xe8000 0x1000>;
306 serdes: serdes@ea000 {
307 compatible = "fsl,p5020-serdes";
308 reg = <0xea000 0x1000>;
312 #address-cells = <1>;
314 compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
315 reg = <0x100300 0x4>;
316 ranges = <0x0 0x100100 0x200>;
319 compatible = "fsl,p5020-dma-channel",
320 "fsl,eloplus-dma-channel";
323 interrupts = <28 2 0 0>;
326 compatible = "fsl,p5020-dma-channel",
327 "fsl,eloplus-dma-channel";
330 interrupts = <29 2 0 0>;
333 compatible = "fsl,p5020-dma-channel",
334 "fsl,eloplus-dma-channel";
337 interrupts = <30 2 0 0>;
340 compatible = "fsl,p5020-dma-channel",
341 "fsl,eloplus-dma-channel";
344 interrupts = <31 2 0 0>;
349 #address-cells = <1>;
351 compatible = "fsl,p5020-dma", "fsl,eloplus-dma";
352 reg = <0x101300 0x4>;
353 ranges = <0x0 0x101100 0x200>;
356 compatible = "fsl,p5020-dma-channel",
357 "fsl,eloplus-dma-channel";
360 interrupts = <32 2 0 0>;
363 compatible = "fsl,p5020-dma-channel",
364 "fsl,eloplus-dma-channel";
367 interrupts = <33 2 0 0>;
370 compatible = "fsl,p5020-dma-channel",
371 "fsl,eloplus-dma-channel";
374 interrupts = <34 2 0 0>;
377 compatible = "fsl,p5020-dma-channel",
378 "fsl,eloplus-dma-channel";
381 interrupts = <35 2 0 0>;
386 #address-cells = <1>;
388 compatible = "fsl,p5020-espi", "fsl,mpc8536-espi";
389 reg = <0x110000 0x1000>;
390 interrupts = <53 0x2 0 0>;
391 fsl,espi-num-chipselects = <4>;
395 compatible = "fsl,p5020-esdhc", "fsl,esdhc";
396 reg = <0x114000 0x1000>;
397 interrupts = <48 2 0 0>;
399 clock-frequency = <0>;
403 #address-cells = <1>;
406 compatible = "fsl-i2c";
407 reg = <0x118000 0x100>;
408 interrupts = <38 2 0 0>;
413 #address-cells = <1>;
416 compatible = "fsl-i2c";
417 reg = <0x118100 0x100>;
418 interrupts = <38 2 0 0>;
423 #address-cells = <1>;
426 compatible = "fsl-i2c";
427 reg = <0x119000 0x100>;
428 interrupts = <39 2 0 0>;
433 #address-cells = <1>;
436 compatible = "fsl-i2c";
437 reg = <0x119100 0x100>;
438 interrupts = <39 2 0 0>;
442 serial0: serial@11c500 {
444 device_type = "serial";
445 compatible = "ns16550";
446 reg = <0x11c500 0x100>;
447 clock-frequency = <0>;
448 interrupts = <36 2 0 0>;
451 serial1: serial@11c600 {
453 device_type = "serial";
454 compatible = "ns16550";
455 reg = <0x11c600 0x100>;
456 clock-frequency = <0>;
457 interrupts = <36 2 0 0>;
460 serial2: serial@11d500 {
462 device_type = "serial";
463 compatible = "ns16550";
464 reg = <0x11d500 0x100>;
465 clock-frequency = <0>;
466 interrupts = <37 2 0 0>;
469 serial3: serial@11d600 {
471 device_type = "serial";
472 compatible = "ns16550";
473 reg = <0x11d600 0x100>;
474 clock-frequency = <0>;
475 interrupts = <37 2 0 0>;
479 compatible = "fsl,p5020-gpio", "fsl,qoriq-gpio";
480 reg = <0x130000 0x1000>;
481 interrupts = <55 2 0 0>;
487 compatible = "fsl,p5020-usb2-mph",
488 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
489 reg = <0x210000 0x1000>;
490 #address-cells = <1>;
492 interrupts = <44 0x2 0 0>;
498 compatible = "fsl,p5020-usb2-dr",
499 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
500 reg = <0x211000 0x1000>;
501 #address-cells = <1>;
503 interrupts = <45 0x2 0 0>;
509 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
510 reg = <0x220000 0x1000>;
511 interrupts = <68 0x2 0 0>;
515 compatible = "fsl,p5020-sata", "fsl,pq-sata-v2";
516 reg = <0x221000 0x1000>;
517 interrupts = <69 0x2 0 0>;
520 crypto: crypto@300000 {
521 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
522 #address-cells = <1>;
524 reg = <0x300000 0x10000>;
525 ranges = <0 0x300000 0x10000>;
526 interrupts = <92 2 0 0>;
529 compatible = "fsl,sec-v4.2-job-ring",
530 "fsl,sec-v4.0-job-ring";
531 reg = <0x1000 0x1000>;
532 interrupts = <88 2 0 0>;
536 compatible = "fsl,sec-v4.2-job-ring",
537 "fsl,sec-v4.0-job-ring";
538 reg = <0x2000 0x1000>;
539 interrupts = <89 2 0 0>;
543 compatible = "fsl,sec-v4.2-job-ring",
544 "fsl,sec-v4.0-job-ring";
545 reg = <0x3000 0x1000>;
546 interrupts = <90 2 0 0>;
550 compatible = "fsl,sec-v4.2-job-ring",
551 "fsl,sec-v4.0-job-ring";
552 reg = <0x4000 0x1000>;
553 interrupts = <91 2 0 0>;
557 compatible = "fsl,sec-v4.2-rtic",
559 #address-cells = <1>;
561 reg = <0x6000 0x100>;
562 ranges = <0x0 0x6100 0xe00>;
565 compatible = "fsl,sec-v4.2-rtic-memory",
566 "fsl,sec-v4.0-rtic-memory";
567 reg = <0x00 0x20 0x100 0x80>;
571 compatible = "fsl,sec-v4.2-rtic-memory",
572 "fsl,sec-v4.0-rtic-memory";
573 reg = <0x20 0x20 0x200 0x80>;
577 compatible = "fsl,sec-v4.2-rtic-memory",
578 "fsl,sec-v4.0-rtic-memory";
579 reg = <0x40 0x20 0x300 0x80>;
583 compatible = "fsl,sec-v4.2-rtic-memory",
584 "fsl,sec-v4.0-rtic-memory";
585 reg = <0x60 0x20 0x500 0x80>;
590 sec_mon: sec_mon@314000 {
591 compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
592 reg = <0x314000 0x1000>;
593 interrupts = <93 2 0 0>;
598 rapidio0: rapidio@ffe0c0000
602 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
603 interrupts = <25 2 0 0>;
604 #address-cells = <2>;
608 pci0: pcie@ffe200000 {
609 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
612 #address-cells = <3>;
613 bus-range = <0x0 0xff>;
614 clock-frequency = <0x1fca055>;
616 interrupts = <16 2 1 15>;
620 #interrupt-cells = <1>;
622 #address-cells = <3>;
624 interrupts = <16 2 1 15>;
625 interrupt-map-mask = <0xf800 0 0 7>;
628 0000 0 0 1 &mpic 40 1 0 0
629 0000 0 0 2 &mpic 1 1 0 0
630 0000 0 0 3 &mpic 2 1 0 0
631 0000 0 0 4 &mpic 3 1 0 0
636 pci1: pcie@ffe201000 {
637 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
640 #address-cells = <3>;
641 bus-range = <0 0xff>;
642 clock-frequency = <0x1fca055>;
644 interrupts = <16 2 1 14>;
647 #interrupt-cells = <1>;
649 #address-cells = <3>;
651 interrupts = <16 2 1 14>;
652 interrupt-map-mask = <0xf800 0 0 7>;
655 0000 0 0 1 &mpic 41 1 0 0
656 0000 0 0 2 &mpic 5 1 0 0
657 0000 0 0 3 &mpic 6 1 0 0
658 0000 0 0 4 &mpic 7 1 0 0
663 pci2: pcie@ffe202000 {
664 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
667 #address-cells = <3>;
668 bus-range = <0x0 0xff>;
669 clock-frequency = <0x1fca055>;
671 interrupts = <16 2 1 13>;
674 #interrupt-cells = <1>;
676 #address-cells = <3>;
678 interrupts = <16 2 1 13>;
679 interrupt-map-mask = <0xf800 0 0 7>;
682 0000 0 0 1 &mpic 42 1 0 0
683 0000 0 0 2 &mpic 9 1 0 0
684 0000 0 0 3 &mpic 10 1 0 0
685 0000 0 0 4 &mpic 11 1 0 0
690 pci3: pcie@ffe203000 {
691 compatible = "fsl,p5020-pcie", "fsl,qoriq-pcie-v2.2";
694 #address-cells = <3>;
695 bus-range = <0x0 0xff>;
696 clock-frequency = <0x1fca055>;
698 interrupts = <16 2 1 12>;
701 #interrupt-cells = <1>;
703 #address-cells = <3>;
705 interrupts = <16 2 1 12>;
706 interrupt-map-mask = <0xf800 0 0 7>;
709 0000 0 0 1 &mpic 43 1 0 0
710 0000 0 0 2 &mpic 0 1 0 0
711 0000 0 0 3 &mpic 4 1 0 0
712 0000 0 0 4 &mpic 8 1 0 0