arch/powerpc/boot/dts/p3041si.dtsi

   1 /*
   2  * P3041 Silicon Device Tree Source
   3  *
   4  * Copyright 2010-2011 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 /dts-v1/;
  36
  37 / {
  38         compatible = "fsl,P3041";
  39         #address-cells = <2>;
  40         #size-cells = <2>;
  41         interrupt-parent = <&mpic>;
  42
  43         aliases {
  44                 ccsr = &soc;
  45
  46                 serial0 = &serial0;
  47                 serial1 = &serial1;
  48                 serial2 = &serial2;
  49                 serial3 = &serial3;
  50                 pci0 = &pci0;
  51                 pci1 = &pci1;
  52                 pci2 = &pci2;
  53                 pci3 = &pci3;
  54                 usb0 = &usb0;
  55                 usb1 = &usb1;
  56                 dma0 = &dma0;
  57                 dma1 = &dma1;
  58                 sdhc = &sdhc;
  59                 msi0 = &msi0;
  60                 msi1 = &msi1;
  61                 msi2 = &msi2;
  62
  63                 crypto = &crypto;
  64                 sec_jr0 = &sec_jr0;
  65                 sec_jr1 = &sec_jr1;
  66                 sec_jr2 = &sec_jr2;
  67                 sec_jr3 = &sec_jr3;
  68                 rtic_a = &rtic_a;
  69                 rtic_b = &rtic_b;
  70                 rtic_c = &rtic_c;
  71                 rtic_d = &rtic_d;
  72                 sec_mon = &sec_mon;
  73
  74 /*
  75                 rio0 = &rapidio0;
  76  */
  77         };
  78
  79         cpus {
  80                 #address-cells = <1>;
  81                 #size-cells = <0>;
  82
  83                 cpu0: PowerPC,e500mc@0 {
  84                         device_type = "cpu";
  85                         reg = <0>;
  86                         next-level-cache = <&L2_0>;
  87                         L2_0: l2-cache {
  88                                 next-level-cache = <&cpc>;
  89                         };
  90                 };
  91                 cpu1: PowerPC,e500mc@1 {
  92                         device_type = "cpu";
  93                         reg = <1>;
  94                         next-level-cache = <&L2_1>;
  95                         L2_1: l2-cache {
  96                                 next-level-cache = <&cpc>;
  97                         };
  98                 };
  99                 cpu2: PowerPC,e500mc@2 {
 100                         device_type = "cpu";
 101                         reg = <2>;
 102                         next-level-cache = <&L2_2>;
 103                         L2_2: l2-cache {
 104                                 next-level-cache = <&cpc>;
 105                         };
 106                 };
 107                 cpu3: PowerPC,e500mc@3 {
 108                         device_type = "cpu";
 109                         reg = <3>;
 110                         next-level-cache = <&L2_3>;
 111                         L2_3: l2-cache {
 112                                 next-level-cache = <&cpc>;
 113                         };
 114                 };
 115         };
 116
 117         soc: soc@ffe000000 {
 118                 #address-cells = <1>;
 119                 #size-cells = <1>;
 120                 device_type = "soc";
 121                 compatible = "simple-bus";
 122                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
 123                 reg = <0xf 0xfe000000 0 0x00001000>;
 124
 125                 soc-sram-error {
 126                         compatible = "fsl,soc-sram-error";
 127                         interrupts = <16 2 1 29>;
 128                 };
 129
 130                 corenet-law@0 {
 131                         compatible = "fsl,corenet-law";
 132                         reg = <0x0 0x1000>;
 133                         fsl,num-laws = <32>;
 134                 };
 135
 136                 memory-controller@8000 {
 137                         compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
 138                         reg = <0x8000 0x1000>;
 139                         interrupts = <16 2 1 23>;
 140                 };
 141
 142                 cpc: l3-cache-controller@10000 {
 143                         compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
 144                         reg = <0x10000 0x1000>;
 145                         interrupts = <16 2 1 27>;
 146                 };
 147
 148                 corenet-cf@18000 {
 149                         compatible = "fsl,corenet-cf";
 150                         reg = <0x18000 0x1000>;
 151                         interrupts = <16 2 1 31>;
 152                         fsl,ccf-num-csdids = <32>;
 153                         fsl,ccf-num-snoopids = <32>;
 154                 };
 155
 156                 iommu@20000 {
 157                         compatible = "fsl,pamu-v1.0", "fsl,pamu";
 158                         reg = <0x20000 0x4000>;
 159                         interrupts = <
 160                                 24 2 0 0
 161                                 16 2 1 30>;
 162                 };
 163
 164                 mpic: pic@40000 {
 165                         clock-frequency = <0>;
 166                         interrupt-controller;
 167                         #address-cells = <0>;
 168                         #interrupt-cells = <4>;
 169                         reg = <0x40000 0x40000>;
 170                         compatible = "fsl,mpic", "chrp,open-pic";
 171                         device_type = "open-pic";
 172                 };
 173
 174                 msi0: msi@41600 {
 175                         compatible = "fsl,mpic-msi";
 176                         reg = <0x41600 0x200>;
 177                         msi-available-ranges = <0 0x100>;
 178                         interrupts = <
 179                                 0xe0 0 0 0
 180                                 0xe1 0 0 0
 181                                 0xe2 0 0 0
 182                                 0xe3 0 0 0
 183                                 0xe4 0 0 0
 184                                 0xe5 0 0 0
 185                                 0xe6 0 0 0
 186                                 0xe7 0 0 0>;
 187                 };
 188
 189                 msi1: msi@41800 {
 190                         compatible = "fsl,mpic-msi";
 191                         reg = <0x41800 0x200>;
 192                         msi-available-ranges = <0 0x100>;
 193                         interrupts = <
 194                                 0xe8 0 0 0
 195                                 0xe9 0 0 0
 196                                 0xea 0 0 0
 197                                 0xeb 0 0 0
 198                                 0xec 0 0 0
 199                                 0xed 0 0 0
 200                                 0xee 0 0 0
 201                                 0xef 0 0 0>;
 202                 };
 203
 204                 msi2: msi@41a00 {
 205                         compatible = "fsl,mpic-msi";
 206                         reg = <0x41a00 0x200>;
 207                         msi-available-ranges = <0 0x100>;
 208                         interrupts = <
 209                                 0xf0 0 0 0
 210                                 0xf1 0 0 0
 211                                 0xf2 0 0 0
 212                                 0xf3 0 0 0
 213                                 0xf4 0 0 0
 214                                 0xf5 0 0 0
 215                                 0xf6 0 0 0
 216                                 0xf7 0 0 0>;
 217                 };
 218
 219                 guts: global-utilities@e0000 {
 220                         compatible = "fsl,qoriq-device-config-1.0";
 221                         reg = <0xe0000 0xe00>;
 222                         fsl,has-rstcr;
 223                         #sleep-cells = <1>;
 224                         fsl,liodn-bits = <12>;
 225                 };
 226
 227                 pins: global-utilities@e0e00 {
 228                         compatible = "fsl,qoriq-pin-control-1.0";
 229                         reg = <0xe0e00 0x200>;
 230                         #sleep-cells = <2>;
 231                 };
 232
 233                 clockgen: global-utilities@e1000 {
 234                         compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
 235                         reg = <0xe1000 0x1000>;
 236                         clock-frequency = <0>;
 237                 };
 238
 239                 rcpm: global-utilities@e2000 {
 240                         compatible = "fsl,qoriq-rcpm-1.0";
 241                         reg = <0xe2000 0x1000>;
 242                         #sleep-cells = <1>;
 243                 };
 244
 245                 sfp: sfp@e8000 {
 246                         compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
 247                         reg        = <0xe8000 0x1000>;
 248                 };
 249
 250                 serdes: serdes@ea000 {
 251                         compatible = "fsl,p3041-serdes";
 252                         reg        = <0xea000 0x1000>;
 253                 };
 254
 255                 dma0: dma@100300 {
 256                         #address-cells = <1>;
 257                         #size-cells = <1>;
 258                         compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
 259                         reg = <0x100300 0x4>;
 260                         ranges = <0x0 0x100100 0x200>;
 261                         cell-index = <0>;
 262                         dma-channel@0 {
 263                                 compatible = "fsl,p3041-dma-channel",
 264                                                 "fsl,eloplus-dma-channel";
 265                                 reg = <0x0 0x80>;
 266                                 cell-index = <0>;
 267                                 interrupts = <28 2 0 0>;
 268                         };
 269                         dma-channel@80 {
 270                                 compatible = "fsl,p3041-dma-channel",
 271                                                 "fsl,eloplus-dma-channel";
 272                                 reg = <0x80 0x80>;
 273                                 cell-index = <1>;
 274                                 interrupts = <29 2 0 0>;
 275                         };
 276                         dma-channel@100 {
 277                                 compatible = "fsl,p3041-dma-channel",
 278                                                 "fsl,eloplus-dma-channel";
 279                                 reg = <0x100 0x80>;
 280                                 cell-index = <2>;
 281                                 interrupts = <30 2 0 0>;
 282                         };
 283                         dma-channel@180 {
 284                                 compatible = "fsl,p3041-dma-channel",
 285                                                 "fsl,eloplus-dma-channel";
 286                                 reg = <0x180 0x80>;
 287                                 cell-index = <3>;
 288                                 interrupts = <31 2 0 0>;
 289                         };
 290                 };
 291
 292                 dma1: dma@101300 {
 293                         #address-cells = <1>;
 294                         #size-cells = <1>;
 295                         compatible = "fsl,p3041-dma", "fsl,eloplus-dma";
 296                         reg = <0x101300 0x4>;
 297                         ranges = <0x0 0x101100 0x200>;
 298                         cell-index = <1>;
 299                         dma-channel@0 {
 300                                 compatible = "fsl,p3041-dma-channel",
 301                                                 "fsl,eloplus-dma-channel";
 302                                 reg = <0x0 0x80>;
 303                                 cell-index = <0>;
 304                                 interrupts = <32 2 0 0>;
 305                         };
 306                         dma-channel@80 {
 307                                 compatible = "fsl,p3041-dma-channel",
 308                                                 "fsl,eloplus-dma-channel";
 309                                 reg = <0x80 0x80>;
 310                                 cell-index = <1>;
 311                                 interrupts = <33 2 0 0>;
 312                         };
 313                         dma-channel@100 {
 314                                 compatible = "fsl,p3041-dma-channel",
 315                                                 "fsl,eloplus-dma-channel";
 316                                 reg = <0x100 0x80>;
 317                                 cell-index = <2>;
 318                                 interrupts = <34 2 0 0>;
 319                         };
 320                         dma-channel@180 {
 321                                 compatible = "fsl,p3041-dma-channel",
 322                                                 "fsl,eloplus-dma-channel";
 323                                 reg = <0x180 0x80>;
 324                                 cell-index = <3>;
 325                                 interrupts = <35 2 0 0>;
 326                         };
 327                 };
 328
 329                 spi@110000 {
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                         compatible = "fsl,p3041-espi", "fsl,mpc8536-espi";
 333                         reg = <0x110000 0x1000>;
 334                         interrupts = <53 0x2 0 0>;
 335                         fsl,espi-num-chipselects = <4>;
 336                 };
 337
 338                 sdhc: sdhc@114000 {
 339                         compatible = "fsl,p3041-esdhc", "fsl,esdhc";
 340                         reg = <0x114000 0x1000>;
 341                         interrupts = <48 2 0 0>;
 342                         sdhci,auto-cmd12;
 343                         clock-frequency = <0>;
 344                 };
 345
 346                 i2c@118000 {
 347                         #address-cells = <1>;
 348                         #size-cells = <0>;
 349                         cell-index = <0>;
 350                         compatible = "fsl-i2c";
 351                         reg = <0x118000 0x100>;
 352                         interrupts = <38 2 0 0>;
 353                         dfsrr;
 354                 };
 355
 356                 i2c@118100 {
 357                         #address-cells = <1>;
 358                         #size-cells = <0>;
 359                         cell-index = <1>;
 360                         compatible = "fsl-i2c";
 361                         reg = <0x118100 0x100>;
 362                         interrupts = <38 2 0 0>;
 363                         dfsrr;
 364                 };
 365
 366                 i2c@119000 {
 367                         #address-cells = <1>;
 368                         #size-cells = <0>;
 369                         cell-index = <2>;
 370                         compatible = "fsl-i2c";
 371                         reg = <0x119000 0x100>;
 372                         interrupts = <39 2 0 0>;
 373                         dfsrr;
 374                 };
 375
 376                 i2c@119100 {
 377                         #address-cells = <1>;
 378                         #size-cells = <0>;
 379                         cell-index = <3>;
 380                         compatible = "fsl-i2c";
 381                         reg = <0x119100 0x100>;
 382                         interrupts = <39 2 0 0>;
 383                         dfsrr;
 384                 };
 385
 386                 serial0: serial@11c500 {
 387                         cell-index = <0>;
 388                         device_type = "serial";
 389                         compatible = "ns16550";
 390                         reg = <0x11c500 0x100>;
 391                         clock-frequency = <0>;
 392                         interrupts = <36 2 0 0>;
 393                 };
 394
 395                 serial1: serial@11c600 {
 396                         cell-index = <1>;
 397                         device_type = "serial";
 398                         compatible = "ns16550";
 399                         reg = <0x11c600 0x100>;
 400                         clock-frequency = <0>;
 401                         interrupts = <36 2 0 0>;
 402                 };
 403
 404                 serial2: serial@11d500 {
 405                         cell-index = <2>;
 406                         device_type = "serial";
 407                         compatible = "ns16550";
 408                         reg = <0x11d500 0x100>;
 409                         clock-frequency = <0>;
 410                         interrupts = <37 2 0 0>;
 411                 };
 412
 413                 serial3: serial@11d600 {
 414                         cell-index = <3>;
 415                         device_type = "serial";
 416                         compatible = "ns16550";
 417                         reg = <0x11d600 0x100>;
 418                         clock-frequency = <0>;
 419                         interrupts = <37 2 0 0>;
 420                 };
 421
 422                 gpio0: gpio@130000 {
 423                         compatible = "fsl,p3041-gpio", "fsl,qoriq-gpio";
 424                         reg = <0x130000 0x1000>;
 425                         interrupts = <55 2 0 0>;
 426                         #gpio-cells = <2>;
 427                         gpio-controller;
 428                 };
 429
 430                 usb0: usb@210000 {
 431                         compatible = "fsl,p3041-usb2-mph",
 432                                         "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
 433                         reg = <0x210000 0x1000>;
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                         interrupts = <44 0x2 0 0>;
 437                         phy_type = "utmi";
 438                         port0;
 439                 };
 440
 441                 usb1: usb@211000 {
 442                         compatible = "fsl,p3041-usb2-dr",
 443                                         "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
 444                         reg = <0x211000 0x1000>;
 445                         #address-cells = <1>;
 446                         #size-cells = <0>;
 447                         interrupts = <45 0x2 0 0>;
 448                         dr_mode = "host";
 449                         phy_type = "utmi";
 450                 };
 451
 452                 sata@220000 {
 453                         compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
 454                         reg = <0x220000 0x1000>;
 455                         interrupts = <68 0x2 0 0>;
 456                 };
 457
 458                 sata@221000 {
 459                         compatible = "fsl,p3041-sata", "fsl,pq-sata-v2";
 460                         reg = <0x221000 0x1000>;
 461                         interrupts = <69 0x2 0 0>;
 462                 };
 463
 464                 crypto: crypto@300000 {
 465                         compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
 466                         #address-cells = <1>;
 467                         #size-cells = <1>;
 468                         reg              = <0x300000 0x10000>;
 469                         ranges           = <0 0x300000 0x10000>;
 470                         interrupts       = <92 2 0 0>;
 471
 472                         sec_jr0: jr@1000 {
 473                                 compatible = "fsl,sec-v4.2-job-ring",
 474                                              "fsl,sec-v4.0-job-ring";
 475                                 reg = <0x1000 0x1000>;
 476                                 interrupts = <88 2 0 0>;
 477                         };
 478
 479                         sec_jr1: jr@2000 {
 480                                 compatible = "fsl,sec-v4.2-job-ring",
 481                                              "fsl,sec-v4.0-job-ring";
 482                                 reg = <0x2000 0x1000>;
 483                                 interrupts = <89 2 0 0>;
 484                         };
 485
 486                         sec_jr2: jr@3000 {
 487                                 compatible = "fsl,sec-v4.2-job-ring",
 488                                              "fsl,sec-v4.0-job-ring";
 489                                 reg = <0x3000 0x1000>;
 490                                 interrupts = <90 2 0 0>;
 491                         };
 492
 493                         sec_jr3: jr@4000 {
 494                                 compatible = "fsl,sec-v4.2-job-ring",
 495                                              "fsl,sec-v4.0-job-ring";
 496                                 reg = <0x4000 0x1000>;
 497                                 interrupts = <91 2 0 0>;
 498                         };
 499
 500                         rtic@6000 {
 501                                 compatible = "fsl,sec-v4.2-rtic",
 502                                              "fsl,sec-v4.0-rtic";
 503                                 #address-cells = <1>;
 504                                 #size-cells = <1>;
 505                                 reg = <0x6000 0x100>;
 506                                 ranges = <0x0 0x6100 0xe00>;
 507
 508                                 rtic_a: rtic-a@0 {
 509                                         compatible = "fsl,sec-v4.2-rtic-memory",
 510                                                      "fsl,sec-v4.0-rtic-memory";
 511                                         reg = <0x00 0x20 0x100 0x80>;
 512                                 };
 513
 514                                 rtic_b: rtic-b@20 {
 515                                         compatible = "fsl,sec-v4.2-rtic-memory",
 516                                                      "fsl,sec-v4.0-rtic-memory";
 517                                         reg = <0x20 0x20 0x200 0x80>;
 518                                 };
 519
 520                                 rtic_c: rtic-c@40 {
 521                                         compatible = "fsl,sec-v4.2-rtic-memory",
 522                                                      "fsl,sec-v4.0-rtic-memory";
 523                                         reg = <0x40 0x20 0x300 0x80>;
 524                                 };
 525
 526                                 rtic_d: rtic-d@60 {
 527                                         compatible = "fsl,sec-v4.2-rtic-memory",
 528                                                      "fsl,sec-v4.0-rtic-memory";
 529                                         reg = <0x60 0x20 0x500 0x80>;
 530                                 };
 531                         };
 532                 };
 533
 534                 sec_mon: sec_mon@314000 {
 535                         compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
 536                         reg = <0x314000 0x1000>;
 537                         interrupts = <93 2 0 0>;
 538                 };
 539         };
 540
 541 /*
 542         rapidio0: rapidio@ffe0c0000
 543 */
 544
 545         localbus@ffe124000 {
 546                 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
 547                 interrupts = <25 2 0 0>;
 548                 #address-cells = <2>;
 549                 #size-cells = <1>;
 550         };
 551
 552         pci0: pcie@ffe200000 {
 553                 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
 554                 device_type = "pci";
 555                 #size-cells = <2>;
 556                 #address-cells = <3>;
 557                 bus-range = <0x0 0xff>;
 558                 clock-frequency = <0x1fca055>;
 559                 fsl,msi = <&msi0>;
 560                 interrupts = <16 2 1 15>;
 561
 562                 pcie@0 {
 563                         reg = <0 0 0 0 0>;
 564                         #interrupt-cells = <1>;
 565                         #size-cells = <2>;
 566                         #address-cells = <3>;
 567                         device_type = "pci";
 568                         interrupts = <16 2 1 15>;
 569                         interrupt-map-mask = <0xf800 0 0 7>;
 570                         interrupt-map = <
 571                                 /* IDSEL 0x0 */
 572                                 0000 0 0 1 &mpic 40 1 0 0
 573                                 0000 0 0 2 &mpic 1 1 0 0
 574                                 0000 0 0 3 &mpic 2 1 0 0
 575                                 0000 0 0 4 &mpic 3 1 0 0
 576                                 >;
 577                 };
 578         };
 579
 580         pci1: pcie@ffe201000 {
 581                 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
 582                 device_type = "pci";
 583                 #size-cells = <2>;
 584                 #address-cells = <3>;
 585                 bus-range = <0 0xff>;
 586                 clock-frequency = <0x1fca055>;
 587                 fsl,msi = <&msi1>;
 588                 interrupts = <16 2 1 14>;
 589                 pcie@0 {
 590                         reg = <0 0 0 0 0>;
 591                         #interrupt-cells = <1>;
 592                         #size-cells = <2>;
 593                         #address-cells = <3>;
 594                         device_type = "pci";
 595                         interrupts = <16 2 1 14>;
 596                         interrupt-map-mask = <0xf800 0 0 7>;
 597                         interrupt-map = <
 598                                 /* IDSEL 0x0 */
 599                                 0000 0 0 1 &mpic 41 1 0 0
 600                                 0000 0 0 2 &mpic 5 1 0 0
 601                                 0000 0 0 3 &mpic 6 1 0 0
 602                                 0000 0 0 4 &mpic 7 1 0 0
 603                                 >;
 604                 };
 605         };
 606
 607         pci2: pcie@ffe202000 {
 608                 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
 609                 device_type = "pci";
 610                 #size-cells = <2>;
 611                 #address-cells = <3>;
 612                 bus-range = <0x0 0xff>;
 613                 clock-frequency = <0x1fca055>;
 614                 fsl,msi = <&msi2>;
 615                 interrupts = <16 2 1 13>;
 616                 pcie@0 {
 617                         reg = <0 0 0 0 0>;
 618                         #interrupt-cells = <1>;
 619                         #size-cells = <2>;
 620                         #address-cells = <3>;
 621                         device_type = "pci";
 622                         interrupts = <16 2 1 13>;
 623                         interrupt-map-mask = <0xf800 0 0 7>;
 624                         interrupt-map = <
 625                                 /* IDSEL 0x0 */
 626                                 0000 0 0 1 &mpic 42 1 0 0
 627                                 0000 0 0 2 &mpic 9 1 0 0
 628                                 0000 0 0 3 &mpic 10 1 0 0
 629                                 0000 0 0 4 &mpic 11 1 0 0
 630                                 >;
 631                 };
 632         };
 633
 634         pci3: pcie@ffe203000 {
 635                 compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
 636                 device_type = "pci";
 637                 #size-cells = <2>;
 638                 #address-cells = <3>;
 639                 bus-range = <0x0 0xff>;
 640                 clock-frequency = <0x1fca055>;
 641                 fsl,msi = <&msi2>;
 642                 interrupts = <16 2 1 12>;
 643                 pcie@0 {
 644                         reg = <0 0 0 0 0>;
 645                         #interrupt-cells = <1>;
 646                         #size-cells = <2>;
 647                         #address-cells = <3>;
 648                         device_type = "pci";
 649                         interrupts = <16 2 1 12>;
 650                         interrupt-map-mask = <0xf800 0 0 7>;
 651                         interrupt-map = <
 652                                 /* IDSEL 0x0 */
 653                                 0000 0 0 1 &mpic 43 1 0 0
 654                                 0000 0 0 2 &mpic 0 1 0 0
 655                                 0000 0 0 3 &mpic 4 1 0 0
 656                                 0000 0 0 4 &mpic 8 1 0 0
 657                                 >;
 658                 };
 659         };
 660 };