2 * P2020 DS Device Tree Source
4 * Copyright 2009-2011 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 /include/ "p2020si.dtsi"
15 model = "fsl,P2020DS";
16 compatible = "fsl,P2020DS";
31 device_type = "memory";
35 compatible = "fsl,elbc", "simple-bus";
36 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
37 0x1 0x0 0x0 0xe0000000 0x08000000
38 0x2 0x0 0x0 0xffa00000 0x00040000
39 0x3 0x0 0x0 0xffdf0000 0x00008000
40 0x4 0x0 0x0 0xffa40000 0x00040000
41 0x5 0x0 0x0 0xffa80000 0x00040000
42 0x6 0x0 0x0 0xffac0000 0x00040000>;
47 compatible = "cfi-flash";
48 reg = <0x0 0x0 0x8000000>;
53 reg = <0x0 0x03000000>;
58 reg = <0x03000000 0x00e00000>;
63 reg = <0x03e00000 0x00200000>;
68 reg = <0x04000000 0x00400000>;
73 reg = <0x04400000 0x03b00000>;
77 reg = <0x07f00000 0x00080000>;
82 reg = <0x07f80000 0x00080000>;
90 compatible = "fsl,elbc-fcm-nand";
91 reg = <0x2 0x0 0x40000>;
94 reg = <0x0 0x02000000>;
99 reg = <0x02000000 0x10000000>;
103 reg = <0x12000000 0x08000000>;
108 reg = <0x1a000000 0x04000000>;
112 reg = <0x1e000000 0x01000000>;
117 reg = <0x1f000000 0x21000000>;
122 compatible = "fsl,elbc-fcm-nand";
123 reg = <0x4 0x0 0x40000>;
127 compatible = "fsl,elbc-fcm-nand";
128 reg = <0x5 0x0 0x40000>;
132 compatible = "fsl,elbc-fcm-nand";
133 reg = <0x6 0x0 0x40000>;
144 phy0: ethernet-phy@0 {
145 interrupt-parent = <&mpic>;
149 phy1: ethernet-phy@1 {
150 interrupt-parent = <&mpic>;
154 phy2: ethernet-phy@2 {
155 interrupt-parent = <&mpic>;
161 device_type = "tbi-phy";
169 device_type = "tbi-phy";
176 device_type = "tbi-phy";
181 enet0: ethernet@24000 {
182 tbi-handle = <&tbi0>;
183 phy-handle = <&phy0>;
184 phy-connection-type = "rgmii-id";
187 enet1: ethernet@25000 {
188 tbi-handle = <&tbi1>;
189 phy-handle = <&phy1>;
190 phy-connection-type = "rgmii-id";
194 enet2: ethernet@26000 {
195 tbi-handle = <&tbi2>;
196 phy-handle = <&phy2>;
197 phy-connection-type = "rgmii-id";
202 compatible = "fsl,mpic-msi";
206 pci0: pcie@ffe08000 {
207 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
208 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
209 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
212 0000 0x0 0x0 0x1 &mpic 0x8 0x1
213 0000 0x0 0x0 0x2 &mpic 0x9 0x1
214 0000 0x0 0x0 0x3 &mpic 0xa 0x1
215 0000 0x0 0x0 0x4 &mpic 0xb 0x1
218 reg = <0x0 0x0 0x0 0x0 0x0>;
220 #address-cells = <3>;
222 ranges = <0x2000000 0x0 0x80000000
223 0x2000000 0x0 0x80000000
232 pci1: pcie@ffe09000 {
233 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
234 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
235 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
238 // IDSEL 0x11 func 0 - PCI slot 1
239 0x8800 0x0 0x0 0x1 &i8259 0x9 0x2
240 0x8800 0x0 0x0 0x2 &i8259 0xa 0x2
242 // IDSEL 0x11 func 1 - PCI slot 1
243 0x8900 0x0 0x0 0x1 &i8259 0x9 0x2
244 0x8900 0x0 0x0 0x2 &i8259 0xa 0x2
246 // IDSEL 0x11 func 2 - PCI slot 1
247 0x8a00 0x0 0x0 0x1 &i8259 0x9 0x2
248 0x8a00 0x0 0x0 0x2 &i8259 0xa 0x2
250 // IDSEL 0x11 func 3 - PCI slot 1
251 0x8b00 0x0 0x0 0x1 &i8259 0x9 0x2
252 0x8b00 0x0 0x0 0x2 &i8259 0xa 0x2
254 // IDSEL 0x11 func 4 - PCI slot 1
255 0x8c00 0x0 0x0 0x1 &i8259 0x9 0x2
256 0x8c00 0x0 0x0 0x2 &i8259 0xa 0x2
258 // IDSEL 0x11 func 5 - PCI slot 1
259 0x8d00 0x0 0x0 0x1 &i8259 0x9 0x2
260 0x8d00 0x0 0x0 0x2 &i8259 0xa 0x2
262 // IDSEL 0x11 func 6 - PCI slot 1
263 0x8e00 0x0 0x0 0x1 &i8259 0x9 0x2
264 0x8e00 0x0 0x0 0x2 &i8259 0xa 0x2
266 // IDSEL 0x11 func 7 - PCI slot 1
267 0x8f00 0x0 0x0 0x1 &i8259 0x9 0x2
268 0x8f00 0x0 0x0 0x2 &i8259 0xa 0x2
271 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
274 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
275 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
277 // IDSEL 0x1f IDE/SATA
278 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
279 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
283 reg = <0x0 0x0 0x0 0x0 0x0>;
285 #address-cells = <3>;
287 ranges = <0x2000000 0x0 0xa0000000
288 0x2000000 0x0 0xa0000000
295 reg = <0x0 0x0 0x0 0x0 0x0>;
297 #address-cells = <3>;
298 ranges = <0x2000000 0x0 0xa0000000
299 0x2000000 0x0 0xa0000000
307 #interrupt-cells = <2>;
309 #address-cells = <2>;
310 reg = <0xf000 0x0 0x0 0x0 0x0>;
311 ranges = <0x1 0x0 0x1000000 0x0 0x0
313 interrupt-parent = <&i8259>;
315 i8259: interrupt-controller@20 {
319 interrupt-controller;
320 device_type = "interrupt-controller";
321 #address-cells = <0>;
322 #interrupt-cells = <2>;
323 compatible = "chrp,iic";
325 interrupt-parent = <&mpic>;
330 #address-cells = <1>;
331 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
332 interrupts = <1 3 12 3>;
338 compatible = "pnpPNP,303";
343 compatible = "pnpPNP,f03";
348 compatible = "pnpPNP,b00";
349 reg = <0x1 0x70 0x2>;
353 reg = <0x1 0x400 0x80>;
361 pci2: pcie@ffe0a000 {
362 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
363 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
364 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
367 0000 0x0 0x0 0x1 &mpic 0x0 0x1
368 0000 0x0 0x0 0x2 &mpic 0x1 0x1
369 0000 0x0 0x0 0x3 &mpic 0x2 0x1
370 0000 0x0 0x0 0x4 &mpic 0x3 0x1
373 reg = <0x0 0x0 0x0 0x0 0x0>;
375 #address-cells = <3>;
377 ranges = <0x2000000 0x0 0xc0000000
378 0x2000000 0x0 0xc0000000