2 * MPC8610 HPCD Device Tree Source
4 * Copyright 2007-2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License Version 2 as published
8 * by the Free Software Foundation.
14 model = "MPC8610HPCD";
15 compatible = "fsl,MPC8610HPCD";
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>; // L1
37 i-cache-size = <32768>; // L1
38 sleep = <&pmc 0x00008000 0 // core
39 &pmc 0x00004000 0>; // timebase
40 timebase-frequency = <0>; // From uboot
41 bus-frequency = <0>; // From uboot
42 clock-frequency = <0>; // From uboot
47 device_type = "memory";
48 reg = <0x00000000 0x20000000>; // 512M at 0x0
54 compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
55 reg = <0xe0005000 0x1000>;
57 interrupt-parent = <&mpic>;
58 ranges = <0 0 0xf8000000 0x08000000
59 1 0 0xf0000000 0x08000000
60 2 0 0xe8400000 0x00008000
61 4 0 0xe8440000 0x00008000
62 5 0 0xe8480000 0x00008000
63 6 0 0xe84c0000 0x00008000
64 3 0 0xe8000000 0x00000020>;
65 sleep = <&pmc 0x08000000 0>;
68 compatible = "cfi-flash";
69 reg = <0 0 0x8000000>;
75 compatible = "cfi-flash";
76 reg = <1 0 0x8000000>;
82 compatible = "fsl,mpc8610-fcm-nand",
88 compatible = "fsl,mpc8610-fcm-nand",
94 compatible = "fsl,mpc8610-fcm-nand",
100 compatible = "fsl,mpc8610-fcm-nand",
106 #address-cells = <1>;
108 compatible = "fsl,fpga-pixis";
110 ranges = <0 3 0 0x20>;
111 interrupt-parent = <&mpic>;
114 sdcsr_pio: gpio-controller@a {
116 compatible = "fsl,fpga-pixis-gpio-bank";
124 #address-cells = <1>;
126 #interrupt-cells = <2>;
128 compatible = "fsl,mpc8610-immr", "simple-bus";
129 ranges = <0x0 0xe0000000 0x00100000>;
133 compatible = "fsl,mcm-law";
139 compatible = "fsl,mpc8610-mcm", "fsl,mcm";
140 reg = <0x1000 0x1000>;
142 interrupt-parent = <&mpic>;
146 #address-cells = <1>;
149 compatible = "fsl-i2c";
150 reg = <0x3000 0x100>;
152 interrupt-parent = <&mpic>;
156 compatible = "cirrus,cs4270";
158 /* MCLK source is a stand-alone oscillator */
159 clock-frequency = <12288000>;
164 #address-cells = <1>;
167 compatible = "fsl-i2c";
168 reg = <0x3100 0x100>;
170 interrupt-parent = <&mpic>;
171 sleep = <&pmc 0x00000004 0>;
175 serial0: serial@4500 {
177 device_type = "serial";
178 compatible = "ns16550";
179 reg = <0x4500 0x100>;
180 clock-frequency = <0>;
182 interrupt-parent = <&mpic>;
183 sleep = <&pmc 0x00000002 0>;
186 serial1: serial@4600 {
188 device_type = "serial";
189 compatible = "ns16550";
190 reg = <0x4600 0x100>;
191 clock-frequency = <0>;
193 interrupt-parent = <&mpic>;
194 sleep = <&pmc 0x00000008 0>;
198 #address-cells = <1>;
200 compatible = "fsl,mpc8610-spi", "fsl,spi";
204 interrupt-parent = <&mpic>;
206 gpios = <&sdcsr_pio 7 0>;
207 sleep = <&pmc 0x00000800 0>;
210 compatible = "fsl,mpc8610hpcd-mmc-slot",
213 gpios = <&sdcsr_pio 0 1 /* nCD */
214 &sdcsr_pio 1 0>; /* WP */
215 voltage-ranges = <3300 3300>;
216 spi-max-frequency = <50000000>;
221 compatible = "fsl,diu";
224 interrupt-parent = <&mpic>;
225 sleep = <&pmc 0x04000000 0>;
228 mpic: interrupt-controller@40000 {
229 interrupt-controller;
230 #address-cells = <0>;
231 #interrupt-cells = <2>;
232 reg = <0x40000 0x40000>;
233 compatible = "chrp,open-pic";
234 device_type = "open-pic";
238 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
239 reg = <0x41600 0x80>;
240 msi-available-ranges = <0 0x100>;
250 interrupt-parent = <&mpic>;
253 global-utilities@e0000 {
254 #address-cells = <1>;
256 compatible = "fsl,mpc8610-guts";
257 reg = <0xe0000 0x1000>;
258 ranges = <0 0xe0000 0x1000>;
262 compatible = "fsl,mpc8610-pmc",
269 compatible = "fsl,mpc8610-wdt";
270 reg = <0xe4000 0x100>;
274 compatible = "fsl,mpc8610-ssi";
276 reg = <0x16000 0x100>;
277 interrupt-parent = <&mpic>;
279 fsl,mode = "i2s-slave";
280 codec-handle = <&cs4270>;
281 fsl,playback-dma = <&dma00>;
282 fsl,capture-dma = <&dma01>;
283 fsl,fifo-depth = <8>;
284 sleep = <&pmc 0 0x08000000>;
288 compatible = "fsl,mpc8610-ssi";
290 reg = <0x16100 0x100>;
291 interrupt-parent = <&mpic>;
293 fsl,fifo-depth = <8>;
294 sleep = <&pmc 0 0x04000000>;
298 #address-cells = <1>;
300 compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
302 reg = <0x21300 0x4>; /* DMA general status register */
303 ranges = <0x0 0x21100 0x200>;
304 sleep = <&pmc 0x00000400 0>;
306 dma00: dma-channel@0 {
307 compatible = "fsl,mpc8610-dma-channel",
308 "fsl,ssi-dma-channel";
311 interrupt-parent = <&mpic>;
314 dma01: dma-channel@1 {
315 compatible = "fsl,mpc8610-dma-channel",
316 "fsl,ssi-dma-channel";
319 interrupt-parent = <&mpic>;
323 compatible = "fsl,mpc8610-dma-channel",
324 "fsl,eloplus-dma-channel";
327 interrupt-parent = <&mpic>;
331 compatible = "fsl,mpc8610-dma-channel",
332 "fsl,eloplus-dma-channel";
335 interrupt-parent = <&mpic>;
341 #address-cells = <1>;
343 compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
345 reg = <0xc300 0x4>; /* DMA general status register */
346 ranges = <0x0 0xc100 0x200>;
347 sleep = <&pmc 0x00000200 0>;
350 compatible = "fsl,mpc8610-dma-channel",
351 "fsl,eloplus-dma-channel";
354 interrupt-parent = <&mpic>;
358 compatible = "fsl,mpc8610-dma-channel",
359 "fsl,eloplus-dma-channel";
362 interrupt-parent = <&mpic>;
366 compatible = "fsl,mpc8610-dma-channel",
367 "fsl,eloplus-dma-channel";
370 interrupt-parent = <&mpic>;
374 compatible = "fsl,mpc8610-dma-channel",
375 "fsl,eloplus-dma-channel";
378 interrupt-parent = <&mpic>;
386 compatible = "fsl,mpc8610-pci";
388 #interrupt-cells = <1>;
390 #address-cells = <3>;
391 reg = <0xe0008000 0x1000>;
393 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
394 0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
395 sleep = <&pmc 0x80000000 0>;
396 clock-frequency = <33333333>;
397 interrupt-parent = <&mpic>;
399 interrupt-map-mask = <0xf800 0 0 7>;
402 0x8800 0 0 1 &mpic 4 1
403 0x8800 0 0 2 &mpic 5 1
404 0x8800 0 0 3 &mpic 6 1
405 0x8800 0 0 4 &mpic 7 1
408 0x9000 0 0 1 &mpic 5 1
409 0x9000 0 0 2 &mpic 6 1
410 0x9000 0 0 3 &mpic 7 1
411 0x9000 0 0 4 &mpic 4 1
415 pci1: pcie@e000a000 {
416 compatible = "fsl,mpc8641-pcie";
418 #interrupt-cells = <1>;
420 #address-cells = <3>;
421 reg = <0xe000a000 0x1000>;
423 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
424 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
425 sleep = <&pmc 0x40000000 0>;
426 clock-frequency = <33333333>;
427 interrupt-parent = <&mpic>;
429 interrupt-map-mask = <0xf800 0 0 7>;
433 0xd800 0 0 1 &mpic 2 1
436 0xe000 0 0 1 &mpic 1 1
437 0xe000 0 0 2 &mpic 1 1
438 0xe000 0 0 3 &mpic 1 1
439 0xe000 0 0 4 &mpic 1 1
442 0xf800 0 0 1 &mpic 3 2
443 0xf800 0 0 2 &mpic 0 1
449 #address-cells = <3>;
451 ranges = <0x02000000 0x0 0xa0000000
452 0x02000000 0x0 0xa0000000
454 0x01000000 0x0 0x00000000
455 0x01000000 0x0 0x00000000
460 #address-cells = <3>;
461 ranges = <0x02000000 0x0 0xa0000000
462 0x02000000 0x0 0xa0000000
464 0x01000000 0x0 0x00000000
465 0x01000000 0x0 0x00000000
471 #address-cells = <2>;
472 reg = <0xf000 0 0 0 0>;
473 ranges = <1 0 0x01000000 0 0
477 compatible = "pnpPNP,b00";
485 pci2: pcie@e0009000 {
486 #address-cells = <3>;
488 #interrupt-cells = <1>;
490 compatible = "fsl,mpc8641-pcie";
491 reg = <0xe0009000 0x00001000>;
492 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
493 0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
495 interrupt-map-mask = <0xf800 0 0 7>;
496 interrupt-map = <0x0000 0 0 1 &mpic 4 1
497 0x0000 0 0 2 &mpic 5 1
498 0x0000 0 0 3 &mpic 6 1
499 0x0000 0 0 4 &mpic 7 1>;
500 interrupt-parent = <&mpic>;
502 sleep = <&pmc 0x20000000 0>;
503 clock-frequency = <33333333>;