arch/powerpc/boot/dts/mpc8569mds.dts

   1 /*
   2  * MPC8569E MDS Device Tree Source
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8569EMDS";
  16         compatible = "fsl,MPC8569EMDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 serial0 = &serial0;
  22                 serial1 = &serial1;
  23                 ethernet0 = &enet0;
  24                 ethernet1 = &enet1;
  25                 ethernet2 = &enet2;
  26                 ethernet3 = &enet3;
  27                 pci1 = &pci1;
  28                 rapidio0 = &rio0;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 PowerPC,8569@0 {
  36                         device_type = "cpu";
  37                         reg = <0x0>;
  38                         d-cache-line-size = <32>;       // 32 bytes
  39                         i-cache-line-size = <32>;       // 32 bytes
  40                         d-cache-size = <0x8000>;                // L1, 32K
  41                         i-cache-size = <0x8000>;                // L1, 32K
  42                         timebase-frequency = <0>;
  43                         bus-frequency = <0>;
  44                         clock-frequency = <0>;
  45                         next-level-cache = <&L2>;
  46                 };
  47         };
  48
  49         memory {
  50                 device_type = "memory";
  51         };
  52
  53         localbus@e0005000 {
  54                 #address-cells = <2>;
  55                 #size-cells = <1>;
  56                 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
  57                 reg = <0xe0005000 0x1000>;
  58                 interrupts = <19 2>;
  59                 interrupt-parent = <&mpic>;
  60
  61                 ranges = <0x0 0x0 0xfe000000 0x02000000
  62                           0x1 0x0 0xf8000000 0x00008000
  63                           0x2 0x0 0xf0000000 0x04000000
  64                           0x3 0x0 0xfc000000 0x00008000
  65                           0x4 0x0 0xf8008000 0x00008000
  66                           0x5 0x0 0xf8010000 0x00008000>;
  67
  68                 nor@0,0 {
  69                         #address-cells = <1>;
  70                         #size-cells = <1>;
  71                         compatible = "cfi-flash";
  72                         reg = <0x0 0x0 0x02000000>;
  73                         bank-width = <2>;
  74                         device-width = <1>;
  75                 };
  76
  77                 bcsr@1,0 {
  78                         compatible = "fsl,mpc8569mds-bcsr";
  79                         reg = <1 0 0x8000>;
  80                 };
  81
  82                 nand@3,0 {
  83                         compatible = "fsl,mpc8569-fcm-nand",
  84                                      "fsl,elbc-fcm-nand";
  85                         reg = <3 0 0x8000>;
  86                 };
  87
  88                 pib@4,0 {
  89                         compatible = "fsl,mpc8569mds-pib";
  90                         reg = <4 0 0x8000>;
  91                 };
  92
  93                 pib@5,0 {
  94                         compatible = "fsl,mpc8569mds-pib";
  95                         reg = <5 0 0x8000>;
  96                 };
  97         };
  98
  99         soc@e0000000 {
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 device_type = "soc";
 103                 compatible = "fsl,mpc8569-immr", "simple-bus";
 104                 ranges = <0x0 0xe0000000 0x100000>;
 105                 bus-frequency = <0>;
 106
 107                 ecm-law@0 {
 108                         compatible = "fsl,ecm-law";
 109                         reg = <0x0 0x1000>;
 110                         fsl,num-laws = <10>;
 111                 };
 112
 113                 ecm@1000 {
 114                         compatible = "fsl,mpc8569-ecm", "fsl,ecm";
 115                         reg = <0x1000 0x1000>;
 116                         interrupts = <17 2>;
 117                         interrupt-parent = <&mpic>;
 118                 };
 119
 120                 memory-controller@2000 {
 121                         compatible = "fsl,mpc8569-memory-controller";
 122                         reg = <0x2000 0x1000>;
 123                         interrupt-parent = <&mpic>;
 124                         interrupts = <18 2>;
 125                 };
 126
 127                 i2c@3000 {
 128                         #address-cells = <1>;
 129                         #size-cells = <0>;
 130                         cell-index = <0>;
 131                         compatible = "fsl-i2c";
 132                         reg = <0x3000 0x100>;
 133                         interrupts = <43 2>;
 134                         interrupt-parent = <&mpic>;
 135                         dfsrr;
 136
 137                         rtc@68 {
 138                                 compatible = "dallas,ds1374";
 139                                 reg = <0x68>;
 140                         };
 141                 };
 142
 143                 i2c@3100 {
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         cell-index = <1>;
 147                         compatible = "fsl-i2c";
 148                         reg = <0x3100 0x100>;
 149                         interrupts = <43 2>;
 150                         interrupt-parent = <&mpic>;
 151                         dfsrr;
 152                 };
 153
 154                 serial0: serial@4500 {
 155                         cell-index = <0>;
 156                         device_type = "serial";
 157                         compatible = "ns16550";
 158                         reg = <0x4500 0x100>;
 159                         clock-frequency = <0>;
 160                         interrupts = <42 2>;
 161                         interrupt-parent = <&mpic>;
 162                 };
 163
 164                 serial1: serial@4600 {
 165                         cell-index = <1>;
 166                         device_type = "serial";
 167                         compatible = "ns16550";
 168                         reg = <0x4600 0x100>;
 169                         clock-frequency = <0>;
 170                         interrupts = <42 2>;
 171                         interrupt-parent = <&mpic>;
 172                 };
 173
 174                 L2: l2-cache-controller@20000 {
 175                         compatible = "fsl,mpc8569-l2-cache-controller";
 176                         reg = <0x20000 0x1000>;
 177                         cache-line-size = <32>; // 32 bytes
 178                         cache-size = <0x80000>; // L2, 512K
 179                         interrupt-parent = <&mpic>;
 180                         interrupts = <16 2>;
 181                 };
 182
 183                 dma@21300 {
 184                         #address-cells = <1>;
 185                         #size-cells = <1>;
 186                         compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
 187                         reg = <0x21300 0x4>;
 188                         ranges = <0x0 0x21100 0x200>;
 189                         cell-index = <0>;
 190                         dma-channel@0 {
 191                                 compatible = "fsl,mpc8569-dma-channel",
 192                                                 "fsl,eloplus-dma-channel";
 193                                 reg = <0x0 0x80>;
 194                                 cell-index = <0>;
 195                                 interrupt-parent = <&mpic>;
 196                                 interrupts = <20 2>;
 197                         };
 198                         dma-channel@80 {
 199                                 compatible = "fsl,mpc8569-dma-channel",
 200                                                 "fsl,eloplus-dma-channel";
 201                                 reg = <0x80 0x80>;
 202                                 cell-index = <1>;
 203                                 interrupt-parent = <&mpic>;
 204                                 interrupts = <21 2>;
 205                         };
 206                         dma-channel@100 {
 207                                 compatible = "fsl,mpc8569-dma-channel",
 208                                                 "fsl,eloplus-dma-channel";
 209                                 reg = <0x100 0x80>;
 210                                 cell-index = <2>;
 211                                 interrupt-parent = <&mpic>;
 212                                 interrupts = <22 2>;
 213                         };
 214                         dma-channel@180 {
 215                                 compatible = "fsl,mpc8569-dma-channel",
 216                                                 "fsl,eloplus-dma-channel";
 217                                 reg = <0x180 0x80>;
 218                                 cell-index = <3>;
 219                                 interrupt-parent = <&mpic>;
 220                                 interrupts = <23 2>;
 221                         };
 222                 };
 223
 224                 sdhci@2e000 {
 225                         compatible = "fsl,mpc8569-esdhc", "fsl,esdhc";
 226                         reg = <0x2e000 0x1000>;
 227                         interrupts = <72 0x8>;
 228                         interrupt-parent = <&mpic>;
 229                         /* Filled in by U-Boot */
 230                         clock-frequency = <0>;
 231                         status = "disabled";
 232                 };
 233
 234                 crypto@30000 {
 235                         compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
 236                                 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
 237                         reg = <0x30000 0x10000>;
 238                         interrupts = <45 2 58 2>;
 239                         interrupt-parent = <&mpic>;
 240                         fsl,num-channels = <4>;
 241                         fsl,channel-fifo-len = <24>;
 242                         fsl,exec-units-mask = <0xbfe>;
 243                         fsl,descriptor-types-mask = <0x3ab0ebf>;
 244                 };
 245
 246                 mpic: pic@40000 {
 247                         interrupt-controller;
 248                         #address-cells = <0>;
 249                         #interrupt-cells = <2>;
 250                         reg = <0x40000 0x40000>;
 251                         compatible = "chrp,open-pic";
 252                         device_type = "open-pic";
 253                 };
 254
 255                 msi@41600 {
 256                         compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
 257                         reg = <0x41600 0x80>;
 258                         msi-available-ranges = <0 0x100>;
 259                         interrupts = <
 260                                 0xe0 0
 261                                 0xe1 0
 262                                 0xe2 0
 263                                 0xe3 0
 264                                 0xe4 0
 265                                 0xe5 0
 266                                 0xe6 0
 267                                 0xe7 0>;
 268                         interrupt-parent = <&mpic>;
 269                 };
 270
 271                 global-utilities@e0000 {
 272                         compatible = "fsl,mpc8569-guts";
 273                         reg = <0xe0000 0x1000>;
 274                         fsl,has-rstcr;
 275                 };
 276
 277                 par_io@e0100 {
 278                         #address-cells = <1>;
 279                         #size-cells = <1>;
 280                         reg = <0xe0100 0x100>;
 281                         ranges = <0x0 0xe0100 0x100>;
 282                         device_type = "par_io";
 283                         num-ports = <7>;
 284
 285                         qe_pio_e: gpio-controller@80 {
 286                                 #gpio-cells = <2>;
 287                                 compatible = "fsl,mpc8569-qe-pario-bank",
 288                                              "fsl,mpc8323-qe-pario-bank";
 289                                 reg = <0x80 0x18>;
 290                                 gpio-controller;
 291                         };
 292
 293                         pio1: ucc_pin@01 {
 294                                 pio-map = <
 295                         /* port  pin  dir  open_drain  assignment  has_irq */
 296                                         0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 297                                         0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
 298                                         0x2  0x0b 0x2  0x0  0x1  0x0    /* CLK12*/
 299                                         0x0  0x0  0x1  0x0  0x3  0x0    /* ENET1_TXD0_SER1_TXD0 */
 300                                         0x0  0x1  0x1  0x0  0x3  0x0    /* ENET1_TXD1_SER1_TXD1 */
 301                                         0x0  0x2  0x1  0x0  0x1  0x0    /* ENET1_TXD2_SER1_TXD2 */
 302                                         0x0  0x3  0x1  0x0  0x2  0x0    /* ENET1_TXD3_SER1_TXD3 */
 303                                         0x0  0x6  0x2  0x0  0x3  0x0    /* ENET1_RXD0_SER1_RXD0 */
 304                                         0x0  0x7  0x2  0x0  0x1  0x0    /* ENET1_RXD1_SER1_RXD1 */
 305                                         0x0  0x8  0x2  0x0  0x2  0x0    /* ENET1_RXD2_SER1_RXD2 */
 306                                         0x0  0x9  0x2  0x0  0x2  0x0    /* ENET1_RXD3_SER1_RXD3 */
 307                                         0x0  0x4  0x1  0x0  0x2  0x0    /* ENET1_TX_EN_SER1_RTS_B */
 308                                         0x0  0xc  0x2  0x0  0x3  0x0    /* ENET1_RX_DV_SER1_CTS_B */
 309                                         0x2  0x8  0x2  0x0  0x1  0x0    /* ENET1_GRXCLK */
 310                                         0x2  0x14 0x1  0x0  0x2  0x0>;  /* ENET1_GTXCLK */
 311                         };
 312
 313                         pio2: ucc_pin@02 {
 314                                 pio-map = <
 315                         /* port  pin  dir  open_drain  assignment  has_irq */
 316                                         0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 317                                         0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
 318                                         0x2  0x10 0x2  0x0  0x3  0x0    /* CLK17 */
 319                                         0x0  0xe  0x1  0x0  0x2  0x0    /* ENET2_TXD0_SER2_TXD0 */
 320                                         0x0  0xf  0x1  0x0  0x2  0x0    /* ENET2_TXD1_SER2_TXD1 */
 321                                         0x0  0x10 0x1  0x0  0x1  0x0    /* ENET2_TXD2_SER2_TXD2 */
 322                                         0x0  0x11 0x1  0x0  0x1  0x0    /* ENET2_TXD3_SER2_TXD3 */
 323                                         0x0  0x14 0x2  0x0  0x2  0x0    /* ENET2_RXD0_SER2_RXD0 */
 324                                         0x0  0x15 0x2  0x0  0x1  0x0    /* ENET2_RXD1_SER2_RXD1 */
 325                                         0x0  0x16 0x2  0x0  0x1  0x0    /* ENET2_RXD2_SER2_RXD2 */
 326                                         0x0  0x17 0x2  0x0  0x1  0x0    /* ENET2_RXD3_SER2_RXD3 */
 327                                         0x0  0x12 0x1  0x0  0x2  0x0    /* ENET2_TX_EN_SER2_RTS_B */
 328                                         0x0  0x1a 0x2  0x0  0x3  0x0    /* ENET2_RX_DV_SER2_CTS_B */
 329                                         0x2  0x3  0x2  0x0  0x1  0x0    /* ENET2_GRXCLK */
 330                                         0x2  0x2 0x1  0x0  0x2  0x0>;   /* ENET2_GTXCLK */
 331                         };
 332
 333                         pio3: ucc_pin@03 {
 334                                 pio-map = <
 335                         /* port  pin  dir  open_drain  assignment  has_irq */
 336                                         0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 337                                         0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
 338                                         0x2  0x0b 0x2  0x0  0x1  0x0    /* CLK12*/
 339                                         0x0  0x1d 0x1  0x0  0x2  0x0    /* ENET3_TXD0_SER3_TXD0 */
 340                                         0x0  0x1e 0x1  0x0  0x3  0x0    /* ENET3_TXD1_SER3_TXD1 */
 341                                         0x0  0x1f 0x1  0x0  0x2  0x0    /* ENET3_TXD2_SER3_TXD2 */
 342                                         0x1  0x0  0x1  0x0  0x3  0x0    /* ENET3_TXD3_SER3_TXD3 */
 343                                         0x1  0x3  0x2  0x0  0x3  0x0    /* ENET3_RXD0_SER3_RXD0 */
 344                                         0x1  0x4  0x2  0x0  0x1  0x0    /* ENET3_RXD1_SER3_RXD1 */
 345                                         0x1  0x5  0x2  0x0  0x2  0x0    /* ENET3_RXD2_SER3_RXD2 */
 346                                         0x1  0x6  0x2  0x0  0x3  0x0    /* ENET3_RXD3_SER3_RXD3 */
 347                                         0x1  0x1  0x1  0x0  0x1  0x0    /* ENET3_TX_EN_SER3_RTS_B */
 348                                         0x1  0x9  0x2  0x0  0x3  0x0    /* ENET3_RX_DV_SER3_CTS_B */
 349                                         0x2  0x9  0x2  0x0  0x2  0x0    /* ENET3_GRXCLK */
 350                                         0x2  0x19 0x1  0x0  0x2  0x0>;  /* ENET3_GTXCLK */
 351                         };
 352
 353                         pio4: ucc_pin@04 {
 354                                 pio-map = <
 355                         /* port  pin  dir  open_drain  assignment  has_irq */
 356                                         0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 357                                         0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
 358                                         0x2  0x10 0x2  0x0  0x3  0x0    /* CLK17 */
 359                                         0x1  0xc  0x1  0x0  0x2  0x0    /* ENET4_TXD0_SER4_TXD0 */
 360                                         0x1  0xd  0x1  0x0  0x2  0x0    /* ENET4_TXD1_SER4_TXD1 */
 361                                         0x1  0xe  0x1  0x0  0x1  0x0    /* ENET4_TXD2_SER4_TXD2 */
 362                                         0x1  0xf  0x1  0x0  0x2  0x0    /* ENET4_TXD3_SER4_TXD3 */
 363                                         0x1  0x12 0x2  0x0  0x2  0x0    /* ENET4_RXD0_SER4_RXD0 */
 364                                         0x1  0x13 0x2  0x0  0x1  0x0    /* ENET4_RXD1_SER4_RXD1 */
 365                                         0x1  0x14 0x2  0x0  0x1  0x0    /* ENET4_RXD2_SER4_RXD2 */
 366                                         0x1  0x15 0x2  0x0  0x2  0x0    /* ENET4_RXD3_SER4_RXD3 */
 367                                         0x1  0x10 0x1  0x0  0x2  0x0    /* ENET4_TX_EN_SER4_RTS_B */
 368                                         0x1  0x18 0x2  0x0  0x3  0x0    /* ENET4_RX_DV_SER4_CTS_B */
 369                                         0x2  0x11 0x2  0x0  0x2  0x0    /* ENET4_GRXCLK */
 370                                         0x2  0x18 0x1  0x0  0x2  0x0>;  /* ENET4_GTXCLK */
 371                         };
 372                 };
 373         };
 374
 375         qe@e0080000 {
 376                 #address-cells = <1>;
 377                 #size-cells = <1>;
 378                 device_type = "qe";
 379                 compatible = "fsl,qe";
 380                 ranges = <0x0 0xe0080000 0x40000>;
 381                 reg = <0xe0080000 0x480>;
 382                 brg-frequency = <0>;
 383                 bus-frequency = <0>;
 384                 fsl,qe-num-riscs = <4>;
 385                 fsl,qe-num-snums = <46>;
 386
 387                 qeic: interrupt-controller@80 {
 388                         interrupt-controller;
 389                         compatible = "fsl,qe-ic";
 390                         #address-cells = <0>;
 391                         #interrupt-cells = <1>;
 392                         reg = <0x80 0x80>;
 393                         interrupts = <46 2 46 2>; //high:30 low:30
 394                         interrupt-parent = <&mpic>;
 395                 };
 396
 397                 spi@4c0 {
 398                         #address-cells = <1>;
 399                         #size-cells = <0>;
 400                         compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
 401                         reg = <0x4c0 0x40>;
 402                         cell-index = <0>;
 403                         interrupts = <2>;
 404                         interrupt-parent = <&qeic>;
 405                         gpios = <&qe_pio_e 30 0>;
 406                         mode = "cpu-qe";
 407
 408                         serial-flash@0 {
 409                                 compatible = "stm,m25p40";
 410                                 reg = <0>;
 411                                 spi-max-frequency = <25000000>;
 412                         };
 413                 };
 414
 415                 spi@500 {
 416                         cell-index = <1>;
 417                         compatible = "fsl,spi";
 418                         reg = <0x500 0x40>;
 419                         interrupts = <1>;
 420                         interrupt-parent = <&qeic>;
 421                         mode = "cpu";
 422                 };
 423
 424                 enet0: ucc@2000 {
 425                         device_type = "network";
 426                         compatible = "ucc_geth";
 427                         cell-index = <1>;
 428                         reg = <0x2000 0x200>;
 429                         interrupts = <32>;
 430                         interrupt-parent = <&qeic>;
 431                         local-mac-address = [ 00 00 00 00 00 00 ];
 432                         rx-clock-name = "none";
 433                         tx-clock-name = "clk12";
 434                         pio-handle = <&pio1>;
 435                         phy-handle = <&qe_phy0>;
 436                         phy-connection-type = "rgmii-id";
 437                 };
 438
 439                 mdio@2120 {
 440                         #address-cells = <1>;
 441                         #size-cells = <0>;
 442                         reg = <0x2120 0x18>;
 443                         compatible = "fsl,ucc-mdio";
 444
 445                         qe_phy0: ethernet-phy@07 {
 446                                 interrupt-parent = <&mpic>;
 447                                 interrupts = <1 1>;
 448                                 reg = <0x7>;
 449                                 device_type = "ethernet-phy";
 450                         };
 451                         qe_phy1: ethernet-phy@01 {
 452                                 interrupt-parent = <&mpic>;
 453                                 interrupts = <2 1>;
 454                                 reg = <0x1>;
 455                                 device_type = "ethernet-phy";
 456                         };
 457                         qe_phy2: ethernet-phy@02 {
 458                                 interrupt-parent = <&mpic>;
 459                                 interrupts = <3 1>;
 460                                 reg = <0x2>;
 461                                 device_type = "ethernet-phy";
 462                         };
 463                         qe_phy3: ethernet-phy@03 {
 464                                 interrupt-parent = <&mpic>;
 465                                 interrupts = <4 1>;
 466                                 reg = <0x3>;
 467                                 device_type = "ethernet-phy";
 468                         };
 469                 };
 470
 471                 enet2: ucc@2200 {
 472                         device_type = "network";
 473                         compatible = "ucc_geth";
 474                         cell-index = <3>;
 475                         reg = <0x2200 0x200>;
 476                         interrupts = <34>;
 477                         interrupt-parent = <&qeic>;
 478                         local-mac-address = [ 00 00 00 00 00 00 ];
 479                         rx-clock-name = "none";
 480                         tx-clock-name = "clk12";
 481                         pio-handle = <&pio3>;
 482                         phy-handle = <&qe_phy2>;
 483                         phy-connection-type = "rgmii-id";
 484                 };
 485
 486                 enet1: ucc@3000 {
 487                         device_type = "network";
 488                         compatible = "ucc_geth";
 489                         cell-index = <2>;
 490                         reg = <0x3000 0x200>;
 491                         interrupts = <33>;
 492                         interrupt-parent = <&qeic>;
 493                         local-mac-address = [ 00 00 00 00 00 00 ];
 494                         rx-clock-name = "none";
 495                         tx-clock-name = "clk17";
 496                         pio-handle = <&pio2>;
 497                         phy-handle = <&qe_phy1>;
 498                         phy-connection-type = "rgmii-id";
 499                 };
 500
 501                 enet3: ucc@3200 {
 502                         device_type = "network";
 503                         compatible = "ucc_geth";
 504                         cell-index = <4>;
 505                         reg = <0x3200 0x200>;
 506                         interrupts = <35>;
 507                         interrupt-parent = <&qeic>;
 508                         local-mac-address = [ 00 00 00 00 00 00 ];
 509                         rx-clock-name = "none";
 510                         tx-clock-name = "clk17";
 511                         pio-handle = <&pio4>;
 512                         phy-handle = <&qe_phy3>;
 513                         phy-connection-type = "rgmii-id";
 514                 };
 515
 516                 muram@10000 {
 517                         #address-cells = <1>;
 518                         #size-cells = <1>;
 519                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
 520                         ranges = <0x0 0x10000 0x20000>;
 521
 522                         data-only@0 {
 523                                 compatible = "fsl,qe-muram-data",
 524                                              "fsl,cpm-muram-data";
 525                                 reg = <0x0 0x20000>;
 526                         };
 527                 };
 528
 529         };
 530
 531         /* PCI Express */
 532         pci1: pcie@e000a000 {
 533                 compatible = "fsl,mpc8548-pcie";
 534                 device_type = "pci";
 535                 #interrupt-cells = <1>;
 536                 #size-cells = <2>;
 537                 #address-cells = <3>;
 538                 reg = <0xe000a000 0x1000>;
 539                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 540                 interrupt-map = <
 541                         /* IDSEL 0x0 (PEX) */
 542                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
 543                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
 544                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
 545                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 546
 547                 interrupt-parent = <&mpic>;
 548                 interrupts = <26 2>;
 549                 bus-range = <0 255>;
 550                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 551                           0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
 552                 clock-frequency = <33333333>;
 553                 pcie@0 {
 554                         reg = <0x0 0x0 0x0 0x0 0x0>;
 555                         #size-cells = <2>;
 556                         #address-cells = <3>;
 557                         device_type = "pci";
 558                         ranges = <0x2000000 0x0 0xa0000000
 559                                   0x2000000 0x0 0xa0000000
 560                                   0x0 0x10000000
 561
 562                                   0x1000000 0x0 0x0
 563                                   0x1000000 0x0 0x0
 564                                   0x0 0x800000>;
 565                 };
 566         };
 567
 568         rio0: rapidio@e00c00000 {
 569                 #address-cells = <2>;
 570                 #size-cells = <2>;
 571                 compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta";
 572                 reg = <0xe00c0000 0x20000>;
 573                 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
 574                 interrupts = <48 2 /* error     */
 575                               49 2 /* bell_outb */
 576                               50 2 /* bell_inb  */
 577                               53 2 /* msg1_tx   */
 578                               54 2 /* msg1_rx   */
 579                               55 2 /* msg2_tx   */
 580                               56 2 /* msg2_rx   */>;
 581                 interrupt-parent = <&mpic>;
 582         };
 583 };