arch/powerpc/boot/dts/mpc8560ads.dts

   1 /*
   2  * MPC8560 ADS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 / {
  14         model = "MPC8560ADS";
  15         compatible = "MPC8560ADS", "MPC85xxADS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 PowerPC,8560@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         d-cache-line-size = <20>;       // 32 bytes
  27                         i-cache-line-size = <20>;       // 32 bytes
  28                         d-cache-size = <8000>;          // L1, 32K
  29                         i-cache-size = <8000>;          // L1, 32K
  30                         timebase-frequency = <04ead9a0>;
  31                         bus-frequency = <13ab6680>;
  32                         clock-frequency = <312c8040>;
  33                         32-bit;
  34                 };
  35         };
  36
  37         memory {
  38                 device_type = "memory";
  39                 reg = <00000000 10000000>;
  40         };
  41
  42         soc8560@e0000000 {
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 #interrupt-cells = <2>;
  46                 device_type = "soc";
  47                 ranges = <0 e0000000 00100000>;
  48                 reg = <e0000000 00000200>;
  49                 bus-frequency = <13ab6680>;
  50
  51                 memory-controller@2000 {
  52                         compatible = "fsl,8540-memory-controller";
  53                         reg = <2000 1000>;
  54                         interrupt-parent = <&mpic>;
  55                         interrupts = <2 2>;
  56                 };
  57
  58                 l2-cache-controller@20000 {
  59                         compatible = "fsl,8540-l2-cache-controller";
  60                         reg = <20000 1000>;
  61                         cache-line-size = <20>; // 32 bytes
  62                         cache-size = <40000>;   // L2, 256K
  63                         interrupt-parent = <&mpic>;
  64                         interrupts = <0 2>;
  65                 };
  66
  67                 mdio@24520 {
  68                         device_type = "mdio";
  69                         compatible = "gianfar";
  70                         reg = <24520 20>;
  71                         #address-cells = <1>;
  72                         #size-cells = <0>;
  73                         phy0: ethernet-phy@0 {
  74                                 interrupt-parent = <&mpic>;
  75                                 interrupts = <35 1>;
  76                                 reg = <0>;
  77                                 device_type = "ethernet-phy";
  78                         };
  79                         phy1: ethernet-phy@1 {
  80                                 interrupt-parent = <&mpic>;
  81                                 interrupts = <35 1>;
  82                                 reg = <1>;
  83                                 device_type = "ethernet-phy";
  84                         };
  85                         phy2: ethernet-phy@2 {
  86                                 interrupt-parent = <&mpic>;
  87                                 interrupts = <37 1>;
  88                                 reg = <2>;
  89                                 device_type = "ethernet-phy";
  90                         };
  91                         phy3: ethernet-phy@3 {
  92                                 interrupt-parent = <&mpic>;
  93                                 interrupts = <37 1>;
  94                                 reg = <3>;
  95                                 device_type = "ethernet-phy";
  96                         };
  97                 };
  98
  99                 ethernet@24000 {
 100                         device_type = "network";
 101                         model = "TSEC";
 102                         compatible = "gianfar";
 103                         reg = <24000 1000>;
 104                         address = [ 00 00 0C 00 00 FD ];
 105                         interrupts = <d 2 e 2 12 2>;
 106                         interrupt-parent = <&mpic>;
 107                         phy-handle = <&phy0>;
 108                 };
 109
 110                 ethernet@25000 {
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113                         device_type = "network";
 114                         model = "TSEC";
 115                         compatible = "gianfar";
 116                         reg = <25000 1000>;
 117                         address = [ 00 00 0C 00 01 FD ];
 118                         interrupts = <13 2 14 2 18 2>;
 119                         interrupt-parent = <&mpic>;
 120                         phy-handle = <&phy1>;
 121                 };
 122
 123                 pci@8000 {
 124                         #interrupt-cells = <1>;
 125                         #size-cells = <2>;
 126                         #address-cells = <3>;
 127                         compatible = "85xx";
 128                         device_type = "pci";
 129                         reg = <8000 1000>;
 130                         clock-frequency = <3f940aa>;
 131                         interrupt-map-mask = <f800 0 0 7>;
 132                         interrupt-map = <
 133
 134                                         /* IDSEL 0x2 */
 135                                          1000 0 0 1 &mpic 31 1
 136                                          1000 0 0 2 &mpic 32 1
 137                                          1000 0 0 3 &mpic 33 1
 138                                          1000 0 0 4 &mpic 34 1
 139
 140                                         /* IDSEL 0x3 */
 141                                          1800 0 0 1 &mpic 34 1
 142                                          1800 0 0 2 &mpic 31 1
 143                                          1800 0 0 3 &mpic 32 1
 144                                          1800 0 0 4 &mpic 33 1
 145
 146                                         /* IDSEL 0x4 */
 147                                          2000 0 0 1 &mpic 33 1
 148                                          2000 0 0 2 &mpic 34 1
 149                                          2000 0 0 3 &mpic 31 1
 150                                          2000 0 0 4 &mpic 32 1
 151
 152                                         /* IDSEL 0x5  */
 153                                          2800 0 0 1 &mpic 32 1
 154                                          2800 0 0 2 &mpic 33 1
 155                                          2800 0 0 3 &mpic 34 1
 156                                          2800 0 0 4 &mpic 31 1
 157
 158                                         /* IDSEL 12 */
 159                                          6000 0 0 1 &mpic 31 1
 160                                          6000 0 0 2 &mpic 32 1
 161                                          6000 0 0 3 &mpic 33 1
 162                                          6000 0 0 4 &mpic 34 1
 163
 164                                         /* IDSEL 13 */
 165                                          6800 0 0 1 &mpic 34 1
 166                                          6800 0 0 2 &mpic 31 1
 167                                          6800 0 0 3 &mpic 32 1
 168                                          6800 0 0 4 &mpic 33 1
 169
 170                                         /* IDSEL 14*/
 171                                          7000 0 0 1 &mpic 33 1
 172                                          7000 0 0 2 &mpic 34 1
 173                                          7000 0 0 3 &mpic 31 1
 174                                          7000 0 0 4 &mpic 32 1
 175
 176                                         /* IDSEL 15 */
 177                                          7800 0 0 1 &mpic 32 1
 178                                          7800 0 0 2 &mpic 33 1
 179                                          7800 0 0 3 &mpic 34 1
 180                                          7800 0 0 4 &mpic 31 1
 181
 182                                         /* IDSEL 18 */
 183                                          9000 0 0 1 &mpic 31 1
 184                                          9000 0 0 2 &mpic 32 1
 185                                          9000 0 0 3 &mpic 33 1
 186                                          9000 0 0 4 &mpic 34 1
 187
 188                                         /* IDSEL 19 */
 189                                          9800 0 0 1 &mpic 34 1
 190                                          9800 0 0 2 &mpic 31 1
 191                                          9800 0 0 3 &mpic 32 1
 192                                          9800 0 0 4 &mpic 33 1
 193
 194                                         /* IDSEL 20 */
 195                                          a000 0 0 1 &mpic 33 1
 196                                          a000 0 0 2 &mpic 34 1
 197                                          a000 0 0 3 &mpic 31 1
 198                                          a000 0 0 4 &mpic 32 1
 199
 200                                         /* IDSEL 21 */
 201                                          a800 0 0 1 &mpic 32 1
 202                                          a800 0 0 2 &mpic 33 1
 203                                          a800 0 0 3 &mpic 34 1
 204                                          a800 0 0 4 &mpic 31 1>;
 205
 206                         interrupt-parent = <&mpic>;
 207                         interrupts = <8 0>;
 208                         bus-range = <0 0>;
 209                         ranges = <02000000 0 80000000 80000000 0 20000000
 210                                   01000000 0 00000000 e2000000 0 01000000>;
 211                 };
 212
 213                 mpic: pic@40000 {
 214                         interrupt-controller;
 215                         #address-cells = <0>;
 216                         #interrupt-cells = <2>;
 217                         reg = <40000 40000>;
 218                         built-in;
 219                         device_type = "open-pic";
 220                 };
 221
 222                 cpm@e0000000 {
 223                         #address-cells = <1>;
 224                         #size-cells = <1>;
 225                         #interrupt-cells = <2>;
 226                         device_type = "cpm";
 227                         model = "CPM2";
 228                         ranges = <0 0 c0000>;
 229                         reg = <80000 40000>;
 230                         command-proc = <919c0>;
 231                         brg-frequency = <9d5b340>;
 232
 233                         cpmpic: pic@90c00 {
 234                                 interrupt-controller;
 235                                 #address-cells = <0>;
 236                                 #interrupt-cells = <2>;
 237                                 interrupts = <1e 0>;
 238                                 interrupt-parent = <&mpic>;
 239                                 reg = <90c00 80>;
 240                                 built-in;
 241                                 device_type = "cpm-pic";
 242                         };
 243
 244                         scc@91a00 {
 245                                 device_type = "serial";
 246                                 compatible = "cpm_uart";
 247                                 model = "SCC";
 248                                 device-id = <1>;
 249                                 reg = <91a00 20 88000 100>;
 250                                 clock-setup = <00ffffff 0>;
 251                                 rx-clock = <1>;
 252                                 tx-clock = <1>;
 253                                 current-speed = <1c200>;
 254                                 interrupts = <28 8>;
 255                                 interrupt-parent = <&cpmpic>;
 256                         };
 257
 258                         scc@91a20 {
 259                                 device_type = "serial";
 260                                 compatible = "cpm_uart";
 261                                 model = "SCC";
 262                                 device-id = <2>;
 263                                 reg = <91a20 20 88100 100>;
 264                                 clock-setup = <ff00ffff 90000>;
 265                                 rx-clock = <2>;
 266                                 tx-clock = <2>;
 267                                 current-speed = <1c200>;
 268                                 interrupts = <29 8>;
 269                                 interrupt-parent = <&cpmpic>;
 270                         };
 271
 272                         fcc@91320 {
 273                                 device_type = "network";
 274                                 compatible = "fs_enet";
 275                                 model = "FCC";
 276                                 device-id = <2>;
 277                                 reg = <91320 20 88500 100 913a0 30>;
 278                                 mac-address = [ 00 00 0C 00 02 FD ];
 279                                 clock-setup = <ff00ffff 250000>;
 280                                 rx-clock = <15>;
 281                                 tx-clock = <16>;
 282                                 interrupts = <21 8>;
 283                                 interrupt-parent = <&cpmpic>;
 284                                 phy-handle = <&phy2>;
 285                         };
 286
 287                         fcc@91340 {
 288                                 device_type = "network";
 289                                 compatible = "fs_enet";
 290                                 model = "FCC";
 291                                 device-id = <3>;
 292                                 reg = <91340 20 88600 100 913d0 30>;
 293                                 mac-address = [ 00 00 0C 00 03 FD ];
 294                                 clock-setup = <ffff00ff 3700>;
 295                                 rx-clock = <17>;
 296                                 tx-clock = <18>;
 297                                 interrupts = <22 8>;
 298                                 interrupt-parent = <&cpmpic>;
 299                                 phy-handle = <&phy3>;
 300                         };
 301                 };
 302         };
 303 };