arch/powerpc/boot/dts/mpc8555cds.dts

   1 /*
   2  * MPC8555 CDS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 / {
  14         model = "MPC8555CDS";
  15         compatible = "MPC8555CDS", "MPC85xxCDS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 PowerPC,8555@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         d-cache-line-size = <20>;       // 32 bytes
  27                         i-cache-line-size = <20>;       // 32 bytes
  28                         d-cache-size = <8000>;          // L1, 32K
  29                         i-cache-size = <8000>;          // L1, 32K
  30                         timebase-frequency = <0>;       //  33 MHz, from uboot
  31                         bus-frequency = <0>;    // 166 MHz
  32                         clock-frequency = <0>;  // 825 MHz, from uboot
  33                 };
  34         };
  35
  36         memory {
  37                 device_type = "memory";
  38                 reg = <00000000 08000000>;      // 128M at 0x0
  39         };
  40
  41         soc8555@e0000000 {
  42                 #address-cells = <1>;
  43                 #size-cells = <1>;
  44                 device_type = "soc";
  45                 ranges = <0 e0000000 00100000>;
  46                 reg = <e0000000 00001000>;      // CCSRBAR 1M
  47                 bus-frequency = <0>;
  48
  49                 memory-controller@2000 {
  50                         compatible = "fsl,8555-memory-controller";
  51                         reg = <2000 1000>;
  52                         interrupt-parent = <&mpic>;
  53                         interrupts = <12 2>;
  54                 };
  55
  56                 l2-cache-controller@20000 {
  57                         compatible = "fsl,8555-l2-cache-controller";
  58                         reg = <20000 1000>;
  59                         cache-line-size = <20>; // 32 bytes
  60                         cache-size = <40000>;   // L2, 256K
  61                         interrupt-parent = <&mpic>;
  62                         interrupts = <10 2>;
  63                 };
  64
  65                 i2c@3000 {
  66                         #address-cells = <1>;
  67                         #size-cells = <0>;
  68                         cell-index = <0>;
  69                         compatible = "fsl-i2c";
  70                         reg = <3000 100>;
  71                         interrupts = <2b 2>;
  72                         interrupt-parent = <&mpic>;
  73                         dfsrr;
  74                 };
  75
  76                 mdio@24520 {
  77                         #address-cells = <1>;
  78                         #size-cells = <0>;
  79                         device_type = "mdio";
  80                         compatible = "gianfar";
  81                         reg = <24520 20>;
  82                         phy0: ethernet-phy@0 {
  83                                 interrupt-parent = <&mpic>;
  84                                 interrupts = <5 1>;
  85                                 reg = <0>;
  86                                 device_type = "ethernet-phy";
  87                         };
  88                         phy1: ethernet-phy@1 {
  89                                 interrupt-parent = <&mpic>;
  90                                 interrupts = <5 1>;
  91                                 reg = <1>;
  92                                 device_type = "ethernet-phy";
  93                         };
  94                 };
  95
  96                 ethernet@24000 {
  97                         #address-cells = <1>;
  98                         #size-cells = <0>;
  99                         device_type = "network";
 100                         model = "TSEC";
 101                         compatible = "gianfar";
 102                         reg = <24000 1000>;
 103                         local-mac-address = [ 00 00 00 00 00 00 ];
 104                         interrupts = <1d 2 1e 2 22 2>;
 105                         interrupt-parent = <&mpic>;
 106                         phy-handle = <&phy0>;
 107                 };
 108
 109                 ethernet@25000 {
 110                         #address-cells = <1>;
 111                         #size-cells = <0>;
 112                         device_type = "network";
 113                         model = "TSEC";
 114                         compatible = "gianfar";
 115                         reg = <25000 1000>;
 116                         local-mac-address = [ 00 00 00 00 00 00 ];
 117                         interrupts = <23 2 24 2 28 2>;
 118                         interrupt-parent = <&mpic>;
 119                         phy-handle = <&phy1>;
 120                 };
 121
 122                 serial@4500 {
 123                         device_type = "serial";
 124                         compatible = "ns16550";
 125                         reg = <4500 100>;       // reg base, size
 126                         clock-frequency = <0>;  // should we fill in in uboot?
 127                         interrupts = <2a 2>;
 128                         interrupt-parent = <&mpic>;
 129                 };
 130
 131                 serial@4600 {
 132                         device_type = "serial";
 133                         compatible = "ns16550";
 134                         reg = <4600 100>;       // reg base, size
 135                         clock-frequency = <0>;  // should we fill in in uboot?
 136                         interrupts = <2a 2>;
 137                         interrupt-parent = <&mpic>;
 138                 };
 139
 140                 mpic: pic@40000 {
 141                         clock-frequency = <0>;
 142                         interrupt-controller;
 143                         #address-cells = <0>;
 144                         #interrupt-cells = <2>;
 145                         reg = <40000 40000>;
 146                         compatible = "chrp,open-pic";
 147                         device_type = "open-pic";
 148                         big-endian;
 149                 };
 150
 151                 cpm@919c0 {
 152                         #address-cells = <1>;
 153                         #size-cells = <1>;
 154                         compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
 155                         reg = <919c0 30>;
 156                         ranges;
 157
 158                         muram@80000 {
 159                                 #address-cells = <1>;
 160                                 #size-cells = <1>;
 161                                 ranges = <0 80000 10000>;
 162
 163                                 data@0 {
 164                                         compatible = "fsl,cpm-muram-data";
 165                                         reg = <0 2000 9000 1000>;
 166                                 };
 167                         };
 168
 169                         brg@919f0 {
 170                                 compatible = "fsl,mpc8555-brg",
 171                                              "fsl,cpm2-brg",
 172                                              "fsl,cpm-brg";
 173                                 reg = <919f0 10 915f0 10>;
 174                         };
 175
 176                         cpmpic: pic@90c00 {
 177                                 interrupt-controller;
 178                                 #address-cells = <0>;
 179                                 #interrupt-cells = <2>;
 180                                 interrupts = <2e 2>;
 181                                 interrupt-parent = <&mpic>;
 182                                 reg = <90c00 80>;
 183                                 compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
 184                         };
 185                 };
 186         };
 187
 188         pci1: pci@e0008000 {
 189                 interrupt-map-mask = <1f800 0 0 7>;
 190                 interrupt-map = <
 191
 192                         /* IDSEL 0x10 */
 193                         08000 0 0 1 &mpic 0 1
 194                         08000 0 0 2 &mpic 1 1
 195                         08000 0 0 3 &mpic 2 1
 196                         08000 0 0 4 &mpic 3 1
 197
 198                         /* IDSEL 0x11 */
 199                         08800 0 0 1 &mpic 0 1
 200                         08800 0 0 2 &mpic 1 1
 201                         08800 0 0 3 &mpic 2 1
 202                         08800 0 0 4 &mpic 3 1
 203
 204                         /* IDSEL 0x12 (Slot 1) */
 205                         09000 0 0 1 &mpic 0 1
 206                         09000 0 0 2 &mpic 1 1
 207                         09000 0 0 3 &mpic 2 1
 208                         09000 0 0 4 &mpic 3 1
 209
 210                         /* IDSEL 0x13 (Slot 2) */
 211                         09800 0 0 1 &mpic 1 1
 212                         09800 0 0 2 &mpic 2 1
 213                         09800 0 0 3 &mpic 3 1
 214                         09800 0 0 4 &mpic 0 1
 215
 216                         /* IDSEL 0x14 (Slot 3) */
 217                         0a000 0 0 1 &mpic 2 1
 218                         0a000 0 0 2 &mpic 3 1
 219                         0a000 0 0 3 &mpic 0 1
 220                         0a000 0 0 4 &mpic 1 1
 221
 222                         /* IDSEL 0x15 (Slot 4) */
 223                         0a800 0 0 1 &mpic 3 1
 224                         0a800 0 0 2 &mpic 0 1
 225                         0a800 0 0 3 &mpic 1 1
 226                         0a800 0 0 4 &mpic 2 1
 227
 228                         /* Bus 1 (Tundra Bridge) */
 229                         /* IDSEL 0x12 (ISA bridge) */
 230                         19000 0 0 1 &mpic 0 1
 231                         19000 0 0 2 &mpic 1 1
 232                         19000 0 0 3 &mpic 2 1
 233                         19000 0 0 4 &mpic 3 1>;
 234                 interrupt-parent = <&mpic>;
 235                 interrupts = <18 2>;
 236                 bus-range = <0 0>;
 237                 ranges = <02000000 0 80000000 80000000 0 20000000
 238                           01000000 0 00000000 e2000000 0 00100000>;
 239                 clock-frequency = <3f940aa>;
 240                 #interrupt-cells = <1>;
 241                 #size-cells = <2>;
 242                 #address-cells = <3>;
 243                 reg = <e0008000 1000>;
 244                 compatible = "fsl,mpc8540-pci";
 245                 device_type = "pci";
 246
 247                 i8259@19000 {
 248                         interrupt-controller;
 249                         device_type = "interrupt-controller";
 250                         reg = <19000 0 0 0 1>;
 251                         #address-cells = <0>;
 252                         #interrupt-cells = <2>;
 253                         compatible = "chrp,iic";
 254                         interrupts = <1>;
 255                         interrupt-parent = <&pci1>;
 256                 };
 257         };
 258
 259         pci@e0009000 {
 260                 interrupt-map-mask = <f800 0 0 7>;
 261                 interrupt-map = <
 262
 263                         /* IDSEL 0x15 */
 264                         a800 0 0 1 &mpic b 1
 265                         a800 0 0 2 &mpic b 1
 266                         a800 0 0 3 &mpic b 1
 267                         a800 0 0 4 &mpic b 1>;
 268                 interrupt-parent = <&mpic>;
 269                 interrupts = <19 2>;
 270                 bus-range = <0 0>;
 271                 ranges = <02000000 0 a0000000 a0000000 0 20000000
 272                           01000000 0 00000000 e3000000 0 00100000>;
 273                 clock-frequency = <3f940aa>;
 274                 #interrupt-cells = <1>;
 275                 #size-cells = <2>;
 276                 #address-cells = <3>;
 277                 reg = <e0009000 1000>;
 278                 compatible = "fsl,mpc8540-pci";
 279                 device_type = "pci";
 280         };
 281 };