2 * MPC8544 DS Device Tree Source
4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
15 compatible = "MPC8544DS", "MPC85xxDS";
37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <0x8000>; // L1, 32K
41 timebase-frequency = <0>;
43 clock-frequency = <0>;
44 next-level-cache = <&L2>;
49 device_type = "memory";
50 reg = <0x0 0x0>; // Filled by U-Boot
58 ranges = <0x0 0xe0000000 0x100000>;
59 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
60 bus-frequency = <0>; // Filled out by uboot.
62 memory-controller@2000 {
63 compatible = "fsl,8544-memory-controller";
64 reg = <0x2000 0x1000>;
65 interrupt-parent = <&mpic>;
69 L2: l2-cache-controller@20000 {
70 compatible = "fsl,8544-l2-cache-controller";
71 reg = <0x20000 0x1000>;
72 cache-line-size = <32>; // 32 bytes
73 cache-size = <0x40000>; // L2, 256K
74 interrupt-parent = <&mpic>;
82 compatible = "fsl-i2c";
85 interrupt-parent = <&mpic>;
93 compatible = "fsl-i2c";
96 interrupt-parent = <&mpic>;
101 #address-cells = <1>;
103 compatible = "fsl,gianfar-mdio";
104 reg = <0x24520 0x20>;
106 phy0: ethernet-phy@0 {
107 interrupt-parent = <&mpic>;
110 device_type = "ethernet-phy";
112 phy1: ethernet-phy@1 {
113 interrupt-parent = <&mpic>;
116 device_type = "ethernet-phy";
121 #address-cells = <1>;
123 compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
125 ranges = <0x0 0x21100 0x200>;
128 compatible = "fsl,mpc8544-dma-channel",
129 "fsl,eloplus-dma-channel";
132 interrupt-parent = <&mpic>;
136 compatible = "fsl,mpc8544-dma-channel",
137 "fsl,eloplus-dma-channel";
140 interrupt-parent = <&mpic>;
144 compatible = "fsl,mpc8544-dma-channel",
145 "fsl,eloplus-dma-channel";
148 interrupt-parent = <&mpic>;
152 compatible = "fsl,mpc8544-dma-channel",
153 "fsl,eloplus-dma-channel";
156 interrupt-parent = <&mpic>;
161 enet0: ethernet@24000 {
163 device_type = "network";
165 compatible = "gianfar";
166 reg = <0x24000 0x1000>;
167 local-mac-address = [ 00 00 00 00 00 00 ];
168 interrupts = <29 2 30 2 34 2>;
169 interrupt-parent = <&mpic>;
170 phy-handle = <&phy0>;
171 phy-connection-type = "rgmii-id";
174 enet1: ethernet@26000 {
176 device_type = "network";
178 compatible = "gianfar";
179 reg = <0x26000 0x1000>;
180 local-mac-address = [ 00 00 00 00 00 00 ];
181 interrupts = <31 2 32 2 33 2>;
182 interrupt-parent = <&mpic>;
183 phy-handle = <&phy1>;
184 phy-connection-type = "rgmii-id";
187 serial0: serial@4500 {
189 device_type = "serial";
190 compatible = "ns16550";
191 reg = <0x4500 0x100>;
192 clock-frequency = <0>;
194 interrupt-parent = <&mpic>;
197 serial1: serial@4600 {
199 device_type = "serial";
200 compatible = "ns16550";
201 reg = <0x4600 0x100>;
202 clock-frequency = <0>;
204 interrupt-parent = <&mpic>;
207 global-utilities@e0000 { //global utilities block
208 compatible = "fsl,mpc8548-guts";
209 reg = <0xe0000 0x1000>;
214 interrupt-controller;
215 #address-cells = <0>;
216 #interrupt-cells = <2>;
217 reg = <0x40000 0x40000>;
218 compatible = "chrp,open-pic";
219 device_type = "open-pic";
223 compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
224 reg = <0x41600 0x80>;
225 msi-available-ranges = <0 0x100>;
235 interrupt-parent = <&mpic>;
241 compatible = "fsl,mpc8540-pci";
243 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
246 /* IDSEL 0x11 J17 Slot 1 */
247 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
248 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
249 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
250 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
252 /* IDSEL 0x12 J16 Slot 2 */
254 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
255 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
256 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
257 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
259 interrupt-parent = <&mpic>;
262 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
263 0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
264 clock-frequency = <66666666>;
265 #interrupt-cells = <1>;
267 #address-cells = <3>;
268 reg = <0xe0008000 0x1000>;
271 pci1: pcie@e0009000 {
273 compatible = "fsl,mpc8548-pcie";
275 #interrupt-cells = <1>;
277 #address-cells = <3>;
278 reg = <0xe0009000 0x1000>;
280 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
281 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
282 clock-frequency = <33333333>;
283 interrupt-parent = <&mpic>;
285 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
288 0000 0x0 0x0 0x1 &mpic 0x4 0x1
289 0000 0x0 0x0 0x2 &mpic 0x5 0x1
290 0000 0x0 0x0 0x3 &mpic 0x6 0x1
291 0000 0x0 0x0 0x4 &mpic 0x7 0x1
294 reg = <0x0 0x0 0x0 0x0 0x0>;
296 #address-cells = <3>;
298 ranges = <0x2000000 0x0 0x80000000
299 0x2000000 0x0 0x80000000
308 pci2: pcie@e000a000 {
310 compatible = "fsl,mpc8548-pcie";
312 #interrupt-cells = <1>;
314 #address-cells = <3>;
315 reg = <0xe000a000 0x1000>;
317 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
318 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
319 clock-frequency = <33333333>;
320 interrupt-parent = <&mpic>;
322 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
325 0000 0x0 0x0 0x1 &mpic 0x0 0x1
326 0000 0x0 0x0 0x2 &mpic 0x1 0x1
327 0000 0x0 0x0 0x3 &mpic 0x2 0x1
328 0000 0x0 0x0 0x4 &mpic 0x3 0x1
331 reg = <0x0 0x0 0x0 0x0 0x0>;
333 #address-cells = <3>;
335 ranges = <0x2000000 0x0 0xa0000000
336 0x2000000 0x0 0xa0000000
345 pci3: pcie@e000b000 {
347 compatible = "fsl,mpc8548-pcie";
349 #interrupt-cells = <1>;
351 #address-cells = <3>;
352 reg = <0xe000b000 0x1000>;
354 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
355 0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
356 clock-frequency = <33333333>;
357 interrupt-parent = <&mpic>;
359 interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
362 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
363 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
364 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
365 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
368 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
371 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
372 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
374 // IDSEL 0x1f IDE/SATA
375 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
376 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
380 reg = <0x0 0x0 0x0 0x0 0x0>;
382 #address-cells = <3>;
384 ranges = <0x2000000 0x0 0xb0000000
385 0x2000000 0x0 0xb0000000
393 reg = <0x0 0x0 0x0 0x0 0x0>;
395 #address-cells = <3>;
396 ranges = <0x2000000 0x0 0xb0000000
397 0x2000000 0x0 0xb0000000
405 #interrupt-cells = <2>;
407 #address-cells = <2>;
408 reg = <0xf000 0x0 0x0 0x0 0x0>;
412 interrupt-parent = <&i8259>;
414 i8259: interrupt-controller@20 {
418 interrupt-controller;
419 device_type = "interrupt-controller";
420 #address-cells = <0>;
421 #interrupt-cells = <2>;
422 compatible = "chrp,iic";
424 interrupt-parent = <&mpic>;
429 #address-cells = <1>;
430 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
431 interrupts = <1 3 12 3>;
432 interrupt-parent = <&i8259>;
436 compatible = "pnpPNP,303";
441 compatible = "pnpPNP,f03";
446 compatible = "pnpPNP,b00";
447 reg = <0x1 0x70 0x2>;
451 reg = <0x1 0x400 0x80>;