Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[pandora-kernel.git] / arch / powerpc / boot / dts / mpc8378_mds.dts
1 /*
2  * MPC8378E MDS Device Tree Source
3  *
4  * Copyright 2007 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12 /dts-v1/;
13
14 / {
15         model = "fsl,mpc8378emds";
16         compatible = "fsl,mpc8378emds","fsl,mpc837xmds";
17         #address-cells = <1>;
18         #size-cells = <1>;
19
20         aliases {
21                 ethernet0 = &enet0;
22                 ethernet1 = &enet1;
23                 serial0 = &serial0;
24                 serial1 = &serial1;
25                 pci0 = &pci0;
26                 pci1 = &pci1;
27                 pci2 = &pci2;
28         };
29
30         cpus {
31                 #address-cells = <1>;
32                 #size-cells = <0>;
33
34                 PowerPC,8378@0 {
35                         device_type = "cpu";
36                         reg = <0x0>;
37                         d-cache-line-size = <32>;
38                         i-cache-line-size = <32>;
39                         d-cache-size = <32768>;
40                         i-cache-size = <32768>;
41                         timebase-frequency = <0>;
42                         bus-frequency = <0>;
43                         clock-frequency = <0>;
44                 };
45         };
46
47         memory {
48                 device_type = "memory";
49                 reg = <0x00000000 0x20000000>;  // 512MB at 0
50         };
51
52         localbus@e0005000 {
53                 #address-cells = <2>;
54                 #size-cells = <1>;
55                 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
56                 reg = <0xe0005000 0x1000>;
57                 interrupts = <77 0x8>;
58                 interrupt-parent = <&ipic>;
59
60                 // booting from NOR flash
61                 ranges = <0 0x0 0xfe000000 0x02000000
62                           1 0x0 0xf8000000 0x00008000
63                           3 0x0 0xe0600000 0x00008000>;
64
65                 flash@0,0 {
66                         #address-cells = <1>;
67                         #size-cells = <1>;
68                         compatible = "cfi-flash";
69                         reg = <0 0x0 0x2000000>;
70                         bank-width = <2>;
71                         device-width = <1>;
72
73                         u-boot@0 {
74                                 reg = <0x0 0x100000>;
75                                 read-only;
76                         };
77
78                         fs@100000 {
79                                 reg = <0x100000 0x800000>;
80                         };
81
82                         kernel@1d00000 {
83                                 reg = <0x1d00000 0x200000>;
84                         };
85
86                         dtb@1f00000 {
87                                 reg = <0x1f00000 0x100000>;
88                         };
89                 };
90
91                 bcsr@1,0 {
92                         reg = <1 0x0 0x8000>;
93                         compatible = "fsl,mpc837xmds-bcsr";
94                 };
95
96                 nand@3,0 {
97                         #address-cells = <1>;
98                         #size-cells = <1>;
99                         compatible = "fsl,mpc8378-fcm-nand",
100                                      "fsl,elbc-fcm-nand";
101                         reg = <3 0x0 0x8000>;
102
103                         u-boot@0 {
104                                 reg = <0x0 0x100000>;
105                                 read-only;
106                         };
107
108                         kernel@100000 {
109                                 reg = <0x100000 0x300000>;
110                         };
111
112                         fs@400000 {
113                                 reg = <0x400000 0x1c00000>;
114                         };
115                 };
116         };
117
118         soc@e0000000 {
119                 #address-cells = <1>;
120                 #size-cells = <1>;
121                 device_type = "soc";
122                 compatible = "simple-bus";
123                 ranges = <0x0 0xe0000000 0x00100000>;
124                 reg = <0xe0000000 0x00000200>;
125                 bus-frequency = <0>;
126
127                 wdt@200 {
128                         compatible = "mpc83xx_wdt";
129                         reg = <0x200 0x100>;
130                 };
131
132                 sleep-nexus {
133                         #address-cells = <1>;
134                         #size-cells = <1>;
135                         compatible = "simple-bus";
136                         sleep = <&pmc 0x0c000000>;
137                         ranges;
138
139                         i2c@3000 {
140                                 #address-cells = <1>;
141                                 #size-cells = <0>;
142                                 cell-index = <0>;
143                                 compatible = "fsl-i2c";
144                                 reg = <0x3000 0x100>;
145                                 interrupts = <14 0x8>;
146                                 interrupt-parent = <&ipic>;
147                                 dfsrr;
148
149                                 rtc@68 {
150                                         compatible = "dallas,ds1374";
151                                         reg = <0x68>;
152                                         interrupts = <19 0x8>;
153                                         interrupt-parent = <&ipic>;
154                                 };
155                         };
156
157                         sdhci@2e000 {
158                                 compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
159                                 reg = <0x2e000 0x1000>;
160                                 interrupts = <42 0x8>;
161                                 interrupt-parent = <&ipic>;
162                                 /* Filled in by U-Boot */
163                                 clock-frequency = <0>;
164                         };
165                 };
166
167                 i2c@3100 {
168                         #address-cells = <1>;
169                         #size-cells = <0>;
170                         cell-index = <1>;
171                         compatible = "fsl-i2c";
172                         reg = <0x3100 0x100>;
173                         interrupts = <15 0x8>;
174                         interrupt-parent = <&ipic>;
175                         dfsrr;
176                 };
177
178                 spi@7000 {
179                         cell-index = <0>;
180                         compatible = "fsl,spi";
181                         reg = <0x7000 0x1000>;
182                         interrupts = <16 0x8>;
183                         interrupt-parent = <&ipic>;
184                         mode = "cpu";
185                 };
186
187                 dma@82a8 {
188                         #address-cells = <1>;
189                         #size-cells = <1>;
190                         compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
191                         reg = <0x82a8 4>;
192                         ranges = <0 0x8100 0x1a8>;
193                         interrupt-parent = <&ipic>;
194                         interrupts = <71 8>;
195                         cell-index = <0>;
196                         dma-channel@0 {
197                                 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
198                                 reg = <0 0x80>;
199                                 cell-index = <0>;
200                                 interrupt-parent = <&ipic>;
201                                 interrupts = <71 8>;
202                         };
203                         dma-channel@80 {
204                                 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
205                                 reg = <0x80 0x80>;
206                                 cell-index = <1>;
207                                 interrupt-parent = <&ipic>;
208                                 interrupts = <71 8>;
209                         };
210                         dma-channel@100 {
211                                 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
212                                 reg = <0x100 0x80>;
213                                 cell-index = <2>;
214                                 interrupt-parent = <&ipic>;
215                                 interrupts = <71 8>;
216                         };
217                         dma-channel@180 {
218                                 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
219                                 reg = <0x180 0x28>;
220                                 cell-index = <3>;
221                                 interrupt-parent = <&ipic>;
222                                 interrupts = <71 8>;
223                         };
224                 };
225
226                 usb@23000 {
227                         compatible = "fsl-usb2-dr";
228                         reg = <0x23000 0x1000>;
229                         #address-cells = <1>;
230                         #size-cells = <0>;
231                         interrupt-parent = <&ipic>;
232                         interrupts = <38 0x8>;
233                         dr_mode = "host";
234                         phy_type = "ulpi";
235                         sleep = <&pmc 0x00c00000>;
236                 };
237
238                 enet0: ethernet@24000 {
239                         #address-cells = <1>;
240                         #size-cells = <1>;
241                         cell-index = <0>;
242                         device_type = "network";
243                         model = "eTSEC";
244                         compatible = "gianfar";
245                         reg = <0x24000 0x1000>;
246                         ranges = <0x0 0x24000 0x1000>;
247                         local-mac-address = [ 00 00 00 00 00 00 ];
248                         interrupts = <32 0x8 33 0x8 34 0x8>;
249                         phy-connection-type = "mii";
250                         interrupt-parent = <&ipic>;
251                         tbi-handle = <&tbi0>;
252                         phy-handle = <&phy2>;
253                         sleep = <&pmc 0xc0000000>;
254                         fsl,magic-packet;
255
256                         mdio@520 {
257                                 #address-cells = <1>;
258                                 #size-cells = <0>;
259                                 compatible = "fsl,gianfar-mdio";
260                                 reg = <0x520 0x20>;
261
262                                 phy2: ethernet-phy@2 {
263                                         interrupt-parent = <&ipic>;
264                                         interrupts = <17 0x8>;
265                                         reg = <0x2>;
266                                         device_type = "ethernet-phy";
267                                 };
268
269                                 phy3: ethernet-phy@3 {
270                                         interrupt-parent = <&ipic>;
271                                         interrupts = <18 0x8>;
272                                         reg = <0x3>;
273                                         device_type = "ethernet-phy";
274                                 };
275
276                                 tbi0: tbi-phy@11 {
277                                         reg = <0x11>;
278                                         device_type = "tbi-phy";
279                                 };
280                         };
281                 };
282
283                 enet1: ethernet@25000 {
284                         #address-cells = <1>;
285                         #size-cells = <1>;
286                         cell-index = <1>;
287                         device_type = "network";
288                         model = "eTSEC";
289                         compatible = "gianfar";
290                         reg = <0x25000 0x1000>;
291                         ranges = <0x0 0x25000 0x1000>;
292                         local-mac-address = [ 00 00 00 00 00 00 ];
293                         interrupts = <35 0x8 36 0x8 37 0x8>;
294                         phy-connection-type = "mii";
295                         interrupt-parent = <&ipic>;
296                         tbi-handle = <&tbi1>;
297                         phy-handle = <&phy3>;
298                         sleep = <&pmc 0x30000000>;
299                         fsl,magic-packet;
300
301                         mdio@520 {
302                                 #address-cells = <1>;
303                                 #size-cells = <0>;
304                                 compatible = "fsl,gianfar-tbi";
305                                 reg = <0x520 0x20>;
306
307                                 tbi1: tbi-phy@11 {
308                                         reg = <0x11>;
309                                         device_type = "tbi-phy";
310                                 };
311                         };
312                 };
313
314                 serial0: serial@4500 {
315                         cell-index = <0>;
316                         device_type = "serial";
317                         compatible = "ns16550";
318                         reg = <0x4500 0x100>;
319                         clock-frequency = <0>;
320                         interrupts = <9 0x8>;
321                         interrupt-parent = <&ipic>;
322                 };
323
324                 serial1: serial@4600 {
325                         cell-index = <1>;
326                         device_type = "serial";
327                         compatible = "ns16550";
328                         reg = <0x4600 0x100>;
329                         clock-frequency = <0>;
330                         interrupts = <10 0x8>;
331                         interrupt-parent = <&ipic>;
332                 };
333
334                 crypto@30000 {
335                         compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
336                                      "fsl,sec2.1", "fsl,sec2.0";
337                         reg = <0x30000 0x10000>;
338                         interrupts = <11 0x8>;
339                         interrupt-parent = <&ipic>;
340                         fsl,num-channels = <4>;
341                         fsl,channel-fifo-len = <24>;
342                         fsl,exec-units-mask = <0x9fe>;
343                         fsl,descriptor-types-mask = <0x3ab0ebf>;
344                         sleep = <&pmc 0x03000000>;
345                 };
346
347                 /* IPIC
348                  * interrupts cell = <intr #, sense>
349                  * sense values match linux IORESOURCE_IRQ_* defines:
350                  * sense == 8: Level, low assertion
351                  * sense == 2: Edge, high-to-low change
352                  */
353                 ipic: pic@700 {
354                         compatible = "fsl,ipic";
355                         interrupt-controller;
356                         #address-cells = <0>;
357                         #interrupt-cells = <2>;
358                         reg = <0x700 0x100>;
359                 };
360
361                 pmc: power@b00 {
362                         compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc";
363                         reg = <0xb00 0x100 0xa00 0x100>;
364                         interrupts = <80 0x8>;
365                         interrupt-parent = <&ipic>;
366                 };
367         };
368
369         pci0: pci@e0008500 {
370                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
371                 interrupt-map = <
372
373                                 /* IDSEL 0x11 */
374                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
375                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
376                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
377                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
378
379                                 /* IDSEL 0x12 */
380                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
381                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
382                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
383                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
384
385                                 /* IDSEL 0x13 */
386                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
387                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
388                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
389                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
390
391                                 /* IDSEL 0x15 */
392                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
393                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
394                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
395                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
396
397                                 /* IDSEL 0x16 */
398                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
399                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
400                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
401                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
402
403                                 /* IDSEL 0x17 */
404                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
405                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
406                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
407                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
408
409                                 /* IDSEL 0x18 */
410                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
411                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
412                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
413                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
414                 interrupt-parent = <&ipic>;
415                 interrupts = <66 0x8>;
416                 bus-range = <0x0 0x0>;
417                 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
418                           0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
419                           0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
420                 clock-frequency = <0>;
421                 sleep = <&pmc 0x00010000>;
422                 #interrupt-cells = <1>;
423                 #size-cells = <2>;
424                 #address-cells = <3>;
425                 reg = <0xe0008500 0x100         /* internal registers */
426                        0xe0008300 0x8>;         /* config space access registers */
427                 compatible = "fsl,mpc8349-pci";
428                 device_type = "pci";
429         };
430
431         pci1: pcie@e0009000 {
432                 #address-cells = <3>;
433                 #size-cells = <2>;
434                 #interrupt-cells = <1>;
435                 device_type = "pci";
436                 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
437                 reg = <0xe0009000 0x00001000>;
438                 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
439                           0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
440                 bus-range = <0 255>;
441                 interrupt-map-mask = <0xf800 0 0 7>;
442                 interrupt-map = <0 0 0 1 &ipic 1 8
443                                  0 0 0 2 &ipic 1 8
444                                  0 0 0 3 &ipic 1 8
445                                  0 0 0 4 &ipic 1 8>;
446                 sleep = <&pmc 0x00300000>;
447                 clock-frequency = <0>;
448
449                 pcie@0 {
450                         #address-cells = <3>;
451                         #size-cells = <2>;
452                         device_type = "pci";
453                         reg = <0 0 0 0 0>;
454                         ranges = <0x02000000 0 0xa8000000
455                                   0x02000000 0 0xa8000000
456                                   0 0x10000000
457                                   0x01000000 0 0x00000000
458                                   0x01000000 0 0x00000000
459                                   0 0x00800000>;
460                 };
461         };
462
463         pci2: pcie@e000a000 {
464                 #address-cells = <3>;
465                 #size-cells = <2>;
466                 #interrupt-cells = <1>;
467                 device_type = "pci";
468                 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
469                 reg = <0xe000a000 0x00001000>;
470                 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
471                           0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
472                 bus-range = <0 255>;
473                 interrupt-map-mask = <0xf800 0 0 7>;
474                 interrupt-map = <0 0 0 1 &ipic 2 8
475                                  0 0 0 2 &ipic 2 8
476                                  0 0 0 3 &ipic 2 8
477                                  0 0 0 4 &ipic 2 8>;
478                 sleep = <&pmc 0x000c0000>;
479                 clock-frequency = <0>;
480
481                 pcie@0 {
482                         #address-cells = <3>;
483                         #size-cells = <2>;
484                         device_type = "pci";
485                         reg = <0 0 0 0 0>;
486                         ranges = <0x02000000 0 0xc8000000
487                                   0x02000000 0 0xc8000000
488                                   0 0x10000000
489                                   0x01000000 0 0x00000000
490                                   0x01000000 0 0x00000000
491                                   0 0x00800000>;
492                 };
493         };
494 };