2 * MPC8360E EMDS Device Tree Source
4 * Copyright 2006 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
14 /memreserve/ 00000000 1000000;
19 compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
38 d-cache-line-size = <20>; // 32 bytes
39 i-cache-line-size = <20>; // 32 bytes
40 d-cache-size = <8000>; // L1, 32K
41 i-cache-size = <8000>; // L1, 32K
42 timebase-frequency = <3EF1480>;
43 bus-frequency = <FBC5200>;
44 clock-frequency = <1F78A400>;
49 device_type = "memory";
50 reg = <00000000 10000000>;
54 device_type = "board-control";
55 reg = <f8000000 8000>;
62 ranges = <0 e0000000 00100000>;
63 reg = <e0000000 00000200>;
64 bus-frequency = <FBC5200>;
67 device_type = "watchdog";
68 compatible = "mpc83xx_wdt";
76 compatible = "fsl-i2c";
79 interrupt-parent = < &ipic >;
83 compatible = "dallas,ds1374";
92 compatible = "fsl-i2c";
95 interrupt-parent = < &ipic >;
99 serial0: serial@4500 {
101 device_type = "serial";
102 compatible = "ns16550";
104 clock-frequency = <FBC5200>;
106 interrupt-parent = < &ipic >;
109 serial1: serial@4600 {
111 device_type = "serial";
112 compatible = "ns16550";
114 clock-frequency = <FBC5200>;
116 interrupt-parent = < &ipic >;
120 device_type = "crypto";
122 compatible = "talitos";
125 interrupt-parent = < &ipic >;
127 channel-fifo-len = <18>;
128 exec-units-mask = <0000007e>;
129 /* desc mask is for rev1.x, we need runtime fixup for >=2.x */
130 descriptor-types-mask = <01010ebf>;
134 interrupt-controller;
135 #address-cells = <0>;
136 #interrupt-cells = <2>;
138 device_type = "ipic";
143 device_type = "par_io";
148 /* port pin dir open_drain assignment has_irq */
149 0 3 1 0 1 0 /* TxD0 */
150 0 4 1 0 1 0 /* TxD1 */
151 0 5 1 0 1 0 /* TxD2 */
152 0 6 1 0 1 0 /* TxD3 */
153 1 6 1 0 3 0 /* TxD4 */
154 1 7 1 0 1 0 /* TxD5 */
155 1 9 1 0 2 0 /* TxD6 */
156 1 a 1 0 2 0 /* TxD7 */
157 0 9 2 0 1 0 /* RxD0 */
158 0 a 2 0 1 0 /* RxD1 */
159 0 b 2 0 1 0 /* RxD2 */
160 0 c 2 0 1 0 /* RxD3 */
161 0 d 2 0 1 0 /* RxD4 */
162 1 1 2 0 2 0 /* RxD5 */
163 1 0 2 0 2 0 /* RxD6 */
164 1 4 2 0 2 0 /* RxD7 */
165 0 7 1 0 1 0 /* TX_EN */
166 0 8 1 0 1 0 /* TX_ER */
167 0 f 2 0 1 0 /* RX_DV */
168 0 10 2 0 1 0 /* RX_ER */
169 0 0 2 0 1 0 /* RX_CLK */
170 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
171 2 8 2 0 1 0>; /* GTX125 - CLK9 */
175 /* port pin dir open_drain assignment has_irq */
176 0 11 1 0 1 0 /* TxD0 */
177 0 12 1 0 1 0 /* TxD1 */
178 0 13 1 0 1 0 /* TxD2 */
179 0 14 1 0 1 0 /* TxD3 */
180 1 2 1 0 1 0 /* TxD4 */
181 1 3 1 0 2 0 /* TxD5 */
182 1 5 1 0 3 0 /* TxD6 */
183 1 8 1 0 3 0 /* TxD7 */
184 0 17 2 0 1 0 /* RxD0 */
185 0 18 2 0 1 0 /* RxD1 */
186 0 19 2 0 1 0 /* RxD2 */
187 0 1a 2 0 1 0 /* RxD3 */
188 0 1b 2 0 1 0 /* RxD4 */
189 1 c 2 0 2 0 /* RxD5 */
190 1 d 2 0 3 0 /* RxD6 */
191 1 b 2 0 2 0 /* RxD7 */
192 0 15 1 0 1 0 /* TX_EN */
193 0 16 1 0 1 0 /* TX_ER */
194 0 1d 2 0 1 0 /* RX_DV */
195 0 1e 2 0 1 0 /* RX_ER */
196 0 1f 2 0 1 0 /* RX_CLK */
197 2 2 1 0 2 0 /* GTX_CLK - CLK10 */
198 2 3 2 0 1 0 /* GTX125 - CLK4 */
199 0 1 3 0 2 0 /* MDIO */
200 0 2 1 0 1 0>; /* MDC */
207 #address-cells = <1>;
210 compatible = "fsl,qe";
211 ranges = <0 e0100000 00100000>;
212 reg = <e0100000 480>;
214 bus-frequency = <179A7B00>;
217 #address-cells = <1>;
219 compatible = "fsl,qe-muram", "fsl,cpm-muram";
220 ranges = <0 00010000 0000c000>;
223 compatible = "fsl,qe-muram-data",
224 "fsl,cpm-muram-data";
231 compatible = "fsl,spi";
234 interrupt-parent = < &qeic >;
240 compatible = "fsl,spi";
243 interrupt-parent = < &qeic >;
248 compatible = "qe_udc";
249 reg = <6c0 40 8B00 100>;
251 interrupt-parent = < &qeic >;
256 device_type = "network";
257 compatible = "ucc_geth";
263 interrupt-parent = < &qeic >;
264 local-mac-address = [ 00 00 00 00 00 00 ];
265 rx-clock-name = "none";
266 tx-clock-name = "clk9";
267 phy-handle = < &phy0 >;
268 phy-connection-type = "rgmii-id";
269 pio-handle = < &pio1 >;
273 device_type = "network";
274 compatible = "ucc_geth";
280 interrupt-parent = < &qeic >;
281 local-mac-address = [ 00 00 00 00 00 00 ];
282 rx-clock-name = "none";
283 tx-clock-name = "clk4";
284 phy-handle = < &phy1 >;
285 phy-connection-type = "rgmii-id";
286 pio-handle = < &pio2 >;
290 #address-cells = <1>;
293 compatible = "fsl,ucc-mdio";
295 phy0: ethernet-phy@00 {
296 interrupt-parent = < &ipic >;
299 device_type = "ethernet-phy";
301 phy1: ethernet-phy@01 {
302 interrupt-parent = < &ipic >;
305 device_type = "ethernet-phy";
309 qeic: interrupt-controller@80 {
310 interrupt-controller;
311 compatible = "fsl,qe-ic";
312 #address-cells = <0>;
313 #interrupt-cells = <1>;
316 interrupts = <20 8 21 8>; //high:32 low:33
317 interrupt-parent = < &ipic >;
323 interrupt-map-mask = <f800 0 0 7>;
326 /* IDSEL 0x11 AD17 */
327 8800 0 0 1 &ipic 14 8
328 8800 0 0 2 &ipic 15 8
329 8800 0 0 3 &ipic 16 8
330 8800 0 0 4 &ipic 17 8
332 /* IDSEL 0x12 AD18 */
333 9000 0 0 1 &ipic 16 8
334 9000 0 0 2 &ipic 17 8
335 9000 0 0 3 &ipic 14 8
336 9000 0 0 4 &ipic 15 8
338 /* IDSEL 0x13 AD19 */
339 9800 0 0 1 &ipic 17 8
340 9800 0 0 2 &ipic 14 8
341 9800 0 0 3 &ipic 15 8
342 9800 0 0 4 &ipic 16 8
345 a800 0 0 1 &ipic 14 8
346 a800 0 0 2 &ipic 15 8
347 a800 0 0 3 &ipic 16 8
348 a800 0 0 4 &ipic 17 8
351 b000 0 0 1 &ipic 17 8
352 b000 0 0 2 &ipic 14 8
353 b000 0 0 3 &ipic 15 8
354 b000 0 0 4 &ipic 16 8
357 b800 0 0 1 &ipic 16 8
358 b800 0 0 2 &ipic 17 8
359 b800 0 0 3 &ipic 14 8
360 b800 0 0 4 &ipic 15 8
363 c000 0 0 1 &ipic 15 8
364 c000 0 0 2 &ipic 16 8
365 c000 0 0 3 &ipic 17 8
366 c000 0 0 4 &ipic 14 8>;
367 interrupt-parent = < &ipic >;
370 ranges = <02000000 0 a0000000 a0000000 0 10000000
371 42000000 0 80000000 80000000 0 10000000
372 01000000 0 00000000 e2000000 0 00100000>;
373 clock-frequency = <3f940aa>;
374 #interrupt-cells = <1>;
376 #address-cells = <3>;
377 reg = <e0008500 100>;
378 compatible = "fsl,mpc8349-pci";