arch/powerpc/boot/dts/mpc832x_mds.dts

   1 /*
   2  * MPC8323E EMDS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 / {
  13         model = "MPC8323EMDS";
  14         compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         aliases {
  19                 ethernet0 = &enet0;
  20                 ethernet1 = &enet1;
  21                 serial0 = &serial0;
  22                 serial1 = &serial1;
  23                 pci0 = &pci0;
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 PowerPC,8323@0 {
  31                         device_type = "cpu";
  32                         reg = <0>;
  33                         d-cache-line-size = <20>;       // 32 bytes
  34                         i-cache-line-size = <20>;       // 32 bytes
  35                         d-cache-size = <4000>;          // L1, 16K
  36                         i-cache-size = <4000>;          // L1, 16K
  37                         timebase-frequency = <0>;
  38                         bus-frequency = <0>;
  39                         clock-frequency = <0>;
  40                 };
  41         };
  42
  43         memory {
  44                 device_type = "memory";
  45                 reg = <00000000 08000000>;
  46         };
  47
  48         bcsr@f8000000 {
  49                 device_type = "board-control";
  50                 reg = <f8000000 8000>;
  51         };
  52
  53         soc8323@e0000000 {
  54                 #address-cells = <1>;
  55                 #size-cells = <1>;
  56                 device_type = "soc";
  57                 ranges = <0 e0000000 00100000>;
  58                 reg = <e0000000 00000200>;
  59                 bus-frequency = <7DE2900>;
  60
  61                 wdt@200 {
  62                         device_type = "watchdog";
  63                         compatible = "mpc83xx_wdt";
  64                         reg = <200 100>;
  65                 };
  66
  67                 i2c@3000 {
  68                         #address-cells = <1>;
  69                         #size-cells = <0>;
  70                         cell-index = <0>;
  71                         compatible = "fsl-i2c";
  72                         reg = <3000 100>;
  73                         interrupts = <e 8>;
  74                         interrupt-parent = < &ipic >;
  75                         dfsrr;
  76
  77                         rtc@68 {
  78                                 compatible = "dallas,ds1374";
  79                                 reg = <68>;
  80                         };
  81                 };
  82
  83                 serial0: serial@4500 {
  84                         cell-index = <0>;
  85                         device_type = "serial";
  86                         compatible = "ns16550";
  87                         reg = <4500 100>;
  88                         clock-frequency = <0>;
  89                         interrupts = <9 8>;
  90                         interrupt-parent = < &ipic >;
  91                 };
  92
  93                 serial1: serial@4600 {
  94                         cell-index = <1>;
  95                         device_type = "serial";
  96                         compatible = "ns16550";
  97                         reg = <4600 100>;
  98                         clock-frequency = <0>;
  99                         interrupts = <a 8>;
 100                         interrupt-parent = < &ipic >;
 101                 };
 102
 103                 crypto@30000 {
 104                         device_type = "crypto";
 105                         model = "SEC2";
 106                         compatible = "talitos";
 107                         reg = <30000 7000>;
 108                         interrupts = <b 8>;
 109                         interrupt-parent = < &ipic >;
 110                         /* Rev. 2.2 */
 111                         num-channels = <1>;
 112                         channel-fifo-len = <18>;
 113                         exec-units-mask = <0000004c>;
 114                         descriptor-types-mask = <0122003f>;
 115                 };
 116
 117                 ipic: pic@700 {
 118                         interrupt-controller;
 119                         #address-cells = <0>;
 120                         #interrupt-cells = <2>;
 121                         reg = <700 100>;
 122                         device_type = "ipic";
 123                 };
 124
 125                 par_io@1400 {
 126                         reg = <1400 100>;
 127                         device_type = "par_io";
 128                         num-ports = <7>;
 129
 130                         pio3: ucc_pin@03 {
 131                                 pio-map = <
 132                         /* port  pin  dir  open_drain  assignment  has_irq */
 133                                         3  4  3  0  2  0  /* MDIO */
 134                                         3  5  1  0  2  0  /* MDC */
 135                                         0  d  2  0  1  0        /* RX_CLK (CLK9) */
 136                                         3 18  2  0  1  0        /* TX_CLK (CLK10) */
 137                                         1  0  1  0  1  0        /* TxD0 */
 138                                         1  1  1  0  1  0        /* TxD1 */
 139                                         1  2  1  0  1  0        /* TxD2 */
 140                                         1  3  1  0  1  0        /* TxD3 */
 141                                         1  4  2  0  1  0        /* RxD0 */
 142                                         1  5  2  0  1  0        /* RxD1 */
 143                                         1  6  2  0  1  0        /* RxD2 */
 144                                         1  7  2  0  1  0        /* RxD3 */
 145                                         1  8  2  0  1  0        /* RX_ER */
 146                                         1  9  1  0  1  0        /* TX_ER */
 147                                         1  a  2  0  1  0        /* RX_DV */
 148                                         1  b  2  0  1  0        /* COL */
 149                                         1  c  1  0  1  0        /* TX_EN */
 150                                         1  d  2  0  1  0>;/* CRS */
 151                         };
 152                         pio4: ucc_pin@04 {
 153                                 pio-map = <
 154                         /* port  pin  dir  open_drain  assignment  has_irq */
 155                                         3 1f  2  0  1  0        /* RX_CLK (CLK7) */
 156                                         3  6  2  0  1  0        /* TX_CLK (CLK8) */
 157                                         1 12  1  0  1  0        /* TxD0 */
 158                                         1 13  1  0  1  0        /* TxD1 */
 159                                         1 14  1  0  1  0        /* TxD2 */
 160                                         1 15  1  0  1  0        /* TxD3 */
 161                                         1 16  2  0  1  0        /* RxD0 */
 162                                         1 17  2  0  1  0        /* RxD1 */
 163                                         1 18  2  0  1  0        /* RxD2 */
 164                                         1 19  2  0  1  0        /* RxD3 */
 165                                         1 1a  2  0  1  0        /* RX_ER */
 166                                         1 1b  1  0  1  0        /* TX_ER */
 167                                         1 1c  2  0  1  0        /* RX_DV */
 168                                         1 1d  2  0  1  0        /* COL */
 169                                         1 1e  1  0  1  0        /* TX_EN */
 170                                         1 1f  2  0  1  0>;/* CRS */
 171                         };
 172                 };
 173         };
 174
 175         qe@e0100000 {
 176                 #address-cells = <1>;
 177                 #size-cells = <1>;
 178                 device_type = "qe";
 179                 model = "QE";
 180                 ranges = <0 e0100000 00100000>;
 181                 reg = <e0100000 480>;
 182                 brg-frequency = <0>;
 183                 bus-frequency = <BCD3D80>;
 184
 185                 muram@10000 {
 186                         device_type = "muram";
 187                         ranges = <0 00010000 00004000>;
 188
 189                         data-only@0 {
 190                                 reg = <0 4000>;
 191                         };
 192                 };
 193
 194                 spi@4c0 {
 195                         device_type = "spi";
 196                         compatible = "fsl_spi";
 197                         reg = <4c0 40>;
 198                         interrupts = <2>;
 199                         interrupt-parent = < &qeic >;
 200                         mode = "cpu";
 201                 };
 202
 203                 spi@500 {
 204                         device_type = "spi";
 205                         compatible = "fsl_spi";
 206                         reg = <500 40>;
 207                         interrupts = <1>;
 208                         interrupt-parent = < &qeic >;
 209                         mode = "cpu";
 210                 };
 211
 212                 usb@6c0 {
 213                         device_type = "usb";
 214                         compatible = "qe_udc";
 215                         reg = <6c0 40 8B00 100>;
 216                         interrupts = <b>;
 217                         interrupt-parent = < &qeic >;
 218                         mode = "slave";
 219                 };
 220
 221                 enet0: ucc@2200 {
 222                         device_type = "network";
 223                         compatible = "ucc_geth";
 224                         model = "UCC";
 225                         cell-index = <3>;
 226                         device-id = <3>;
 227                         reg = <2200 200>;
 228                         interrupts = <22>;
 229                         interrupt-parent = < &qeic >;
 230                         local-mac-address = [ 00 00 00 00 00 00 ];
 231                         rx-clock-name = "clk9";
 232                         tx-clock-name = "clk10";
 233                         phy-handle = < &phy3 >;
 234                         pio-handle = < &pio3 >;
 235                 };
 236
 237                 enet1: ucc@3200 {
 238                         device_type = "network";
 239                         compatible = "ucc_geth";
 240                         model = "UCC";
 241                         cell-index = <4>;
 242                         device-id = <4>;
 243                         reg = <3200 200>;
 244                         interrupts = <23>;
 245                         interrupt-parent = < &qeic >;
 246                         local-mac-address = [ 00 00 00 00 00 00 ];
 247                         rx-clock-name = "clk7";
 248                         tx-clock-name = "clk8";
 249                         phy-handle = < &phy4 >;
 250                         pio-handle = < &pio4 >;
 251                 };
 252
 253                 mdio@2320 {
 254                         #address-cells = <1>;
 255                         #size-cells = <0>;
 256                         reg = <2320 18>;
 257                         device_type = "mdio";
 258                         compatible = "ucc_geth_phy";
 259
 260                         phy3: ethernet-phy@03 {
 261                                 interrupt-parent = < &ipic >;
 262                                 interrupts = <11 8>;
 263                                 reg = <3>;
 264                                 device_type = "ethernet-phy";
 265                         };
 266                         phy4: ethernet-phy@04 {
 267                                 interrupt-parent = < &ipic >;
 268                                 interrupts = <12 8>;
 269                                 reg = <4>;
 270                                 device_type = "ethernet-phy";
 271                         };
 272                 };
 273
 274                 qeic: qeic@80 {
 275                         interrupt-controller;
 276                         device_type = "qeic";
 277                         #address-cells = <0>;
 278                         #interrupt-cells = <1>;
 279                         reg = <80 80>;
 280                         big-endian;
 281                         interrupts = <20 8 21 8>; //high:32 low:33
 282                         interrupt-parent = < &ipic >;
 283                 };
 284         };
 285
 286         pci0: pci@e0008500 {
 287                 cell-index = <1>;
 288                 interrupt-map-mask = <f800 0 0 7>;
 289                 interrupt-map = <
 290                                 /* IDSEL 0x11 AD17 */
 291                                  8800 0 0 1 &ipic 14 8
 292                                  8800 0 0 2 &ipic 15 8
 293                                  8800 0 0 3 &ipic 16 8
 294                                  8800 0 0 4 &ipic 17 8
 295
 296                                 /* IDSEL 0x12 AD18 */
 297                                  9000 0 0 1 &ipic 16 8
 298                                  9000 0 0 2 &ipic 17 8
 299                                  9000 0 0 3 &ipic 14 8
 300                                  9000 0 0 4 &ipic 15 8
 301
 302                                 /* IDSEL 0x13 AD19 */
 303                                  9800 0 0 1 &ipic 17 8
 304                                  9800 0 0 2 &ipic 14 8
 305                                  9800 0 0 3 &ipic 15 8
 306                                  9800 0 0 4 &ipic 16 8
 307
 308                                 /* IDSEL 0x15 AD21*/
 309                                  a800 0 0 1 &ipic 14 8
 310                                  a800 0 0 2 &ipic 15 8
 311                                  a800 0 0 3 &ipic 16 8
 312                                  a800 0 0 4 &ipic 17 8
 313
 314                                 /* IDSEL 0x16 AD22*/
 315                                  b000 0 0 1 &ipic 17 8
 316                                  b000 0 0 2 &ipic 14 8
 317                                  b000 0 0 3 &ipic 15 8
 318                                  b000 0 0 4 &ipic 16 8
 319
 320                                 /* IDSEL 0x17 AD23*/
 321                                  b800 0 0 1 &ipic 16 8
 322                                  b800 0 0 2 &ipic 17 8
 323                                  b800 0 0 3 &ipic 14 8
 324                                  b800 0 0 4 &ipic 15 8
 325
 326                                 /* IDSEL 0x18 AD24*/
 327                                  c000 0 0 1 &ipic 15 8
 328                                  c000 0 0 2 &ipic 16 8
 329                                  c000 0 0 3 &ipic 17 8
 330                                  c000 0 0 4 &ipic 14 8>;
 331                 interrupt-parent = < &ipic >;
 332                 interrupts = <42 8>;
 333                 bus-range = <0 0>;
 334                 ranges = <02000000 0 90000000 90000000 0 10000000
 335                           42000000 0 80000000 80000000 0 10000000
 336                           01000000 0 00000000 d0000000 0 00100000>;
 337                 clock-frequency = <0>;
 338                 #interrupt-cells = <1>;
 339                 #size-cells = <2>;
 340                 #address-cells = <3>;
 341                 reg = <e0008500 100>;
 342                 compatible = "fsl,mpc8349-pci";
 343                 device_type = "pci";
 344         };
 345 };