arch/powerpc/boot/dts/mpc8313erdb.dts

   1 /*
   2  * MPC8313E RDB Device Tree Source
   3  *
   4  * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 / {
  13         model = "MPC8313ERDB";
  14         compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB";
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         aliases {
  19                 ethernet0 = &enet0;
  20                 ethernet1 = &enet1;
  21                 serial0 = &serial0;
  22                 serial1 = &serial1;
  23                 pci0 = &pci0;
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 PowerPC,8313@0 {
  31                         device_type = "cpu";
  32                         reg = <0>;
  33                         d-cache-line-size = <20>;       // 32 bytes
  34                         i-cache-line-size = <20>;       // 32 bytes
  35                         d-cache-size = <4000>;          // L1, 16K
  36                         i-cache-size = <4000>;          // L1, 16K
  37                         timebase-frequency = <0>;       // from bootloader
  38                         bus-frequency = <0>;            // from bootloader
  39                         clock-frequency = <0>;          // from bootloader
  40                 };
  41         };
  42
  43         memory {
  44                 device_type = "memory";
  45                 reg = <00000000 08000000>;      // 128MB at 0
  46         };
  47
  48         localbus@e0005000 {
  49                 #address-cells = <2>;
  50                 #size-cells = <1>;
  51                 compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
  52                 reg = <e0005000 1000>;
  53                 interrupts = <d#77 8>;
  54                 interrupt-parent = <&ipic>;
  55
  56                 // CS0 and CS1 are swapped when
  57                 // booting from nand, but the
  58                 // addresses are the same.
  59                 ranges = <0 0 fe000000 00800000
  60                           1 0 e2800000 00008000
  61                           2 0 f0000000 00020000
  62                           3 0 fa000000 00008000>;
  63
  64                 flash@0,0 {
  65                         #address-cells = <1>;
  66                         #size-cells = <1>;
  67                         compatible = "cfi-flash";
  68                         reg = <0 0 800000>;
  69                         bank-width = <2>;
  70                         device-width = <1>;
  71                 };
  72
  73                 nand@1,0 {
  74                         #address-cells = <1>;
  75                         #size-cells = <1>;
  76                         compatible = "fsl,mpc8313-fcm-nand",
  77                                      "fsl,elbc-fcm-nand";
  78                         reg = <1 0 2000>;
  79
  80                         u-boot@0 {
  81                                 reg = <0 100000>;
  82                                 read-only;
  83                         };
  84
  85                         kernel@100000 {
  86                                 reg = <100000 300000>;
  87                         };
  88
  89                         fs@400000 {
  90                                 reg = <400000 1c00000>;
  91                         };
  92                 };
  93         };
  94
  95         soc8313@e0000000 {
  96                 #address-cells = <1>;
  97                 #size-cells = <1>;
  98                 device_type = "soc";
  99                 compatible = "simple-bus";
 100                 ranges = <0 e0000000 00100000>;
 101                 reg = <e0000000 00000200>;
 102                 bus-frequency = <0>;
 103
 104                 wdt@200 {
 105                         device_type = "watchdog";
 106                         compatible = "mpc83xx_wdt";
 107                         reg = <200 100>;
 108                 };
 109
 110                 i2c@3000 {
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113                         cell-index = <0>;
 114                         compatible = "fsl-i2c";
 115                         reg = <3000 100>;
 116                         interrupts = <e 8>;
 117                         interrupt-parent = < &ipic >;
 118                         dfsrr;
 119                 };
 120
 121                 i2c@3100 {
 122                         #address-cells = <1>;
 123                         #size-cells = <0>;
 124                         cell-index = <1>;
 125                         compatible = "fsl-i2c";
 126                         reg = <3100 100>;
 127                         interrupts = <f 8>;
 128                         interrupt-parent = < &ipic >;
 129                         dfsrr;
 130                 };
 131
 132                 spi@7000 {
 133                         cell-index = <0>;
 134                         compatible = "fsl,spi";
 135                         reg = <7000 1000>;
 136                         interrupts = <10 8>;
 137                         interrupt-parent = < &ipic >;
 138                         mode = "cpu";
 139                 };
 140
 141                 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
 142                 usb@23000 {
 143                         compatible = "fsl-usb2-dr";
 144                         reg = <23000 1000>;
 145                         #address-cells = <1>;
 146                         #size-cells = <0>;
 147                         interrupt-parent = < &ipic >;
 148                         interrupts = <26 8>;
 149                         phy_type = "utmi_wide";
 150                 };
 151
 152                 mdio@24520 {
 153                         #address-cells = <1>;
 154                         #size-cells = <0>;
 155                         compatible = "fsl,gianfar-mdio";
 156                         reg = <24520 20>;
 157                         phy1: ethernet-phy@1 {
 158                                 interrupt-parent = < &ipic >;
 159                                 interrupts = <13 8>;
 160                                 reg = <1>;
 161                                 device_type = "ethernet-phy";
 162                         };
 163                         phy4: ethernet-phy@4 {
 164                                 interrupt-parent = < &ipic >;
 165                                 interrupts = <14 8>;
 166                                 reg = <4>;
 167                                 device_type = "ethernet-phy";
 168                         };
 169                 };
 170
 171                 enet0: ethernet@24000 {
 172                         cell-index = <0>;
 173                         device_type = "network";
 174                         model = "eTSEC";
 175                         compatible = "gianfar";
 176                         reg = <24000 1000>;
 177                         local-mac-address = [ 00 00 00 00 00 00 ];
 178                         interrupts = <25 8 24 8 23 8>;
 179                         interrupt-parent = < &ipic >;
 180                         phy-handle = < &phy1 >;
 181                 };
 182
 183                 enet1: ethernet@25000 {
 184                         cell-index = <1>;
 185                         device_type = "network";
 186                         model = "eTSEC";
 187                         compatible = "gianfar";
 188                         reg = <25000 1000>;
 189                         local-mac-address = [ 00 00 00 00 00 00 ];
 190                         interrupts = <22 8 21 8 20 8>;
 191                         interrupt-parent = < &ipic >;
 192                         phy-handle = < &phy4 >;
 193                 };
 194
 195                 serial0: serial@4500 {
 196                         cell-index = <0>;
 197                         device_type = "serial";
 198                         compatible = "ns16550";
 199                         reg = <4500 100>;
 200                         clock-frequency = <0>;
 201                         interrupts = <9 8>;
 202                         interrupt-parent = < &ipic >;
 203                 };
 204
 205                 serial1: serial@4600 {
 206                         cell-index = <1>;
 207                         device_type = "serial";
 208                         compatible = "ns16550";
 209                         reg = <4600 100>;
 210                         clock-frequency = <0>;
 211                         interrupts = <a 8>;
 212                         interrupt-parent = < &ipic >;
 213                 };
 214
 215                 crypto@30000 {
 216                         device_type = "crypto";
 217                         model = "SEC2";
 218                         compatible = "talitos";
 219                         reg = <30000 7000>;
 220                         interrupts = <b 8>;
 221                         interrupt-parent = < &ipic >;
 222                         /* Rev. 2.2 */
 223                         num-channels = <1>;
 224                         channel-fifo-len = <18>;
 225                         exec-units-mask = <0000004c>;
 226                         descriptor-types-mask = <0122003f>;
 227                 };
 228
 229                 /* IPIC
 230                  * interrupts cell = <intr #, sense>
 231                  * sense values match linux IORESOURCE_IRQ_* defines:
 232                  * sense == 8: Level, low assertion
 233                  * sense == 2: Edge, high-to-low change
 234                  */
 235                 ipic: pic@700 {
 236                         interrupt-controller;
 237                         #address-cells = <0>;
 238                         #interrupt-cells = <2>;
 239                         reg = <700 100>;
 240                         device_type = "ipic";
 241                 };
 242         };
 243
 244         pci0: pci@e0008500 {
 245                 cell-index = <1>;
 246                 interrupt-map-mask = <f800 0 0 7>;
 247                 interrupt-map = <
 248
 249                                 /* IDSEL 0x0E -mini PCI */
 250                                  7000 0 0 1 &ipic 12 8
 251                                  7000 0 0 2 &ipic 12 8
 252                                  7000 0 0 3 &ipic 12 8
 253                                  7000 0 0 4 &ipic 12 8
 254
 255                                 /* IDSEL 0x0F - PCI slot */
 256                                  7800 0 0 1 &ipic 11 8
 257                                  7800 0 0 2 &ipic 12 8
 258                                  7800 0 0 3 &ipic 11 8
 259                                  7800 0 0 4 &ipic 12 8>;
 260                 interrupt-parent = < &ipic >;
 261                 interrupts = <42 8>;
 262                 bus-range = <0 0>;
 263                 ranges = <02000000 0 90000000 90000000 0 10000000
 264                           42000000 0 80000000 80000000 0 10000000
 265                           01000000 0 00000000 e2000000 0 00100000>;
 266                 clock-frequency = <3f940aa>;
 267                 #interrupt-cells = <1>;
 268                 #size-cells = <2>;
 269                 #address-cells = <3>;
 270                 reg = <e0008500 100>;
 271                 compatible = "fsl,mpc8349-pci";
 272                 device_type = "pci";
 273         };
 274 };