2 * Code to handle x86 style IRQs plus some generic interrupt stuff.
4 * Copyright (C) 1992 Linus Torvalds
5 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
6 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
7 * Copyright (C) 1999-2000 Grant Grundler
8 * Copyright (c) 2005 Matthew Wilcox
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2, or (at your option)
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/bitops.h>
25 #include <linux/errno.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/kernel_stat.h>
29 #include <linux/seq_file.h>
30 #include <linux/spinlock.h>
31 #include <linux/types.h>
36 #undef PARISC_IRQ_CR16_COUNTS
38 extern irqreturn_t timer_interrupt(int, void *);
39 extern irqreturn_t ipi_interrupt(int, void *);
41 #define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq))
43 /* Bits in EIEM correlate with cpu_irq_action[].
44 ** Numbered *Big Endian*! (ie bit 0 is MSB)
46 static volatile unsigned long cpu_eiem = 0;
49 ** local ACK bitmap ... habitually set to 1, but reset to zero
50 ** between ->ack() and ->end() of the interrupt to prevent
51 ** re-interruption of a processing interrupt.
53 static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL;
55 static void cpu_mask_irq(struct irq_data *d)
57 unsigned long eirr_bit = EIEM_MASK(d->irq);
59 cpu_eiem &= ~eirr_bit;
60 /* Do nothing on the other CPUs. If they get this interrupt,
61 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
62 * handle it, and the set_eiem() at the bottom will ensure it
63 * then gets disabled */
66 static void __cpu_unmask_irq(unsigned int irq)
68 unsigned long eirr_bit = EIEM_MASK(irq);
72 /* This is just a simple NOP IPI. But what it does is cause
73 * all the other CPUs to do a set_eiem(cpu_eiem) at the end
74 * of the interrupt handler */
78 static void cpu_unmask_irq(struct irq_data *d)
80 __cpu_unmask_irq(d->irq);
83 void cpu_ack_irq(struct irq_data *d)
85 unsigned long mask = EIEM_MASK(d->irq);
86 int cpu = smp_processor_id();
88 /* Clear in EIEM so we can no longer process */
89 per_cpu(local_ack_eiem, cpu) &= ~mask;
91 /* disable the interrupt */
92 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
98 void cpu_eoi_irq(struct irq_data *d)
100 unsigned long mask = EIEM_MASK(d->irq);
101 int cpu = smp_processor_id();
103 /* set it in the eiems---it's no longer in process */
104 per_cpu(local_ack_eiem, cpu) |= mask;
106 /* enable the interrupt */
107 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
111 int cpu_check_affinity(struct irq_data *d, const struct cpumask *dest)
115 /* timer and ipi have to always be received on all CPUs */
116 if (irqd_is_per_cpu(d))
119 /* whatever mask they set, we just allow one CPU */
120 cpu_dest = first_cpu(*dest);
125 static int cpu_set_affinity_irq(struct irq_data *d, const struct cpumask *dest,
130 cpu_dest = cpu_check_affinity(d, dest);
134 cpumask_copy(d->affinity, dest);
140 static struct irq_chip cpu_interrupt_type = {
142 .irq_mask = cpu_mask_irq,
143 .irq_unmask = cpu_unmask_irq,
144 .irq_ack = cpu_ack_irq,
145 .irq_eoi = cpu_eoi_irq,
147 .irq_set_affinity = cpu_set_affinity_irq,
149 /* XXX: Needs to be written. We managed without it so far, but
150 * we really ought to write it.
152 .irq_retrigger = NULL,
155 int show_interrupts(struct seq_file *p, void *v)
157 int i = *(loff_t *) v, j;
162 for_each_online_cpu(j)
163 seq_printf(p, " CPU%d", j);
165 #ifdef PARISC_IRQ_CR16_COUNTS
166 seq_printf(p, " [min/avg/max] (CPU cycle counts)");
172 struct irqaction *action;
174 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
175 action = irq_desc[i].action;
178 seq_printf(p, "%3d: ", i);
180 for_each_online_cpu(j)
181 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
183 seq_printf(p, "%10u ", kstat_irqs(i));
186 seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name);
187 #ifndef PARISC_IRQ_CR16_COUNTS
188 seq_printf(p, " %s", action->name);
190 while ((action = action->next))
191 seq_printf(p, ", %s", action->name);
193 for ( ;action; action = action->next) {
194 unsigned int k, avg, min, max;
196 min = max = action->cr16_hist[0];
198 for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
199 int hist = action->cr16_hist[k];
206 if (hist > max) max = hist;
207 if (hist < min) min = hist;
211 seq_printf(p, " %s[%d/%d/%d]", action->name,
218 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
227 ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
228 ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
230 ** To use txn_XXX() interfaces, get a Virtual IRQ first.
231 ** Then use that to get the Transaction address and data.
234 int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data)
236 if (irq_desc[irq].action)
238 if (get_irq_chip(irq) != &cpu_interrupt_type)
241 /* for iosapic interrupts */
243 set_irq_chip_and_handler(irq, type, handle_percpu_irq);
244 set_irq_chip_data(irq, data);
245 __cpu_unmask_irq(irq);
250 int txn_claim_irq(int irq)
252 return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
256 * The bits_wide parameter accommodates the limitations of the HW/SW which
258 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
259 * V-class (EPIC): 6 bits
260 * N/L/A-class (iosapic): 8 bits
261 * PCI 2.2 MSI: 16 bits
262 * Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric)
264 * On the service provider side:
265 * o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register)
266 * o PA 2.0 wide mode 6-bits (per processor)
267 * o IA64 8-bits (0-256 total)
269 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
270 * by the processor...and the N/L-class I/O subsystem supports more bits than
271 * PA2.0 has. The first case is the problem.
273 int txn_alloc_irq(unsigned int bits_wide)
277 /* never return irq 0 cause that's the interval timer */
278 for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
279 if (cpu_claim_irq(irq, NULL, NULL) < 0)
281 if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
286 /* unlikely, but be prepared */
291 unsigned long txn_affinity_addr(unsigned int irq, int cpu)
294 struct irq_data *d = irq_get_irq_data(irq);
295 cpumask_copy(d->affinity, cpumask_of(cpu));
298 return per_cpu(cpu_data, cpu).txn_addr;
302 unsigned long txn_alloc_addr(unsigned int virt_irq)
304 static int next_cpu = -1;
306 next_cpu++; /* assign to "next" CPU we want this bugger on */
309 while ((next_cpu < nr_cpu_ids) &&
310 (!per_cpu(cpu_data, next_cpu).txn_addr ||
311 !cpu_online(next_cpu)))
314 if (next_cpu >= nr_cpu_ids)
315 next_cpu = 0; /* nothing else, assign monarch */
317 return txn_affinity_addr(virt_irq, next_cpu);
321 unsigned int txn_alloc_data(unsigned int virt_irq)
323 return virt_irq - CPU_IRQ_BASE;
326 static inline int eirr_to_irq(unsigned long eirr)
328 int bit = fls_long(eirr);
329 return (BITS_PER_LONG - bit) + TIMER_IRQ;
332 /* ONLY called from entry.S:intr_extint() */
333 void do_cpu_irq_mask(struct pt_regs *regs)
335 struct pt_regs *old_regs;
336 unsigned long eirr_val;
337 int irq, cpu = smp_processor_id();
339 struct irq_desc *desc;
343 old_regs = set_irq_regs(regs);
347 eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu);
350 irq = eirr_to_irq(eirr_val);
353 desc = irq_to_desc(irq);
354 cpumask_copy(&dest, desc->irq_data.affinity);
355 if (irqd_is_per_cpu(&desc->irq_data) &&
356 !cpu_isset(smp_processor_id(), dest)) {
357 int cpu = first_cpu(dest);
359 printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
360 irq, smp_processor_id(), cpu);
361 gsc_writel(irq + CPU_IRQ_BASE,
362 per_cpu(cpu_data, cpu).hpa);
366 generic_handle_irq(irq);
370 set_irq_regs(old_regs);
374 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
378 static struct irqaction timer_action = {
379 .handler = timer_interrupt,
381 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL,
385 static struct irqaction ipi_action = {
386 .handler = ipi_interrupt,
388 .flags = IRQF_DISABLED | IRQF_PERCPU,
392 static void claim_cpu_irqs(void)
395 for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
396 set_irq_chip_and_handler(i, &cpu_interrupt_type,
400 set_irq_handler(TIMER_IRQ, handle_percpu_irq);
401 setup_irq(TIMER_IRQ, &timer_action);
403 set_irq_handler(IPI_IRQ, handle_percpu_irq);
404 setup_irq(IPI_IRQ, &ipi_action);
408 void __init init_IRQ(void)
410 local_irq_disable(); /* PARANOID - should already be disabled */
411 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */
415 cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
417 cpu_eiem = EIEM_MASK(TIMER_IRQ);
419 set_eiem(cpu_eiem); /* EIEM : enable all external intr */