1 #ifndef _PARISC_PGTABLE_H
2 #define _PARISC_PGTABLE_H
4 #include <asm-generic/4level-fixup.h>
6 #include <asm/fixmap.h>
10 * we simulate an x86-style page table for the linux mm code
13 #include <linux/bitops.h>
14 #include <linux/spinlock.h>
15 #include <linux/mm_types.h>
16 #include <asm/processor.h>
17 #include <asm/cache.h>
20 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
21 * memory. For the return value to be meaningful, ADDR must be >=
22 * PAGE_OFFSET. This operation can be relatively expensive (e.g.,
23 * require a hash-, or multi-level tree-lookup or something of that
24 * sort) but it guarantees to return TRUE only if accessing the page
25 * at that address does not cause an error. Note that there may be
26 * addresses for which kern_addr_valid() returns FALSE even though an
27 * access would not cause an error (e.g., this is typically true for
28 * memory mapped I/O regions.
30 * XXX Need to implement this for parisc.
32 #define kern_addr_valid(addr) (1)
34 /* Certain architectures need to do special things when PTEs
35 * within a page table are directly modified. Thus, the following
36 * hook is made available.
38 #define set_pte(pteptr, pteval) \
40 *(pteptr) = (pteval); \
43 extern void purge_tlb_entries(struct mm_struct *, unsigned long);
45 #define set_pte_at(mm, addr, ptep, pteval) \
47 set_pte(ptep, pteval); \
48 purge_tlb_entries(mm, addr); \
51 #endif /* !__ASSEMBLY__ */
53 #define pte_ERROR(e) \
54 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
55 #define pmd_ERROR(e) \
56 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e))
57 #define pgd_ERROR(e) \
58 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e))
60 /* This is the size of the initially mapped kernel memory */
61 #define KERNEL_INITIAL_ORDER 24 /* 0 to 1<<24 = 16MB */
62 #define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER)
64 #if defined(CONFIG_64BIT) && defined(CONFIG_PARISC_PAGE_SIZE_4KB)
66 #define PGD_ORDER 1 /* Number of pages per pgd */
67 #define PMD_ORDER 1 /* Number of pages per pmd */
68 #define PGD_ALLOC_ORDER 2 /* first pgd contains pmd */
71 #define PGD_ORDER 1 /* Number of pages per pgd */
72 #define PGD_ALLOC_ORDER PGD_ORDER
75 /* Definitions for 3rd level (we use PLD here for Page Lower directory
76 * because PTE_SHIFT is used lower down to mean shift that has to be
77 * done to get usable bits out of the PTE) */
78 #define PLD_SHIFT PAGE_SHIFT
79 #define PLD_SIZE PAGE_SIZE
80 #define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY)
81 #define PTRS_PER_PTE (1UL << BITS_PER_PTE)
83 /* Definitions for 2nd level */
84 #define pgtable_cache_init() do { } while (0)
86 #define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE)
87 #define PMD_SIZE (1UL << PMD_SHIFT)
88 #define PMD_MASK (~(PMD_SIZE-1))
90 #define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY)
92 #define BITS_PER_PMD 0
94 #define PTRS_PER_PMD (1UL << BITS_PER_PMD)
96 /* Definitions for 1st level */
97 #define PGDIR_SHIFT (PMD_SHIFT + BITS_PER_PMD)
98 #if (PGDIR_SHIFT + PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) > BITS_PER_LONG
99 #define BITS_PER_PGD (BITS_PER_LONG - PGDIR_SHIFT)
101 #define BITS_PER_PGD (PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY)
103 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
104 #define PGDIR_MASK (~(PGDIR_SIZE-1))
105 #define PTRS_PER_PGD (1UL << BITS_PER_PGD)
106 #define USER_PTRS_PER_PGD PTRS_PER_PGD
109 #define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD)
110 #define MAX_ADDRESS (1UL << MAX_ADDRBITS)
111 #define SPACEID_SHIFT (MAX_ADDRBITS - 32)
113 #define MAX_ADDRBITS (BITS_PER_LONG)
114 #define MAX_ADDRESS (1UL << MAX_ADDRBITS)
115 #define SPACEID_SHIFT 0
118 /* This calculates the number of initial pages we need for the initial
120 #if (KERNEL_INITIAL_ORDER) >= (PMD_SHIFT)
121 # define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT))
123 # define PT_INITIAL (1) /* all initial PTEs fit into one page */
127 * pgd entries used up by user/kernel:
130 #define FIRST_USER_ADDRESS 0
132 /* NB: The tlb miss handlers make certain assumptions about the order */
133 /* of the following bits, so be careful (One example, bits 25-31 */
134 /* are moved together in one instruction). */
136 #define _PAGE_READ_BIT 31 /* (0x001) read access allowed */
137 #define _PAGE_WRITE_BIT 30 /* (0x002) write access allowed */
138 #define _PAGE_EXEC_BIT 29 /* (0x004) execute access allowed */
139 #define _PAGE_GATEWAY_BIT 28 /* (0x008) privilege promotion allowed */
140 #define _PAGE_DMB_BIT 27 /* (0x010) Data Memory Break enable (B bit) */
141 #define _PAGE_DIRTY_BIT 26 /* (0x020) Page Dirty (D bit) */
142 #define _PAGE_FILE_BIT _PAGE_DIRTY_BIT /* overload this bit */
143 #define _PAGE_REFTRAP_BIT 25 /* (0x040) Page Ref. Trap enable (T bit) */
144 #define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */
145 #define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */
146 #define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */
147 /* bit 21 was formerly the FLUSH bit but is now unused */
148 #define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */
150 /* N.B. The bits are defined in terms of a 32 bit word above, so the */
151 /* following macro is ok for both 32 and 64 bit. */
153 #define xlate_pabit(x) (31 - x)
155 /* this defines the shift to the usable bits in the PTE it is set so
156 * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set
158 #define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT)
160 /* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */
161 #define PFN_PTE_SHIFT 12
164 /* this is how many bits may be used by the file functions */
165 #define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_SHIFT)
167 #define pte_to_pgoff(pte) (pte_val(pte) >> PTE_SHIFT)
168 #define pgoff_to_pte(off) ((pte_t) { ((off) << PTE_SHIFT) | _PAGE_FILE })
170 #define _PAGE_READ (1 << xlate_pabit(_PAGE_READ_BIT))
171 #define _PAGE_WRITE (1 << xlate_pabit(_PAGE_WRITE_BIT))
172 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
173 #define _PAGE_EXEC (1 << xlate_pabit(_PAGE_EXEC_BIT))
174 #define _PAGE_GATEWAY (1 << xlate_pabit(_PAGE_GATEWAY_BIT))
175 #define _PAGE_DMB (1 << xlate_pabit(_PAGE_DMB_BIT))
176 #define _PAGE_DIRTY (1 << xlate_pabit(_PAGE_DIRTY_BIT))
177 #define _PAGE_REFTRAP (1 << xlate_pabit(_PAGE_REFTRAP_BIT))
178 #define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT))
179 #define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT))
180 #define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT))
181 #define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT))
182 #define _PAGE_FILE (1 << xlate_pabit(_PAGE_FILE_BIT))
184 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED)
185 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
186 #define _PAGE_KERNEL_RO (_PAGE_PRESENT | _PAGE_READ | _PAGE_DIRTY | _PAGE_ACCESSED)
187 #define _PAGE_KERNEL_EXEC (_PAGE_KERNEL_RO | _PAGE_EXEC)
188 #define _PAGE_KERNEL_RWX (_PAGE_KERNEL_EXEC | _PAGE_WRITE)
189 #define _PAGE_KERNEL (_PAGE_KERNEL_RO | _PAGE_WRITE)
191 /* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds
192 * are page-aligned, we don't care about the PAGE_OFFSET bits, except
193 * for a few meta-information bits, so we shift the address to be
194 * able to effectively address 40/42/44-bits of physical address space
195 * depending on 4k/16k/64k PAGE_SIZE */
196 #define _PxD_PRESENT_BIT 31
197 #define _PxD_ATTACHED_BIT 30
198 #define _PxD_VALID_BIT 29
200 #define PxD_FLAG_PRESENT (1 << xlate_pabit(_PxD_PRESENT_BIT))
201 #define PxD_FLAG_ATTACHED (1 << xlate_pabit(_PxD_ATTACHED_BIT))
202 #define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT))
203 #define PxD_FLAG_MASK (0xf)
204 #define PxD_FLAG_SHIFT (4)
205 #define PxD_VALUE_SHIFT (8) /* (PAGE_SHIFT-PxD_FLAG_SHIFT) */
209 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
210 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_ACCESSED)
211 /* Others seem to make this executable, I don't know if that's correct
212 or not. The stack is mapped this way though so this is necessary
213 in the short term - dhd@linuxcare.com, 2000-08-08 */
214 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_ACCESSED)
215 #define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE | _PAGE_ACCESSED)
216 #define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC |_PAGE_ACCESSED)
217 #define PAGE_COPY PAGE_EXECREAD
218 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC |_PAGE_ACCESSED)
219 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
220 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC)
221 #define PAGE_KERNEL_RWX __pgprot(_PAGE_KERNEL_RWX)
222 #define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO)
223 #define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
224 #define PAGE_GATEWAY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_GATEWAY| _PAGE_READ)
228 * We could have an execute only page using "gateway - promote to priv
229 * level 3", but that is kind of silly. So, the way things are defined
230 * now, we must always have read permission for pages with execute
231 * permission. For the fun of it we'll go ahead and support write only
236 #define __P000 PAGE_NONE
237 #define __P001 PAGE_READONLY
238 #define __P010 __P000 /* copy on write */
239 #define __P011 __P001 /* copy on write */
240 #define __P100 PAGE_EXECREAD
241 #define __P101 PAGE_EXECREAD
242 #define __P110 __P100 /* copy on write */
243 #define __P111 __P101 /* copy on write */
245 #define __S000 PAGE_NONE
246 #define __S001 PAGE_READONLY
247 #define __S010 PAGE_WRITEONLY
248 #define __S011 PAGE_SHARED
249 #define __S100 PAGE_EXECREAD
250 #define __S101 PAGE_EXECREAD
251 #define __S110 PAGE_RWX
252 #define __S111 PAGE_RWX
255 extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */
257 /* initial page tables for 0-8MB for kernel */
261 /* zero page used for uninitialized stuff */
263 extern unsigned long *empty_zero_page;
266 * ZERO_PAGE is a global shared page that is always zero: used
267 * for zero-mapped memory areas etc..
270 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
272 #define pte_none(x) (pte_val(x) == 0)
273 #define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
274 #define pte_clear(mm,addr,xp) do { pte_val(*(xp)) = 0; } while (0)
276 #define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK)
277 #define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
278 #define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK)
279 #define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
282 /* The first entry of the permanent pmd is not there if it contains
283 * the gateway marker */
284 #define pmd_none(x) (!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED)
286 #define pmd_none(x) (!pmd_val(x))
288 #define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID))
289 #define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT)
290 static inline void pmd_clear(pmd_t *pmd) {
292 if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED)
293 /* This is the entry pointing to the permanent pmd
294 * attached to the pgd; cannot clear it */
295 __pmd_val_set(*pmd, PxD_FLAG_ATTACHED);
298 __pmd_val_set(*pmd, 0);
304 #define pgd_page_vaddr(pgd) ((unsigned long) __va(pgd_address(pgd)))
305 #define pgd_page(pgd) virt_to_page((void *)pgd_page_vaddr(pgd))
307 /* For 64 bit we have three level tables */
309 #define pgd_none(x) (!pgd_val(x))
310 #define pgd_bad(x) (!(pgd_flag(x) & PxD_FLAG_VALID))
311 #define pgd_present(x) (pgd_flag(x) & PxD_FLAG_PRESENT)
312 static inline void pgd_clear(pgd_t *pgd) {
314 if(pgd_flag(*pgd) & PxD_FLAG_ATTACHED)
315 /* This is the permanent pmd attached to the pgd; cannot
319 __pgd_val_set(*pgd, 0);
323 * The "pgd_xxx()" functions here are trivial for a folded two-level
324 * setup: the pgd is never bad, and a pmd always exists (as it's folded
325 * into the pgd entry)
327 static inline int pgd_none(pgd_t pgd) { return 0; }
328 static inline int pgd_bad(pgd_t pgd) { return 0; }
329 static inline int pgd_present(pgd_t pgd) { return 1; }
330 static inline void pgd_clear(pgd_t * pgdp) { }
334 * The following only work if pte_present() is true.
335 * Undefined behaviour if not..
337 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
338 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
339 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
340 static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
341 static inline int pte_special(pte_t pte) { return 0; }
343 static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
344 static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
345 static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; }
346 static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
347 static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
348 static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; }
349 static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
352 * Conversion functions: convert a page and protection to a page entry,
353 * and a page entry and page directory to the page they refer to.
355 #define __mk_pte(addr,pgprot) \
359 pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot)); \
364 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
366 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
369 pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot);
373 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
374 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
376 /* Permanent address of a page. On parisc we don't have highmem. */
378 #define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT)
380 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
382 #define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_address(pmd)))
384 #define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd)))
385 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
387 #define pgd_index(address) ((address) >> PGDIR_SHIFT)
389 /* to find an entry in a page-table-directory */
390 #define pgd_offset(mm, address) \
391 ((mm)->pgd + ((address) >> PGDIR_SHIFT))
393 /* to find an entry in a kernel page-table-directory */
394 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
396 /* Find an entry in the second-level page table.. */
399 #define pmd_offset(dir,address) \
400 ((pmd_t *) pgd_page_vaddr(*(dir)) + (((address)>>PMD_SHIFT) & (PTRS_PER_PMD-1)))
402 #define pmd_offset(dir,addr) ((pmd_t *) dir)
405 /* Find an entry in the third-level page table.. */
406 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
407 #define pte_offset_kernel(pmd, address) \
408 ((pte_t *) pmd_page_vaddr(*(pmd)) + pte_index(address))
409 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
410 #define pte_unmap(pte) do { } while (0)
412 #define pte_unmap(pte) do { } while (0)
413 #define pte_unmap_nested(pte) do { } while (0)
415 extern void paging_init (void);
417 /* Used for deferring calls to flush_dcache_page() */
419 #define PG_dcache_dirty PG_arch_1
421 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
423 /* Encode and de-code a swap entry */
425 #define __swp_type(x) ((x).val & 0x1f)
426 #define __swp_offset(x) ( (((x).val >> 6) & 0x7) | \
427 (((x).val >> 8) & ~0x7) )
428 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | \
429 ((offset & 0x7) << 6) | \
430 ((offset & ~0x7) << 8) })
431 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
432 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
434 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
437 if (!pte_young(*ptep))
439 return test_and_clear_bit(xlate_pabit(_PAGE_ACCESSED_BIT), &pte_val(*ptep));
444 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
449 extern spinlock_t pa_dbit_lock;
452 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
456 spin_lock(&pa_dbit_lock);
458 pte_clear(mm,addr,ptep);
459 spin_unlock(&pa_dbit_lock);
464 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
467 unsigned long new, old;
470 old = pte_val(*ptep);
471 new = pte_val(pte_wrprotect(__pte (old)));
472 } while (cmpxchg((unsigned long *) ptep, old, new) != old);
473 purge_tlb_entries(mm, addr);
475 pte_t old_pte = *ptep;
476 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
480 #define pte_same(A,B) (pte_val(A) == pte_val(B))
482 #endif /* !__ASSEMBLY__ */
485 /* TLB page size encoding - see table 3-1 in parisc20.pdf */
486 #define _PAGE_SIZE_ENCODING_4K 0
487 #define _PAGE_SIZE_ENCODING_16K 1
488 #define _PAGE_SIZE_ENCODING_64K 2
489 #define _PAGE_SIZE_ENCODING_256K 3
490 #define _PAGE_SIZE_ENCODING_1M 4
491 #define _PAGE_SIZE_ENCODING_4M 5
492 #define _PAGE_SIZE_ENCODING_16M 6
493 #define _PAGE_SIZE_ENCODING_64M 7
495 #if defined(CONFIG_PARISC_PAGE_SIZE_4KB)
496 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K
497 #elif defined(CONFIG_PARISC_PAGE_SIZE_16KB)
498 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K
499 #elif defined(CONFIG_PARISC_PAGE_SIZE_64KB)
500 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K
504 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
505 remap_pfn_range(vma, vaddr, pfn, size, prot)
507 #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)
509 /* We provide our own get_unmapped_area to provide cache coherency */
511 #define HAVE_ARCH_UNMAPPED_AREA
513 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
514 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
515 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
516 #define __HAVE_ARCH_PTE_SAME
517 #include <asm-generic/pgtable.h>
519 #endif /* _PARISC_PGTABLE_H */