2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 * Copyright (C) 2000-2001 Toshiba Corporation
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 #include <linux/init.h>
33 #include <linux/sched.h>
34 #include <linux/types.h>
35 #include <linux/interrupt.h>
38 #include <asm/mipsregs.h>
39 #include <asm/system.h>
41 #include <asm/processor.h>
42 #include <asm/txx9/generic.h>
43 #include <asm/txx9/jmr3927.h>
45 #if JMR3927_IRQ_END > NR_IRQS
46 #error JMR3927_IRQ_END > NR_IRQS
50 * CP0_STATUS is a thread's resource (saved/restored on context switch).
51 * So disable_irq/enable_irq MUST handle IOC/IRC registers.
53 static void mask_irq_ioc(unsigned int irq)
56 unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
57 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
58 unsigned int bit = 1 << irq_nr;
59 jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
60 /* flush write buffer */
61 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
63 static void unmask_irq_ioc(unsigned int irq)
66 unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
67 unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
68 unsigned int bit = 1 << irq_nr;
69 jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
70 /* flush write buffer */
71 (void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
74 static int jmr3927_ioc_irqroute(void)
76 unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
79 for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
81 return JMR3927_IRQ_IOC + i;
86 static int jmr3927_irq_dispatch(int pending)
90 if ((pending & CAUSEF_IP7) == 0)
92 irq = (pending >> CAUSEB_IP2) & 0x0f;
93 irq += JMR3927_IRQ_IRC;
94 if (irq == JMR3927_IRQ_IOCINT)
95 irq = jmr3927_ioc_irqroute();
99 static struct irq_chip jmr3927_irq_ioc = {
100 .name = "jmr3927_ioc",
102 .mask = mask_irq_ioc,
103 .mask_ack = mask_irq_ioc,
104 .unmask = unmask_irq_ioc,
107 void __init jmr3927_irq_setup(void)
111 txx9_irq_dispatch = jmr3927_irq_dispatch;
112 /* Now, interrupt control disabled, */
113 /* all IRC interrupts are masked, */
114 /* all IRC interrupt mode are Low Active. */
116 /* mask all IOC interrupts */
117 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
118 /* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
119 jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
121 /* clear PCI Soft interrupts */
122 jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
123 /* clear PCI Reset interrupts */
124 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
127 for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
128 set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
130 /* setup IOC interrupt 1 (PCI, MODEM) */
131 set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);