2 * TX4938/4937 setup routines
3 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
4 * and RBTX49xx patch from CELF patch archive.
6 * 2003-2005 (c) MontaVista Software, Inc.
7 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/delay.h>
16 #include <linux/param.h>
17 #include <linux/mtd/physmap.h>
18 #include <asm/txx9irq.h>
19 #include <asm/txx9tmr.h>
20 #include <asm/txx9pio.h>
21 #include <asm/txx9/generic.h>
22 #include <asm/txx9/tx4938.h>
24 static void __init tx4938_wdr_init(void)
26 /* clear WatchDogReset (W1C) */
27 tx4938_ccfg_set(TX4938_CCFG_WDRST);
28 /* do reset on watchdog */
29 tx4938_ccfg_set(TX4938_CCFG_WR);
32 void __init tx4938_wdt_init(void)
34 txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL);
37 static struct resource tx4938_sdram_resource[4];
38 static struct resource tx4938_sram_resource;
40 #define TX4938_SRAM_SIZE 0x800
42 void __init tx4938_setup(void)
49 txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE,
51 set_c0_config(TX49_CONF_CWFON);
53 /* SDRAMC,EBUSC are configured by PROM */
54 for (i = 0; i < 8; i++) {
55 if (!(TX4938_EBUSC_CR(i) & 0x8))
56 continue; /* disabled */
57 txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
59 txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
60 request_resource(&iomem_resource, &txx9_ce_res[i]);
64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
65 if (txx9_master_clock) {
66 /* calculate gbus_clock and cpu_clock from master_clock */
67 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
69 case TX4938_CCFG_DIVMODE_8:
70 case TX4938_CCFG_DIVMODE_10:
71 case TX4938_CCFG_DIVMODE_12:
72 case TX4938_CCFG_DIVMODE_16:
73 case TX4938_CCFG_DIVMODE_18:
74 txx9_gbus_clock = txx9_master_clock * 4; break;
76 txx9_gbus_clock = txx9_master_clock;
79 case TX4938_CCFG_DIVMODE_2:
80 case TX4938_CCFG_DIVMODE_8:
81 cpuclk = txx9_gbus_clock * 2; break;
82 case TX4938_CCFG_DIVMODE_2_5:
83 case TX4938_CCFG_DIVMODE_10:
84 cpuclk = txx9_gbus_clock * 5 / 2; break;
85 case TX4938_CCFG_DIVMODE_3:
86 case TX4938_CCFG_DIVMODE_12:
87 cpuclk = txx9_gbus_clock * 3; break;
88 case TX4938_CCFG_DIVMODE_4:
89 case TX4938_CCFG_DIVMODE_16:
90 cpuclk = txx9_gbus_clock * 4; break;
91 case TX4938_CCFG_DIVMODE_4_5:
92 case TX4938_CCFG_DIVMODE_18:
93 cpuclk = txx9_gbus_clock * 9 / 2; break;
95 txx9_cpu_clock = cpuclk;
97 if (txx9_cpu_clock == 0)
98 txx9_cpu_clock = 300000000; /* 300MHz */
99 /* calculate gbus_clock and master_clock from cpu_clock */
100 cpuclk = txx9_cpu_clock;
101 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
103 case TX4938_CCFG_DIVMODE_2:
104 case TX4938_CCFG_DIVMODE_8:
105 txx9_gbus_clock = cpuclk / 2; break;
106 case TX4938_CCFG_DIVMODE_2_5:
107 case TX4938_CCFG_DIVMODE_10:
108 txx9_gbus_clock = cpuclk * 2 / 5; break;
109 case TX4938_CCFG_DIVMODE_3:
110 case TX4938_CCFG_DIVMODE_12:
111 txx9_gbus_clock = cpuclk / 3; break;
112 case TX4938_CCFG_DIVMODE_4:
113 case TX4938_CCFG_DIVMODE_16:
114 txx9_gbus_clock = cpuclk / 4; break;
115 case TX4938_CCFG_DIVMODE_4_5:
116 case TX4938_CCFG_DIVMODE_18:
117 txx9_gbus_clock = cpuclk * 2 / 9; break;
120 case TX4938_CCFG_DIVMODE_8:
121 case TX4938_CCFG_DIVMODE_10:
122 case TX4938_CCFG_DIVMODE_12:
123 case TX4938_CCFG_DIVMODE_16:
124 case TX4938_CCFG_DIVMODE_18:
125 txx9_master_clock = txx9_gbus_clock / 4; break;
127 txx9_master_clock = txx9_gbus_clock;
130 /* change default value to udelay/mdelay take reasonable time */
131 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
135 /* clear BusErrorOnWrite flag (W1C) */
136 tx4938_ccfg_set(TX4938_CCFG_BEOW);
137 /* enable Timeout BusError */
139 tx4938_ccfg_set(TX4938_CCFG_TOE);
142 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
144 /* Use external clock for external arbiter */
145 if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
146 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
148 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
150 (cpuclk + 500000) / 1000000,
151 (txx9_master_clock + 500000) / 1000000,
152 (__u32)____raw_readq(&tx4938_ccfgptr->crir),
153 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
154 (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
156 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
157 for (i = 0; i < 4; i++) {
158 __u64 cr = TX4938_SDRAMC_CR(i);
159 unsigned long base, size;
160 if (!((__u32)cr & 0x00000400))
161 continue; /* disabled */
162 base = (unsigned long)(cr >> 49) << 21;
163 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
164 printk(" CR%d:%016llx", i, (unsigned long long)cr);
165 tx4938_sdram_resource[i].name = "SDRAM";
166 tx4938_sdram_resource[i].start = base;
167 tx4938_sdram_resource[i].end = base + size - 1;
168 tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
169 request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
171 printk(" TR:%09llx\n",
172 (unsigned long long)____raw_readq(&tx4938_sdramcptr->tr));
175 if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) {
176 unsigned int size = TX4938_SRAM_SIZE;
177 tx4938_sram_resource.name = "SRAM";
178 tx4938_sram_resource.start =
179 (____raw_readq(&tx4938_sramcptr->cr) >> (39-11))
181 tx4938_sram_resource.end =
182 tx4938_sram_resource.start + TX4938_SRAM_SIZE - 1;
183 tx4938_sram_resource.flags = IORESOURCE_MEM;
184 request_resource(&iomem_resource, &tx4938_sram_resource);
188 /* disable all timers */
189 for (i = 0; i < TX4938_NR_TMR; i++)
190 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
193 for (i = 0; i < 2; i++)
194 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
195 (void __iomem *)(TX4938_DMA_REG(i) + 0x50));
198 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
199 __raw_writel(0, &tx4938_pioptr->maskcpu);
200 __raw_writel(0, &tx4938_pioptr->maskext);
202 if (txx9_pcode == 0x4938) {
203 __u64 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
204 /* set PCIC1 reset */
205 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
206 if (pcfg & (TX4938_PCFG_ETH0_SEL | TX4938_PCFG_ETH1_SEL)) {
207 mdelay(1); /* at least 128 cpu clock */
208 /* clear PCIC1 reset */
209 txx9_clear64(&tx4938_ccfgptr->clkctr,
210 TX4938_CLKCTR_PCIC1RST);
212 printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str);
214 txx9_set64(&tx4938_ccfgptr->clkctr,
215 TX4938_CLKCTR_PCIC1CKD);
217 if (!(pcfg & TX4938_PCFG_ETH0_SEL)) {
218 printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str);
219 txx9_set64(&tx4938_ccfgptr->clkctr,
220 TX4938_CLKCTR_ETH0RST);
221 txx9_set64(&tx4938_ccfgptr->clkctr,
222 TX4938_CLKCTR_ETH0CKD);
224 if (!(pcfg & TX4938_PCFG_ETH1_SEL)) {
225 printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str);
226 txx9_set64(&tx4938_ccfgptr->clkctr,
227 TX4938_CLKCTR_ETH1RST);
228 txx9_set64(&tx4938_ccfgptr->clkctr,
229 TX4938_CLKCTR_ETH1CKD);
234 void __init tx4938_time_init(unsigned int tmrnr)
236 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
237 txx9_clockevent_init(TX4938_TMR_REG(tmrnr) & 0xfffffffffULL,
238 TXX9_IRQ_BASE + TX4938_IR_TMR(tmrnr),
242 void __init tx4938_sio_init(unsigned int sclk, unsigned int cts_mask)
245 unsigned int ch_mask = 0;
247 if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_ETH0_SEL)
248 ch_mask |= 1 << 1; /* disable SIO1 by PCFG setting */
249 for (i = 0; i < 2; i++) {
250 if ((1 << i) & ch_mask)
252 txx9_sio_init(TX4938_SIO_REG(i) & 0xfffffffffULL,
253 TXX9_IRQ_BASE + TX4938_IR_SIO(i),
254 i, sclk, (1 << i) & cts_mask);
258 void __init tx4938_spi_init(int busid)
260 txx9_spi_init(busid, TX4938_SPI_REG & 0xfffffffffULL,
261 TXX9_IRQ_BASE + TX4938_IR_SPI);
264 void __init tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
266 u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg);
268 if (addr0 && (pcfg & TX4938_PCFG_ETH0_SEL))
269 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH0, addr0);
270 if (addr1 && (pcfg & TX4938_PCFG_ETH1_SEL))
271 txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH1, addr1);
274 void __init tx4938_mtd_init(int ch)
276 struct physmap_flash_data pdata = {
277 .width = TX4938_EBUSC_WIDTH(ch) / 8,
279 unsigned long start = txx9_ce_res[ch].start;
280 unsigned long size = txx9_ce_res[ch].end - start + 1;
282 if (!(TX4938_EBUSC_CR(ch) & 0x8))
283 return; /* disabled */
284 txx9_physmap_flash_init(ch, start, size, &pdata);