2 * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 * bcm1480_irq_handler() is the routine that is actually called when an
21 * interrupt occurs. It is installed as the exception vector handler in
22 * init_IRQ() in arch/mips/sibyte/bcm1480/irq.c
24 * In the handle we figure out which interrupts need handling, and use that
25 * to call the dispatcher, which will take care of actually calling
28 * Note that we take care of all raised interrupts in one go at the handler.
29 * This is more BSDish than the Indy code, and also, IMHO, more sane.
31 #include <linux/config.h>
33 #include <asm/addrspace.h>
35 #include <asm/mipsregs.h>
36 #include <asm/regdef.h>
37 #include <asm/stackframe.h>
38 #include <asm/sibyte/sb1250_defs.h>
39 #include <asm/sibyte/bcm1480_regs.h>
40 #include <asm/sibyte/bcm1480_int.h>
43 * What a pain. We have to be really careful saving the upper 32 bits of any
44 * register across function calls if we don't want them trashed--since were
45 * running in -o32, the calling routing never saves the full 64 bits of a
46 * register across a function call. Being the interrupt handler, we're
47 * guaranteed that interrupts are disabled during this code so we don't have
48 * to worry about random interrupts blasting the high 32 bits.
58 NESTED(bcm1480_irq_handler, PT_SIZE, sp)
62 #ifdef CONFIG_SIBYTE_BCM1480_PROF
63 /* Set compare to count to silence count/compare timer interrupts */
65 mtc0 t1, CP0_COMPARE /* pause to clear IP[7] bit of cause ? */
70 #ifdef CONFIG_SIBYTE_BCM1480_PROF
71 /* Cpu performance counter interrupt is routed to IP[7] */
72 andi t1, s0, CAUSEF_IP7
74 srl t1, s0, (CAUSEB_BD-2) /* Shift BD bit to bit 2 */
75 and t1, t1, 0x4 /* mask to get just BD bit */
78 daddu a0, a0, t1 /* a0 = EPC + (BD ? 4 : 0) */
81 addu a0, a0, t1 /* a0 = EPC + (BD ? 4 : 0) */
90 /* Timer interrupt is routed to IP[4] */
91 andi t1, s0, CAUSEF_IP4
94 jal bcm1480_timer_interrupt
95 move a0, sp /* Pass the registers along */
101 /* Mailbox interrupt is routed to IP[3] */
102 andi t1, s0, CAUSEF_IP3
105 jal bcm1480_mailbox_interrupt
113 /* KGDB (uart 1) interrupt is routed to IP[6] */
114 andi t1, s0, CAUSEF_IP6
117 jal bcm1480_kgdb_interrupt
124 and t1, s0, CAUSEF_IP2
129 * Default...we've hit an IP[2] interrupt, which means we've got
130 * to check the 1480 interrupt registers to figure out what to do
131 * Need to detect which CPU we're on, now that smp_affinity is
134 PTR_LA v0, CKSEG1 + A_BCM1480_IMR_CPU0_BASE
137 sll t1, t1, BCM1480_IMR_REGISTER_SPACING_SHIFT
141 /* Read IP[2] status (get both high and low halves of status) */
142 ld s0, R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H(v0)
143 ld s1, R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L(v0)
145 move s2, zero /* intr number */
148 beqz s0, 9f /* No interrupts. Return. */
151 xori s4, s0, 1 /* if s0 (_H) == 1, it's a low intr, so... */
152 movz s2, s3, s4 /* start the intr number at 64, and */
153 movz s0, s1, s4 /* look at the low status value. */
155 dclz s1, s0 /* Find the next interrupt. */
165 END(bcm1480_irq_handler)