2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
4 * Copyright (C) 2001 Ralf Baechle
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 * Routines for generic manipulation of the interrupts found on the MIPS
21 * The interrupt controller is located in the South Bridge a PIIX4 device
22 * with two internal 82C95 interrupt controllers.
24 #include <linux/init.h>
25 #include <linux/irq.h>
26 #include <linux/sched.h>
27 #include <linux/smp.h>
28 #include <linux/interrupt.h>
30 #include <linux/kernel_stat.h>
31 #include <linux/kernel.h>
32 #include <linux/random.h>
34 #include <asm/traps.h>
35 #include <asm/i8259.h>
36 #include <asm/irq_cpu.h>
37 #include <asm/irq_regs.h>
38 #include <asm/mips-boards/malta.h>
39 #include <asm/mips-boards/maltaint.h>
40 #include <asm/mips-boards/piix4.h>
41 #include <asm/gt64120.h>
42 #include <asm/mips-boards/generic.h>
43 #include <asm/mips-boards/msc01_pci.h>
44 #include <asm/msc01_ic.h>
46 #include <asm/gcmpregs.h>
48 int gcmp_present = -1;
50 static unsigned long _msc01_biu_base;
51 static unsigned long _gcmp_base;
52 static unsigned int ipi_map[NR_CPUS];
54 static DEFINE_RAW_SPINLOCK(mips_irq_lock);
56 static inline int mips_pcibios_iack(void)
61 * Determine highest priority pending interrupt by performing
62 * a PCI Interrupt Acknowledge cycle.
64 switch (mips_revision_sconid) {
65 case MIPS_REVISION_SCON_SOCIT:
66 case MIPS_REVISION_SCON_ROCIT:
67 case MIPS_REVISION_SCON_SOCITSC:
68 case MIPS_REVISION_SCON_SOCITSCP:
69 MSC_READ(MSC01_PCI_IACK, irq);
72 case MIPS_REVISION_SCON_GT64120:
73 irq = GT_READ(GT_PCI0_IACK_OFS);
76 case MIPS_REVISION_SCON_BONITO:
77 /* The following will generate a PCI IACK cycle on the
78 * Bonito controller. It's a little bit kludgy, but it
79 * was the easiest way to implement it in hardware at
82 BONITO_PCIMAP_CFG = 0x20000;
84 /* Flush Bonito register block */
85 (void) BONITO_PCIMAP_CFG;
88 irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
91 BONITO_PCIMAP_CFG = 0;
94 printk(KERN_WARNING "Unknown system controller.\n");
100 static inline int get_int(void)
104 raw_spin_lock_irqsave(&mips_irq_lock, flags);
106 irq = mips_pcibios_iack();
109 * The only way we can decide if an interrupt is spurious
110 * is by checking the 8259 registers. This needs a spinlock
111 * on an SMP system, so leave it up to the generic code...
114 raw_spin_unlock_irqrestore(&mips_irq_lock, flags);
119 static void malta_hw0_irqdispatch(void)
125 /* interrupt has already been cleared */
129 do_IRQ(MALTA_INT_BASE + irq);
132 static void malta_ipi_irqdispatch(void)
138 return; /* interrupt has already been cleared */
140 do_IRQ(MIPS_GIC_IRQ_BASE + irq);
143 static void corehi_irqdispatch(void)
145 unsigned int intedge, intsteer, pcicmd, pcibadaddr;
146 unsigned int pcimstat, intisr, inten, intpol;
147 unsigned int intrcause, datalo, datahi;
148 struct pt_regs *regs = get_irq_regs();
150 printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");
151 printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n"
152 "Cause : %08lx\nbadVaddr : %08lx\n",
153 regs->cp0_epc, regs->cp0_status,
154 regs->cp0_cause, regs->cp0_badvaddr);
156 /* Read all the registers and then print them as there is a
157 problem with interspersed printk's upsetting the Bonito controller.
158 Do it for the others too.
161 switch (mips_revision_sconid) {
162 case MIPS_REVISION_SCON_SOCIT:
163 case MIPS_REVISION_SCON_ROCIT:
164 case MIPS_REVISION_SCON_SOCITSC:
165 case MIPS_REVISION_SCON_SOCITSCP:
168 case MIPS_REVISION_SCON_GT64120:
169 intrcause = GT_READ(GT_INTRCAUSE_OFS);
170 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
171 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
172 printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause);
173 printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n",
176 case MIPS_REVISION_SCON_BONITO:
177 pcibadaddr = BONITO_PCIBADADDR;
178 pcimstat = BONITO_PCIMSTAT;
179 intisr = BONITO_INTISR;
180 inten = BONITO_INTEN;
181 intpol = BONITO_INTPOL;
182 intedge = BONITO_INTEDGE;
183 intsteer = BONITO_INTSTEER;
184 pcicmd = BONITO_PCICMD;
185 printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr);
186 printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten);
187 printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol);
188 printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge);
189 printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer);
190 printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd);
191 printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr);
192 printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat);
196 die("CoreHi interrupt", regs);
199 static inline int clz(unsigned long x)
213 * Version of ffs that only looks at bits 12..15.
215 static inline unsigned int irq_ffs(unsigned int pending)
217 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
218 return -clz(pending) + 31 - CAUSEB_IP;
223 t0 = pending & 0xf000;
227 pending = pending << t0;
229 t0 = pending & 0xc000;
233 pending = pending << t0;
235 t0 = pending & 0x8000;
239 /* pending = pending << t0; */
246 * IRQs on the Malta board look basically (barring software IRQs which we
247 * don't use at all and all external interrupt sources are combined together
248 * on hardware interrupt 0 (MIPS IRQ 2)) like:
252 * 0 Software (ignored)
253 * 1 Software (ignored)
254 * 2 Combined hardware interrupt (hw0)
255 * 3 Hardware (ignored)
256 * 4 Hardware (ignored)
257 * 5 Hardware (ignored)
258 * 6 Hardware (ignored)
259 * 7 R4k timer (what we use)
261 * We handle the IRQ according to _our_ priority which is:
263 * Highest ---- R4k Timer
264 * Lowest ---- Combined hardware interrupt
266 * then we just return, if multiple IRQs are pending then we will just take
267 * another exception, big deal.
270 asmlinkage void plat_irq_dispatch(void)
272 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
275 irq = irq_ffs(pending);
277 if (irq == MIPSCPU_INT_I8259A)
278 malta_hw0_irqdispatch();
279 else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()]))
280 malta_ipi_irqdispatch();
282 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
284 spurious_interrupt();
287 #ifdef CONFIG_MIPS_MT_SMP
290 #define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3
291 #define GIC_MIPS_CPU_IPI_CALL_IRQ 4
293 #define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
294 #define C_RESCHED C_SW0
295 #define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */
297 static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
299 static void ipi_resched_dispatch(void)
301 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
304 static void ipi_call_dispatch(void)
306 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
309 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
316 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
318 smp_call_function_interrupt();
323 static struct irqaction irq_resched = {
324 .handler = ipi_resched_interrupt,
325 .flags = IRQF_DISABLED|IRQF_PERCPU,
326 .name = "IPI_resched"
329 static struct irqaction irq_call = {
330 .handler = ipi_call_interrupt,
331 .flags = IRQF_DISABLED|IRQF_PERCPU,
334 #endif /* CONFIG_MIPS_MT_SMP */
336 static int gic_resched_int_base;
337 static int gic_call_int_base;
338 #define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
339 #define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
341 unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
343 return GIC_CALL_INT(cpu);
346 unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
348 return GIC_RESCHED_INT(cpu);
351 static struct irqaction i8259irq = {
352 .handler = no_action,
353 .name = "XT-PIC cascade",
354 .flags = IRQF_NO_THREAD,
357 static struct irqaction corehi_irqaction = {
358 .handler = no_action,
360 .flags = IRQF_NO_THREAD,
363 static msc_irqmap_t __initdata msc_irqmap[] = {
364 {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
365 {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
367 static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap);
369 static msc_irqmap_t __initdata msc_eicirqmap[] = {
370 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
371 {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
372 {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
373 {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
374 {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
375 {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
376 {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
377 {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
378 {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
379 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
382 static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
385 * This GIC specific tabular array defines the association between External
386 * Interrupts and CPUs/Core Interrupts. The nature of the External
387 * Interrupts is also defined here - polarity/trigger.
390 #define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK
393 static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
397 { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
398 { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
399 { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
400 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
401 { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
402 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
403 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
406 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
407 { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
408 { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
410 /* The remainder of this table is initialised by fill_ipi_map */
415 * GCMP needs to be detected before any SMP initialisation
417 int __init gcmp_probe(unsigned long addr, unsigned long size)
419 if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) {
424 if (gcmp_present >= 0)
427 _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
428 _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ);
429 gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR;
432 pr_debug("GCMP present\n");
436 /* Return the number of IOCU's present */
437 int __init gcmp_niocu(void)
439 return gcmp_present ?
440 (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF :
444 /* Set GCMP region attributes */
445 void __init gcmp_setregion(int region, unsigned long base,
446 unsigned long mask, int type)
448 GCMPGCBn(CMxBASE, region) = base;
449 GCMPGCBn(CMxMASK, region) = mask | type;
452 #if defined(CONFIG_MIPS_MT_SMP)
453 static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
455 int intr = baseintr + cpu;
456 gic_intr_map[intr].cpunum = cpu;
457 gic_intr_map[intr].pin = cpupin;
458 gic_intr_map[intr].polarity = GIC_POL_POS;
459 gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
460 gic_intr_map[intr].flags = GIC_FLAG_IPI;
461 ipi_map[cpu] |= (1 << (cpupin + 2));
464 static void __init fill_ipi_map(void)
468 for (cpu = 0; cpu < NR_CPUS; cpu++) {
469 fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1);
470 fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2);
475 void __init arch_init_ipiirq(int irq, struct irqaction *action)
477 setup_irq(irq, action);
478 irq_set_handler(irq, handle_percpu_irq);
481 void __init arch_init_irq(void)
489 GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
492 if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
493 _msc01_biu_base = (unsigned long)
494 ioremap_nocache(MSC01_BIU_REG_BASE,
495 MSC01_BIU_ADDRSPACE_SZ);
496 gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
497 MSC01_SC_CFG_GICPRES_MSK) >>
498 MSC01_SC_CFG_GICPRES_SHF;
502 pr_debug("GIC present\n");
504 switch (mips_revision_sconid) {
505 case MIPS_REVISION_SCON_SOCIT:
506 case MIPS_REVISION_SCON_ROCIT:
508 init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
509 MSC01E_INT_BASE, msc_eicirqmap,
512 init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
513 MSC01C_INT_BASE, msc_irqmap,
517 case MIPS_REVISION_SCON_SOCITSC:
518 case MIPS_REVISION_SCON_SOCITSCP:
520 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
521 MSC01E_INT_BASE, msc_eicirqmap,
524 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
525 MSC01C_INT_BASE, msc_irqmap,
530 set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch);
531 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
532 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
533 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
534 } else if (cpu_has_vint) {
535 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
536 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
537 #ifdef CONFIG_MIPS_MT_SMTC
538 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
539 (0x100 << MIPSCPU_INT_I8259A));
540 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
541 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
543 * Temporary hack to ensure that the subsidiary device
544 * interrupts coing in via the i8259A, but associated
545 * with low IRQ numbers, will restore the Status.IM
546 * value associated with the i8259A.
551 for (i = 0; i < 16; i++)
552 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
555 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
556 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
558 #endif /* CONFIG_MIPS_MT_SMTC */
560 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
561 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
568 #if defined(CONFIG_MIPS_MT_SMP)
569 gic_call_int_base = GIC_NUM_INTRS - NR_CPUS;
570 gic_resched_int_base = gic_call_int_base - NR_CPUS;
573 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
574 ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
577 i = REG(_msc01_biu_base, MSC01_SC_CFG);
578 REG(_msc01_biu_base, MSC01_SC_CFG) =
579 (i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
580 pr_debug("GIC Enabled\n");
582 #if defined(CONFIG_MIPS_MT_SMP)
583 /* set up ipi interrupts */
585 set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch);
586 set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch);
588 /* Argh.. this really needs sorting out.. */
589 printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status());
590 write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4);
591 printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
592 write_c0_status(0x1100dc00);
593 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
594 for (i = 0; i < NR_CPUS; i++) {
595 arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
596 GIC_RESCHED_INT(i), &irq_resched);
597 arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
598 GIC_CALL_INT(i), &irq_call);
602 #if defined(CONFIG_MIPS_MT_SMP)
603 /* set up ipi interrupts */
605 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
606 set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
607 cpu_ipi_resched_irq = MSC01E_INT_SW0;
608 cpu_ipi_call_irq = MSC01E_INT_SW1;
611 set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
612 set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
614 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
615 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
617 arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
618 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
623 void malta_be_init(void)
626 /* Could change CM error mask register */
631 static char *tr[8] = {
632 "mem", "gcr", "gic", "mmio",
633 "0x04", "0x05", "0x06", "0x07"
636 static char *mcmd[32] = {
638 [0x01] = "Legacy Write",
639 [0x02] = "Legacy Read",
645 [0x08] = "Coherent Read Own",
646 [0x09] = "Coherent Read Share",
647 [0x0a] = "Coherent Read Discard",
648 [0x0b] = "Coherent Ready Share Always",
649 [0x0c] = "Coherent Upgrade",
650 [0x0d] = "Coherent Writeback",
653 [0x10] = "Coherent Copyback",
654 [0x11] = "Coherent Copyback Invalidate",
655 [0x12] = "Coherent Invalidate",
656 [0x13] = "Coherent Write Invalidate",
657 [0x14] = "Coherent Completion Sync",
671 static char *core[8] = {
672 "Invalid/OK", "Invalid/Data",
673 "Shared/OK", "Shared/Data",
674 "Modified/OK", "Modified/Data",
675 "Exclusive/OK", "Exclusive/Data"
678 static char *causes[32] = {
679 "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
680 "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
681 "0x08", "0x09", "0x0a", "0x0b",
682 "0x0c", "0x0d", "0x0e", "0x0f",
683 "0x10", "0x11", "0x12", "0x13",
684 "0x14", "0x15", "0x16", "INTVN_WR_ERR",
685 "INTVN_RD_ERR", "0x19", "0x1a", "0x1b",
686 "0x1c", "0x1d", "0x1e", "0x1f"
689 int malta_be_handler(struct pt_regs *regs, int is_fixup)
691 /* This duplicates the handling in do_be which seems wrong */
692 int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
695 unsigned long cm_error = GCMPGCB(GCMEC);
696 unsigned long cm_addr = GCMPGCB(GCMEA);
697 unsigned long cm_other = GCMPGCB(GCMEO);
698 unsigned long cause, ocause;
701 cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK);
703 cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF;
705 unsigned long cca_bits = (cm_error >> 15) & 7;
706 unsigned long tr_bits = (cm_error >> 12) & 7;
707 unsigned long mcmd_bits = (cm_error >> 7) & 0x1f;
708 unsigned long stag_bits = (cm_error >> 3) & 15;
709 unsigned long sport_bits = (cm_error >> 0) & 7;
711 snprintf(buf, sizeof(buf),
712 "CCA=%lu TR=%s MCmd=%s STag=%lu "
714 cca_bits, tr[tr_bits], mcmd[mcmd_bits],
715 stag_bits, sport_bits);
717 /* glob state & sresp together */
718 unsigned long c3_bits = (cm_error >> 18) & 7;
719 unsigned long c2_bits = (cm_error >> 15) & 7;
720 unsigned long c1_bits = (cm_error >> 12) & 7;
721 unsigned long c0_bits = (cm_error >> 9) & 7;
722 unsigned long sc_bit = (cm_error >> 8) & 1;
723 unsigned long mcmd_bits = (cm_error >> 3) & 0x1f;
724 unsigned long sport_bits = (cm_error >> 0) & 7;
725 snprintf(buf, sizeof(buf),
726 "C3=%s C2=%s C1=%s C0=%s SC=%s "
727 "MCmd=%s SPort=%lu\n",
728 core[c3_bits], core[c2_bits],
729 core[c1_bits], core[c0_bits],
730 sc_bit ? "True" : "False",
731 mcmd[mcmd_bits], sport_bits);
734 ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >>
735 GCMP_GCB_GMEO_ERROR_2ND_SHF;
737 printk("CM_ERROR=%08lx %s <%s>\n", cm_error,
739 printk("CM_ADDR =%08lx\n", cm_addr);
740 printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
742 /* reprime cause register */