2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Synthesize TLB refill handlers at runtime.
8 * Copyright (C) 2004,2005 by Thiemo Seufer
9 * Copyright (C) 2005 Maciej W. Rozycki
14 #include <linux/config.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
21 #include <asm/pgtable.h>
22 #include <asm/cacheflush.h>
23 #include <asm/mmu_context.h>
29 /* #define DEBUG_TLB */
31 static __init int __attribute__((unused)) r45k_bvahwbug(void)
33 /* XXX: We should probe for the presence of this bug, but we don't. */
37 static __init int __attribute__((unused)) r4k_250MHZhwbug(void)
39 /* XXX: We should probe for the presence of this bug, but we don't. */
43 static __init int __attribute__((unused)) bcm1250_m3_war(void)
45 return BCM1250_M3_WAR;
48 static __init int __attribute__((unused)) r10000_llsc_war(void)
50 return R10000_LLSC_WAR;
54 * A little micro-assembler, intended for TLB refill handler
55 * synthesizing. It is intentionally kept simple, does only support
56 * a subset of instructions, and does not try to hide pipeline effects
57 * like branch delay slots.
83 #define IMM_MASK 0xffff
85 #define JIMM_MASK 0x3ffffff
87 #define FUNC_MASK 0x2f
92 insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
93 insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
94 insn_bne, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0,
95 insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
96 insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld,
97 insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0,
98 insn_ori, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
99 insn_sra, insn_srl, insn_subu, insn_sw, insn_tlbp, insn_tlbwi,
100 insn_tlbwr, insn_xor, insn_xori
109 /* This macro sets the non-variable bits of an instruction. */
110 #define M(a, b, c, d, e, f) \
118 static __initdata struct insn insn_table[] = {
119 { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM },
120 { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD },
121 { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD },
122 { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM },
123 { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM },
124 { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM },
125 { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM },
126 { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM },
127 { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM },
128 { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM },
129 { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM },
130 { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM },
131 { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD },
132 { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD },
133 { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD },
134 { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE },
135 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE },
136 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE },
137 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE },
138 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD },
139 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 },
140 { insn_j, M(j_op,0,0,0,0,0), JIMM },
141 { insn_jal, M(jal_op,0,0,0,0,0), JIMM },
142 { insn_jr, M(spec_op,0,0,0,0,jr_op), RS },
143 { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM },
144 { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM },
145 { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM },
146 { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM },
147 { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM },
148 { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD },
149 { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD },
150 { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM },
151 { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 },
152 { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM },
153 { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM },
154 { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM },
155 { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE },
156 { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE },
157 { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE },
158 { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD },
159 { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM },
160 { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 },
161 { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 },
162 { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 },
163 { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD },
164 { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM },
165 { insn_invalid, 0, 0 }
170 static __init u32 build_rs(u32 arg)
173 printk(KERN_WARNING "TLB synthesizer field overflow\n");
175 return (arg & RS_MASK) << RS_SH;
178 static __init u32 build_rt(u32 arg)
181 printk(KERN_WARNING "TLB synthesizer field overflow\n");
183 return (arg & RT_MASK) << RT_SH;
186 static __init u32 build_rd(u32 arg)
189 printk(KERN_WARNING "TLB synthesizer field overflow\n");
191 return (arg & RD_MASK) << RD_SH;
194 static __init u32 build_re(u32 arg)
197 printk(KERN_WARNING "TLB synthesizer field overflow\n");
199 return (arg & RE_MASK) << RE_SH;
202 static __init u32 build_simm(s32 arg)
204 if (arg > 0x7fff || arg < -0x8000)
205 printk(KERN_WARNING "TLB synthesizer field overflow\n");
210 static __init u32 build_uimm(u32 arg)
213 printk(KERN_WARNING "TLB synthesizer field overflow\n");
215 return arg & IMM_MASK;
218 static __init u32 build_bimm(s32 arg)
220 if (arg > 0x1ffff || arg < -0x20000)
221 printk(KERN_WARNING "TLB synthesizer field overflow\n");
224 printk(KERN_WARNING "Invalid TLB synthesizer branch target\n");
226 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
229 static __init u32 build_jimm(u32 arg)
231 if (arg & ~((JIMM_MASK) << 2))
232 printk(KERN_WARNING "TLB synthesizer field overflow\n");
234 return (arg >> 2) & JIMM_MASK;
237 static __init u32 build_func(u32 arg)
239 if (arg & ~FUNC_MASK)
240 printk(KERN_WARNING "TLB synthesizer field overflow\n");
242 return arg & FUNC_MASK;
246 * The order of opcode arguments is implicitly left to right,
247 * starting with RS and ending with FUNC or IMM.
249 static void __init build_insn(u32 **buf, enum opcode opc, ...)
251 struct insn *ip = NULL;
256 for (i = 0; insn_table[i].opcode != insn_invalid; i++)
257 if (insn_table[i].opcode == opc) {
263 panic("Unsupported TLB synthesizer instruction %d", opc);
267 if (ip->fields & RS) op |= build_rs(va_arg(ap, u32));
268 if (ip->fields & RT) op |= build_rt(va_arg(ap, u32));
269 if (ip->fields & RD) op |= build_rd(va_arg(ap, u32));
270 if (ip->fields & RE) op |= build_re(va_arg(ap, u32));
271 if (ip->fields & SIMM) op |= build_simm(va_arg(ap, s32));
272 if (ip->fields & UIMM) op |= build_uimm(va_arg(ap, u32));
273 if (ip->fields & BIMM) op |= build_bimm(va_arg(ap, s32));
274 if (ip->fields & JIMM) op |= build_jimm(va_arg(ap, u32));
275 if (ip->fields & FUNC) op |= build_func(va_arg(ap, u32));
282 #define I_u1u2u3(op) \
283 static inline void i##op(u32 **buf, unsigned int a, \
284 unsigned int b, unsigned int c) \
286 build_insn(buf, insn##op, a, b, c); \
289 #define I_u2u1u3(op) \
290 static inline void i##op(u32 **buf, unsigned int a, \
291 unsigned int b, unsigned int c) \
293 build_insn(buf, insn##op, b, a, c); \
296 #define I_u3u1u2(op) \
297 static inline void i##op(u32 **buf, unsigned int a, \
298 unsigned int b, unsigned int c) \
300 build_insn(buf, insn##op, b, c, a); \
303 #define I_u1u2s3(op) \
304 static inline void i##op(u32 **buf, unsigned int a, \
305 unsigned int b, signed int c) \
307 build_insn(buf, insn##op, a, b, c); \
310 #define I_u2s3u1(op) \
311 static inline void i##op(u32 **buf, unsigned int a, \
312 signed int b, unsigned int c) \
314 build_insn(buf, insn##op, c, a, b); \
317 #define I_u2u1s3(op) \
318 static inline void i##op(u32 **buf, unsigned int a, \
319 unsigned int b, signed int c) \
321 build_insn(buf, insn##op, b, a, c); \
325 static inline void i##op(u32 **buf, unsigned int a, \
328 build_insn(buf, insn##op, a, b); \
332 static inline void i##op(u32 **buf, unsigned int a, \
335 build_insn(buf, insn##op, a, b); \
339 static inline void i##op(u32 **buf, unsigned int a) \
341 build_insn(buf, insn##op, a); \
345 static inline void i##op(u32 **buf) \
347 build_insn(buf, insn##op); \
412 label_smp_pgtable_change,
413 label_r3000_write_probe_fail,
421 static __init void build_label(struct label **lab, u32 *addr,
430 static inline void l##lb(struct label **lab, u32 *addr) \
432 build_label(lab, addr, label##lb); \
444 L_LA(_smp_pgtable_change)
445 L_LA(_r3000_write_probe_fail)
447 /* convenience macros for instructions */
449 # define i_LW(buf, rs, rt, off) i_ld(buf, rs, rt, off)
450 # define i_SW(buf, rs, rt, off) i_sd(buf, rs, rt, off)
451 # define i_SLL(buf, rs, rt, sh) i_dsll(buf, rs, rt, sh)
452 # define i_SRA(buf, rs, rt, sh) i_dsra(buf, rs, rt, sh)
453 # define i_SRL(buf, rs, rt, sh) i_dsrl(buf, rs, rt, sh)
454 # define i_MFC0(buf, rt, rd) i_dmfc0(buf, rt, rd)
455 # define i_MTC0(buf, rt, rd) i_dmtc0(buf, rt, rd)
456 # define i_ADDIU(buf, rs, rt, val) i_daddiu(buf, rs, rt, val)
457 # define i_ADDU(buf, rs, rt, rd) i_daddu(buf, rs, rt, rd)
458 # define i_SUBU(buf, rs, rt, rd) i_dsubu(buf, rs, rt, rd)
459 # define i_LL(buf, rs, rt, off) i_lld(buf, rs, rt, off)
460 # define i_SC(buf, rs, rt, off) i_scd(buf, rs, rt, off)
462 # define i_LW(buf, rs, rt, off) i_lw(buf, rs, rt, off)
463 # define i_SW(buf, rs, rt, off) i_sw(buf, rs, rt, off)
464 # define i_SLL(buf, rs, rt, sh) i_sll(buf, rs, rt, sh)
465 # define i_SRA(buf, rs, rt, sh) i_sra(buf, rs, rt, sh)
466 # define i_SRL(buf, rs, rt, sh) i_srl(buf, rs, rt, sh)
467 # define i_MFC0(buf, rt, rd) i_mfc0(buf, rt, rd)
468 # define i_MTC0(buf, rt, rd) i_mtc0(buf, rt, rd)
469 # define i_ADDIU(buf, rs, rt, val) i_addiu(buf, rs, rt, val)
470 # define i_ADDU(buf, rs, rt, rd) i_addu(buf, rs, rt, rd)
471 # define i_SUBU(buf, rs, rt, rd) i_subu(buf, rs, rt, rd)
472 # define i_LL(buf, rs, rt, off) i_ll(buf, rs, rt, off)
473 # define i_SC(buf, rs, rt, off) i_sc(buf, rs, rt, off)
476 #define i_b(buf, off) i_beq(buf, 0, 0, off)
477 #define i_beqz(buf, rs, off) i_beq(buf, rs, 0, off)
478 #define i_beqzl(buf, rs, off) i_beql(buf, rs, 0, off)
479 #define i_bnez(buf, rs, off) i_bne(buf, rs, 0, off)
480 #define i_bnezl(buf, rs, off) i_bnel(buf, rs, 0, off)
481 #define i_move(buf, a, b) i_ADDU(buf, a, 0, b)
482 #define i_nop(buf) i_sll(buf, 0, 0, 0)
483 #define i_ssnop(buf) i_sll(buf, 0, 0, 1)
484 #define i_ehb(buf) i_sll(buf, 0, 0, 3)
487 static __init int __attribute__((unused)) in_compat_space_p(long addr)
489 /* Is this address in 32bit compat space? */
490 return (((addr) & 0xffffffff00000000) == 0xffffffff00000000);
493 static __init int __attribute__((unused)) rel_highest(long val)
495 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
498 static __init int __attribute__((unused)) rel_higher(long val)
500 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
504 static __init int rel_hi(long val)
506 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
509 static __init int rel_lo(long val)
511 return ((val & 0xffff) ^ 0x8000) - 0x8000;
514 static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr)
517 if (!in_compat_space_p(addr)) {
518 i_lui(buf, rs, rel_highest(addr));
519 if (rel_higher(addr))
520 i_daddiu(buf, rs, rs, rel_higher(addr));
522 i_dsll(buf, rs, rs, 16);
523 i_daddiu(buf, rs, rs, rel_hi(addr));
524 i_dsll(buf, rs, rs, 16);
526 i_dsll32(buf, rs, rs, 0);
529 i_lui(buf, rs, rel_hi(addr));
532 static __init void __attribute__((unused)) i_LA(u32 **buf, unsigned int rs,
535 i_LA_mostly(buf, rs, addr);
537 i_ADDIU(buf, rs, rs, rel_lo(addr));
550 static __init void r_mips_pc16(struct reloc **rel, u32 *addr,
554 (*rel)->type = R_MIPS_PC16;
559 static inline void __resolve_relocs(struct reloc *rel, struct label *lab)
561 long laddr = (long)lab->addr;
562 long raddr = (long)rel->addr;
566 *rel->addr |= build_bimm(laddr - (raddr + 4));
570 panic("Unsupported TLB synthesizer relocation %d",
575 static __init void resolve_relocs(struct reloc *rel, struct label *lab)
579 for (; rel->lab != label_invalid; rel++)
580 for (l = lab; l->lab != label_invalid; l++)
581 if (rel->lab == l->lab)
582 __resolve_relocs(rel, l);
585 static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end,
588 for (; rel->lab != label_invalid; rel++)
589 if (rel->addr >= first && rel->addr < end)
593 static __init void move_labels(struct label *lab, u32 *first, u32 *end,
596 for (; lab->lab != label_invalid; lab++)
597 if (lab->addr >= first && lab->addr < end)
601 static __init void copy_handler(struct reloc *rel, struct label *lab,
602 u32 *first, u32 *end, u32 *target)
604 long off = (long)(target - first);
606 memcpy(target, first, (end - first) * sizeof(u32));
608 move_relocs(rel, first, end, off);
609 move_labels(lab, first, end, off);
612 static __init int __attribute__((unused)) insn_has_bdelay(struct reloc *rel,
615 for (; rel->lab != label_invalid; rel++) {
616 if (rel->addr == addr
617 && (rel->type == R_MIPS_PC16
618 || rel->type == R_MIPS_26))
625 /* convenience functions for labeled branches */
626 static void __attribute__((unused)) il_bltz(u32 **p, struct reloc **r,
627 unsigned int reg, enum label_id l)
629 r_mips_pc16(r, *p, l);
633 static void __attribute__((unused)) il_b(u32 **p, struct reloc **r,
636 r_mips_pc16(r, *p, l);
640 static void il_beqz(u32 **p, struct reloc **r, unsigned int reg,
643 r_mips_pc16(r, *p, l);
647 static void __attribute__((unused))
648 il_beqzl(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
650 r_mips_pc16(r, *p, l);
654 static void il_bnez(u32 **p, struct reloc **r, unsigned int reg,
657 r_mips_pc16(r, *p, l);
661 static void il_bgezl(u32 **p, struct reloc **r, unsigned int reg,
664 r_mips_pc16(r, *p, l);
668 /* The only general purpose registers allowed in TLB handlers. */
672 /* Some CP0 registers */
674 #define C0_ENTRYLO0 2
675 #define C0_ENTRYLO1 3
677 #define C0_BADVADDR 8
678 #define C0_ENTRYHI 10
680 #define C0_XCONTEXT 20
683 # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_XCONTEXT)
685 # define GET_CONTEXT(buf, reg) i_MFC0(buf, reg, C0_CONTEXT)
688 /* The worst case length of the handler is around 18 instructions for
689 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
690 * Maximum space available is 32 instructions for R3000 and 64
691 * instructions for R4000.
693 * We deliberately chose a buffer size of 128, so we won't scribble
694 * over anything important on overflow before we panic.
696 static __initdata u32 tlb_handler[128];
698 /* simply assume worst case size for labels and relocs */
699 static __initdata struct label labels[128];
700 static __initdata struct reloc relocs[128];
703 * The R3000 TLB handler is simple.
705 static void __init build_r3000_tlb_refill_handler(void)
707 long pgdc = (long)pgd_current;
710 memset(tlb_handler, 0, sizeof(tlb_handler));
713 i_mfc0(&p, K0, C0_BADVADDR);
714 i_lui(&p, K1, rel_hi(pgdc)); /* cp0 delay */
715 i_lw(&p, K1, rel_lo(pgdc), K1);
716 i_srl(&p, K0, K0, 22); /* load delay */
717 i_sll(&p, K0, K0, 2);
718 i_addu(&p, K1, K1, K0);
719 i_mfc0(&p, K0, C0_CONTEXT);
720 i_lw(&p, K1, 0, K1); /* cp0 delay */
721 i_andi(&p, K0, K0, 0xffc); /* load delay */
722 i_addu(&p, K1, K1, K0);
724 i_nop(&p); /* load delay */
725 i_mtc0(&p, K0, C0_ENTRYLO0);
726 i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
727 i_tlbwr(&p); /* cp0 delay */
729 i_rfe(&p); /* branch delay */
731 if (p > tlb_handler + 32)
732 panic("TLB refill handler space exceeded");
734 printk("Synthesized TLB refill handler (%u instructions).\n",
735 (unsigned int)(p - tlb_handler));
740 for (i = 0; i < (p - tlb_handler); i++)
741 printk("%08x\n", tlb_handler[i]);
745 memcpy((void *)CAC_BASE, tlb_handler, 0x80);
746 flush_icache_range(CAC_BASE, CAC_BASE + 0x80);
750 * The R4000 TLB handler is much more complicated. We have two
751 * consecutive handler areas with 32 instructions space each.
752 * Since they aren't used at the same time, we can overflow in the
753 * other one.To keep things simple, we first assume linear space,
754 * then we relocate it to the final handler layout as needed.
756 static __initdata u32 final_handler[64];
761 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
762 * 2. A timing hazard exists for the TLBP instruction.
764 * stalling_instruction
767 * The JTLB is being read for the TLBP throughout the stall generated by the
768 * previous instruction. This is not really correct as the stalling instruction
769 * can modify the address used to access the JTLB. The failure symptom is that
770 * the TLBP instruction will use an address created for the stalling instruction
771 * and not the address held in C0_ENHI and thus report the wrong results.
773 * The software work-around is to not allow the instruction preceding the TLBP
774 * to stall - make it an NOP or some other instruction guaranteed not to stall.
776 * Errata 2 will not be fixed. This errata is also on the R5000.
778 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
780 static __init void __attribute__((unused)) build_tlb_probe_entry(u32 **p)
782 switch (current_cpu_data.cputype) {
797 * Write random or indexed TLB entry, and care about the hazards from
798 * the preceeding mtc0 and for the following eret.
800 enum tlb_write_entry { tlb_random, tlb_indexed };
802 static __init void build_tlb_write_entry(u32 **p, struct label **l,
804 enum tlb_write_entry wmode)
806 void(*tlbw)(u32 **) = NULL;
809 case tlb_random: tlbw = i_tlbwr; break;
810 case tlb_indexed: tlbw = i_tlbwi; break;
813 switch (current_cpu_data.cputype) {
821 * This branch uses up a mtc0 hazard nop slot and saves
822 * two nops after the tlbw instruction.
824 il_bgezl(p, r, 0, label_tlbw_hazard);
826 l_tlbw_hazard(l, *p);
862 i_nop(p); /* QED specifies 2 nops hazard */
864 * This branch uses up a mtc0 hazard nop slot and saves
865 * a nop after the tlbw instruction.
867 il_bgezl(p, r, 0, label_tlbw_hazard);
869 l_tlbw_hazard(l, *p);
888 * When the JTLB is updated by tlbwi or tlbwr, a subsequent
889 * use of the JTLB for instructions should not occur for 4
890 * cpu cycles and use for data translations should not occur
924 panic("No TLB refill handler yet (CPU type: %d)",
925 current_cpu_data.cputype);
932 * TMP and PTR are scratch.
933 * TMP will be clobbered, PTR will hold the pmd entry.
936 build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
937 unsigned int tmp, unsigned int ptr)
939 long pgdc = (long)pgd_current;
942 * The vmalloc handling is not in the hotpath.
944 i_dmfc0(p, tmp, C0_BADVADDR);
945 il_bltz(p, r, tmp, label_vmalloc);
946 /* No i_nop needed here, since the next insn doesn't touch TMP. */
949 # ifdef CONFIG_BUILD_ELF64
951 * 64 bit SMP running in XKPHYS has smp_processor_id() << 3
954 i_dmfc0(p, ptr, C0_CONTEXT);
955 i_dsrl(p, ptr, ptr, 23);
956 i_LA_mostly(p, tmp, pgdc);
957 i_daddu(p, ptr, ptr, tmp);
958 i_dmfc0(p, tmp, C0_BADVADDR);
959 i_ld(p, ptr, rel_lo(pgdc), ptr);
962 * 64 bit SMP running in compat space has the lower part of
963 * &pgd_current[smp_processor_id()] stored in CONTEXT.
965 if (!in_compat_space_p(pgdc))
966 panic("Invalid page directory address!");
968 i_dmfc0(p, ptr, C0_CONTEXT);
969 i_dsra(p, ptr, ptr, 23);
970 i_ld(p, ptr, 0, ptr);
973 i_LA_mostly(p, ptr, pgdc);
974 i_ld(p, ptr, rel_lo(pgdc), ptr);
977 l_vmalloc_done(l, *p);
978 i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); /* get pgd offset in bytes */
979 i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
980 i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
981 i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
982 i_ld(p, ptr, 0, ptr); /* get pmd pointer */
983 i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
984 i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
985 i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
989 * BVADDR is the faulting address, PTR is scratch.
990 * PTR will hold the pgd for vmalloc.
993 build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
994 unsigned int bvaddr, unsigned int ptr)
996 long swpd = (long)swapper_pg_dir;
999 i_LA(p, ptr, VMALLOC_START);
1000 i_dsubu(p, bvaddr, bvaddr, ptr);
1002 if (in_compat_space_p(swpd) && !rel_lo(swpd)) {
1003 il_b(p, r, label_vmalloc_done);
1004 i_lui(p, ptr, rel_hi(swpd));
1006 i_LA_mostly(p, ptr, swpd);
1007 il_b(p, r, label_vmalloc_done);
1008 i_daddiu(p, ptr, ptr, rel_lo(swpd));
1012 #else /* !CONFIG_64BIT */
1015 * TMP and PTR are scratch.
1016 * TMP will be clobbered, PTR will hold the pgd entry.
1018 static __init void __attribute__((unused))
1019 build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
1021 long pgdc = (long)pgd_current;
1023 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
1025 i_mfc0(p, ptr, C0_CONTEXT);
1026 i_LA_mostly(p, tmp, pgdc);
1027 i_srl(p, ptr, ptr, 23);
1028 i_addu(p, ptr, tmp, ptr);
1030 i_LA_mostly(p, ptr, pgdc);
1032 i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
1033 i_lw(p, ptr, rel_lo(pgdc), ptr);
1034 i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
1035 i_sll(p, tmp, tmp, PGD_T_LOG2);
1036 i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
1039 #endif /* !CONFIG_64BIT */
1041 static __init void build_adjust_context(u32 **p, unsigned int ctx)
1043 unsigned int shift = 4 - (PTE_T_LOG2 + 1);
1044 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
1046 switch (current_cpu_data.cputype) {
1063 i_SRL(p, ctx, ctx, shift);
1064 i_andi(p, ctx, ctx, mask);
1067 static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1070 * Bug workaround for the Nevada. It seems as if under certain
1071 * circumstances the move from cp0_context might produce a
1072 * bogus result when the mfc0 instruction and its consumer are
1073 * in a different cacheline or a load instruction, probably any
1074 * memory reference, is between them.
1076 switch (current_cpu_data.cputype) {
1078 i_LW(p, ptr, 0, ptr);
1079 GET_CONTEXT(p, tmp); /* get context reg */
1083 GET_CONTEXT(p, tmp); /* get context reg */
1084 i_LW(p, ptr, 0, ptr);
1088 build_adjust_context(p, tmp);
1089 i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1092 static __init void build_update_entries(u32 **p, unsigned int tmp,
1096 * 64bit address support (36bit on a 32bit CPU) in a 32bit
1097 * Kernel is a special case. Only a few CPUs use it.
1099 #ifdef CONFIG_64BIT_PHYS_ADDR
1100 if (cpu_has_64bits) {
1101 i_ld(p, tmp, 0, ptep); /* get even pte */
1102 i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1103 i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */
1104 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1105 i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */
1106 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1108 int pte_off_even = sizeof(pte_t) / 2;
1109 int pte_off_odd = pte_off_even + sizeof(pte_t);
1111 /* The pte entries are pre-shifted */
1112 i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
1113 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1114 i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
1115 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1118 i_LW(p, tmp, 0, ptep); /* get even pte */
1119 i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
1120 if (r45k_bvahwbug())
1121 build_tlb_probe_entry(p);
1122 i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */
1123 if (r4k_250MHZhwbug())
1124 i_mtc0(p, 0, C0_ENTRYLO0);
1125 i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
1126 i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */
1127 if (r45k_bvahwbug())
1128 i_mfc0(p, tmp, C0_INDEX);
1129 if (r4k_250MHZhwbug())
1130 i_mtc0(p, 0, C0_ENTRYLO1);
1131 i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
1135 static void __init build_r4000_tlb_refill_handler(void)
1137 u32 *p = tlb_handler;
1138 struct label *l = labels;
1139 struct reloc *r = relocs;
1141 unsigned int final_len;
1143 memset(tlb_handler, 0, sizeof(tlb_handler));
1144 memset(labels, 0, sizeof(labels));
1145 memset(relocs, 0, sizeof(relocs));
1146 memset(final_handler, 0, sizeof(final_handler));
1149 * create the plain linear handler
1151 if (bcm1250_m3_war()) {
1152 i_MFC0(&p, K0, C0_BADVADDR);
1153 i_MFC0(&p, K1, C0_ENTRYHI);
1154 i_xor(&p, K0, K0, K1);
1155 i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
1156 il_bnez(&p, &r, K0, label_leave);
1157 /* No need for i_nop */
1161 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1163 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1166 build_get_ptep(&p, K0, K1);
1167 build_update_entries(&p, K0, K1);
1168 build_tlb_write_entry(&p, &l, &r, tlb_random);
1170 i_eret(&p); /* return from trap */
1173 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1);
1177 * Overflow check: For the 64bit handler, we need at least one
1178 * free instruction slot for the wrap-around branch. In worst
1179 * case, if the intended insertion point is a delay slot, we
1180 * need three, with the the second nop'ed and the third being
1184 if ((p - tlb_handler) > 64)
1185 panic("TLB refill handler space exceeded");
1187 if (((p - tlb_handler) > 63)
1188 || (((p - tlb_handler) > 61)
1189 && insn_has_bdelay(relocs, tlb_handler + 29)))
1190 panic("TLB refill handler space exceeded");
1194 * Now fold the handler in the TLB refill handler space.
1198 /* Simplest case, just copy the handler. */
1199 copy_handler(relocs, labels, tlb_handler, p, f);
1200 final_len = p - tlb_handler;
1201 #else /* CONFIG_64BIT */
1202 f = final_handler + 32;
1203 if ((p - tlb_handler) <= 32) {
1204 /* Just copy the handler. */
1205 copy_handler(relocs, labels, tlb_handler, p, f);
1206 final_len = p - tlb_handler;
1208 u32 *split = tlb_handler + 30;
1211 * Find the split point.
1213 if (insn_has_bdelay(relocs, split - 1))
1216 /* Copy first part of the handler. */
1217 copy_handler(relocs, labels, tlb_handler, split, f);
1218 f += split - tlb_handler;
1220 /* Insert branch. */
1221 l_split(&l, final_handler);
1222 il_b(&f, &r, label_split);
1223 if (insn_has_bdelay(relocs, split))
1226 copy_handler(relocs, labels, split, split + 1, f);
1227 move_labels(labels, f, f + 1, -1);
1232 /* Copy the rest of the handler. */
1233 copy_handler(relocs, labels, split, p, final_handler);
1234 final_len = (f - (final_handler + 32)) + (p - split);
1236 #endif /* CONFIG_64BIT */
1238 resolve_relocs(relocs, labels);
1239 printk("Synthesized TLB refill handler (%u instructions).\n",
1251 f = final_handler + 32;
1252 #endif /* CONFIG_64BIT */
1253 for (i = 0; i < final_len; i++)
1254 printk("%08x\n", f[i]);
1258 memcpy((void *)CAC_BASE, final_handler, 0x100);
1259 flush_icache_range(CAC_BASE, CAC_BASE + 0x100);
1263 * TLB load/store/modify handlers.
1265 * Only the fastpath gets synthesized at runtime, the slowpath for
1266 * do_page_fault remains normal asm.
1268 extern void tlb_do_page_fault_0(void);
1269 extern void tlb_do_page_fault_1(void);
1271 #define __tlb_handler_align \
1272 __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT)))
1275 * 128 instructions for the fastpath handler is generous and should
1276 * never be exceeded.
1278 #define FASTPATH_SIZE 128
1280 u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE];
1281 u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE];
1282 u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE];
1285 iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr)
1288 # ifdef CONFIG_64BIT_PHYS_ADDR
1290 i_lld(p, pte, 0, ptr);
1293 i_LL(p, pte, 0, ptr);
1295 # ifdef CONFIG_64BIT_PHYS_ADDR
1297 i_ld(p, pte, 0, ptr);
1300 i_LW(p, pte, 0, ptr);
1305 iPTE_SW(u32 **p, struct reloc **r, unsigned int pte, unsigned int ptr,
1308 #ifdef CONFIG_64BIT_PHYS_ADDR
1309 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
1312 i_ori(p, pte, pte, mode);
1314 # ifdef CONFIG_64BIT_PHYS_ADDR
1316 i_scd(p, pte, 0, ptr);
1319 i_SC(p, pte, 0, ptr);
1321 if (r10000_llsc_war())
1322 il_beqzl(p, r, pte, label_smp_pgtable_change);
1324 il_beqz(p, r, pte, label_smp_pgtable_change);
1326 # ifdef CONFIG_64BIT_PHYS_ADDR
1327 if (!cpu_has_64bits) {
1328 /* no i_nop needed */
1329 i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1330 i_ori(p, pte, pte, hwmode);
1331 i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1332 il_beqz(p, r, pte, label_smp_pgtable_change);
1333 /* no i_nop needed */
1334 i_lw(p, pte, 0, ptr);
1341 # ifdef CONFIG_64BIT_PHYS_ADDR
1343 i_sd(p, pte, 0, ptr);
1346 i_SW(p, pte, 0, ptr);
1348 # ifdef CONFIG_64BIT_PHYS_ADDR
1349 if (!cpu_has_64bits) {
1350 i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1351 i_ori(p, pte, pte, hwmode);
1352 i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1353 i_lw(p, pte, 0, ptr);
1360 * Check if PTE is present, if not then jump to LABEL. PTR points to
1361 * the page table where this PTE is located, PTE will be re-loaded
1362 * with it's original value.
1365 build_pte_present(u32 **p, struct label **l, struct reloc **r,
1366 unsigned int pte, unsigned int ptr, enum label_id lid)
1368 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1369 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
1370 il_bnez(p, r, pte, lid);
1371 iPTE_LW(p, l, pte, ptr);
1374 /* Make PTE valid, store result in PTR. */
1376 build_make_valid(u32 **p, struct reloc **r, unsigned int pte,
1379 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1381 iPTE_SW(p, r, pte, ptr, mode);
1385 * Check if PTE can be written to, if not branch to LABEL. Regardless
1386 * restore PTE with value from PTR when done.
1389 build_pte_writable(u32 **p, struct label **l, struct reloc **r,
1390 unsigned int pte, unsigned int ptr, enum label_id lid)
1392 i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1393 i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
1394 il_bnez(p, r, pte, lid);
1395 iPTE_LW(p, l, pte, ptr);
1398 /* Make PTE writable, update software status bits as well, then store
1402 build_make_write(u32 **p, struct reloc **r, unsigned int pte,
1405 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1408 iPTE_SW(p, r, pte, ptr, mode);
1412 * Check if PTE can be modified, if not branch to LABEL. Regardless
1413 * restore PTE with value from PTR when done.
1416 build_pte_modifiable(u32 **p, struct label **l, struct reloc **r,
1417 unsigned int pte, unsigned int ptr, enum label_id lid)
1419 i_andi(p, pte, pte, _PAGE_WRITE);
1420 il_beqz(p, r, pte, lid);
1421 iPTE_LW(p, l, pte, ptr);
1425 * R3000 style TLB load/store/modify handlers.
1429 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1433 build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1435 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1436 i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1439 i_rfe(p); /* branch delay */
1443 * This places the pte into ENTRYLO0 and writes it with tlbwi
1444 * or tlbwr as appropriate. This is because the index register
1445 * may have the probe fail bit set as a result of a trap on a
1446 * kseg2 access, i.e. without refill. Then it returns.
1449 build_r3000_tlb_reload_write(u32 **p, struct label **l, struct reloc **r,
1450 unsigned int pte, unsigned int tmp)
1452 i_mfc0(p, tmp, C0_INDEX);
1453 i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1454 il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1455 i_mfc0(p, tmp, C0_EPC); /* branch delay */
1456 i_tlbwi(p); /* cp0 delay */
1458 i_rfe(p); /* branch delay */
1459 l_r3000_write_probe_fail(l, *p);
1460 i_tlbwr(p); /* cp0 delay */
1462 i_rfe(p); /* branch delay */
1466 build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1469 long pgdc = (long)pgd_current;
1471 i_mfc0(p, pte, C0_BADVADDR);
1472 i_lui(p, ptr, rel_hi(pgdc)); /* cp0 delay */
1473 i_lw(p, ptr, rel_lo(pgdc), ptr);
1474 i_srl(p, pte, pte, 22); /* load delay */
1475 i_sll(p, pte, pte, 2);
1476 i_addu(p, ptr, ptr, pte);
1477 i_mfc0(p, pte, C0_CONTEXT);
1478 i_lw(p, ptr, 0, ptr); /* cp0 delay */
1479 i_andi(p, pte, pte, 0xffc); /* load delay */
1480 i_addu(p, ptr, ptr, pte);
1481 i_lw(p, pte, 0, ptr);
1482 i_tlbp(p); /* load delay */
1485 static void __init build_r3000_tlb_load_handler(void)
1487 u32 *p = handle_tlbl;
1488 struct label *l = labels;
1489 struct reloc *r = relocs;
1491 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1492 memset(labels, 0, sizeof(labels));
1493 memset(relocs, 0, sizeof(relocs));
1495 build_r3000_tlbchange_handler_head(&p, K0, K1);
1496 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
1497 i_nop(&p); /* load delay */
1498 build_make_valid(&p, &r, K0, K1);
1499 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1501 l_nopage_tlbl(&l, p);
1502 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1505 if ((p - handle_tlbl) > FASTPATH_SIZE)
1506 panic("TLB load handler fastpath space exceeded");
1508 resolve_relocs(relocs, labels);
1509 printk("Synthesized TLB load handler fastpath (%u instructions).\n",
1510 (unsigned int)(p - handle_tlbl));
1516 for (i = 0; i < (p - handle_tlbl); i++)
1517 printk("%08x\n", handle_tlbl[i]);
1521 flush_icache_range((unsigned long)handle_tlbl,
1522 (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32));
1525 static void __init build_r3000_tlb_store_handler(void)
1527 u32 *p = handle_tlbs;
1528 struct label *l = labels;
1529 struct reloc *r = relocs;
1531 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1532 memset(labels, 0, sizeof(labels));
1533 memset(relocs, 0, sizeof(relocs));
1535 build_r3000_tlbchange_handler_head(&p, K0, K1);
1536 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
1537 i_nop(&p); /* load delay */
1538 build_make_write(&p, &r, K0, K1);
1539 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1541 l_nopage_tlbs(&l, p);
1542 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1545 if ((p - handle_tlbs) > FASTPATH_SIZE)
1546 panic("TLB store handler fastpath space exceeded");
1548 resolve_relocs(relocs, labels);
1549 printk("Synthesized TLB store handler fastpath (%u instructions).\n",
1550 (unsigned int)(p - handle_tlbs));
1556 for (i = 0; i < (p - handle_tlbs); i++)
1557 printk("%08x\n", handle_tlbs[i]);
1561 flush_icache_range((unsigned long)handle_tlbs,
1562 (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32));
1565 static void __init build_r3000_tlb_modify_handler(void)
1567 u32 *p = handle_tlbm;
1568 struct label *l = labels;
1569 struct reloc *r = relocs;
1571 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1572 memset(labels, 0, sizeof(labels));
1573 memset(relocs, 0, sizeof(relocs));
1575 build_r3000_tlbchange_handler_head(&p, K0, K1);
1576 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
1577 i_nop(&p); /* load delay */
1578 build_make_write(&p, &r, K0, K1);
1579 build_r3000_pte_reload_tlbwi(&p, K0, K1);
1581 l_nopage_tlbm(&l, p);
1582 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1585 if ((p - handle_tlbm) > FASTPATH_SIZE)
1586 panic("TLB modify handler fastpath space exceeded");
1588 resolve_relocs(relocs, labels);
1589 printk("Synthesized TLB modify handler fastpath (%u instructions).\n",
1590 (unsigned int)(p - handle_tlbm));
1596 for (i = 0; i < (p - handle_tlbm); i++)
1597 printk("%08x\n", handle_tlbm[i]);
1601 flush_icache_range((unsigned long)handle_tlbm,
1602 (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32));
1606 * R4000 style TLB load/store/modify handlers.
1609 build_r4000_tlbchange_handler_head(u32 **p, struct label **l,
1610 struct reloc **r, unsigned int pte,
1614 build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */
1616 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
1619 i_MFC0(p, pte, C0_BADVADDR);
1620 i_LW(p, ptr, 0, ptr);
1621 i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
1622 i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
1623 i_ADDU(p, ptr, ptr, pte);
1626 l_smp_pgtable_change(l, *p);
1628 iPTE_LW(p, l, pte, ptr); /* get even pte */
1629 build_tlb_probe_entry(p);
1633 build_r4000_tlbchange_handler_tail(u32 **p, struct label **l,
1634 struct reloc **r, unsigned int tmp,
1637 i_ori(p, ptr, ptr, sizeof(pte_t));
1638 i_xori(p, ptr, ptr, sizeof(pte_t));
1639 build_update_entries(p, tmp, ptr);
1640 build_tlb_write_entry(p, l, r, tlb_indexed);
1642 i_eret(p); /* return from trap */
1645 build_get_pgd_vmalloc64(p, l, r, tmp, ptr);
1649 static void __init build_r4000_tlb_load_handler(void)
1651 u32 *p = handle_tlbl;
1652 struct label *l = labels;
1653 struct reloc *r = relocs;
1655 memset(handle_tlbl, 0, sizeof(handle_tlbl));
1656 memset(labels, 0, sizeof(labels));
1657 memset(relocs, 0, sizeof(relocs));
1659 if (bcm1250_m3_war()) {
1660 i_MFC0(&p, K0, C0_BADVADDR);
1661 i_MFC0(&p, K1, C0_ENTRYHI);
1662 i_xor(&p, K0, K0, K1);
1663 i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
1664 il_bnez(&p, &r, K0, label_leave);
1665 /* No need for i_nop */
1668 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1669 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
1670 build_make_valid(&p, &r, K0, K1);
1671 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1673 l_nopage_tlbl(&l, p);
1674 i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1677 if ((p - handle_tlbl) > FASTPATH_SIZE)
1678 panic("TLB load handler fastpath space exceeded");
1680 resolve_relocs(relocs, labels);
1681 printk("Synthesized TLB load handler fastpath (%u instructions).\n",
1682 (unsigned int)(p - handle_tlbl));
1688 for (i = 0; i < (p - handle_tlbl); i++)
1689 printk("%08x\n", handle_tlbl[i]);
1693 flush_icache_range((unsigned long)handle_tlbl,
1694 (unsigned long)handle_tlbl + FASTPATH_SIZE * sizeof(u32));
1697 static void __init build_r4000_tlb_store_handler(void)
1699 u32 *p = handle_tlbs;
1700 struct label *l = labels;
1701 struct reloc *r = relocs;
1703 memset(handle_tlbs, 0, sizeof(handle_tlbs));
1704 memset(labels, 0, sizeof(labels));
1705 memset(relocs, 0, sizeof(relocs));
1707 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1708 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
1709 build_make_write(&p, &r, K0, K1);
1710 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1712 l_nopage_tlbs(&l, p);
1713 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1716 if ((p - handle_tlbs) > FASTPATH_SIZE)
1717 panic("TLB store handler fastpath space exceeded");
1719 resolve_relocs(relocs, labels);
1720 printk("Synthesized TLB store handler fastpath (%u instructions).\n",
1721 (unsigned int)(p - handle_tlbs));
1727 for (i = 0; i < (p - handle_tlbs); i++)
1728 printk("%08x\n", handle_tlbs[i]);
1732 flush_icache_range((unsigned long)handle_tlbs,
1733 (unsigned long)handle_tlbs + FASTPATH_SIZE * sizeof(u32));
1736 static void __init build_r4000_tlb_modify_handler(void)
1738 u32 *p = handle_tlbm;
1739 struct label *l = labels;
1740 struct reloc *r = relocs;
1742 memset(handle_tlbm, 0, sizeof(handle_tlbm));
1743 memset(labels, 0, sizeof(labels));
1744 memset(relocs, 0, sizeof(relocs));
1746 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1747 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
1748 /* Present and writable bits set, set accessed and dirty bits. */
1749 build_make_write(&p, &r, K0, K1);
1750 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1752 l_nopage_tlbm(&l, p);
1753 i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1756 if ((p - handle_tlbm) > FASTPATH_SIZE)
1757 panic("TLB modify handler fastpath space exceeded");
1759 resolve_relocs(relocs, labels);
1760 printk("Synthesized TLB modify handler fastpath (%u instructions).\n",
1761 (unsigned int)(p - handle_tlbm));
1767 for (i = 0; i < (p - handle_tlbm); i++)
1768 printk("%08x\n", handle_tlbm[i]);
1772 flush_icache_range((unsigned long)handle_tlbm,
1773 (unsigned long)handle_tlbm + FASTPATH_SIZE * sizeof(u32));
1776 void __init build_tlb_refill_handler(void)
1779 * The refill handler is generated per-CPU, multi-node systems
1780 * may have local storage for it. The other handlers are only
1783 static int run_once = 0;
1785 switch (current_cpu_data.cputype) {
1793 build_r3000_tlb_refill_handler();
1795 build_r3000_tlb_load_handler();
1796 build_r3000_tlb_store_handler();
1797 build_r3000_tlb_modify_handler();
1804 panic("No R6000 TLB refill handler yet");
1808 panic("No R8000 TLB refill handler yet");
1812 build_r4000_tlb_refill_handler();
1814 build_r4000_tlb_load_handler();
1815 build_r4000_tlb_store_handler();
1816 build_r4000_tlb_modify_handler();