2 * Copyright (C) 2006 Chris Dearman (chris@mips.com),
4 #include <linux/init.h>
5 #include <linux/kernel.h>
6 #include <linux/sched.h>
9 #include <asm/mipsregs.h>
10 #include <asm/bcache.h>
11 #include <asm/cacheops.h>
13 #include <asm/pgtable.h>
14 #include <asm/system.h>
15 #include <asm/mmu_context.h>
16 #include <asm/r4kcache.h>
19 * MIPS32/MIPS64 L2 cache handling
23 * Writeback and invalidate the secondary cache before DMA.
25 static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
27 unsigned long sc_lsize = cpu_scache_line_size();
30 pr_debug("mips_sc_wback_inv[%08lx,%08lx]", addr, size);
32 /* Catch bad driver code */
35 a = addr & ~(sc_lsize - 1);
36 end = (addr + size - 1) & ~(sc_lsize - 1);
38 flush_scache_line(a); /* Hit_Writeback_Inv_SD */
46 * Invalidate the secondary cache before DMA.
48 static void mips_sc_inv(unsigned long addr, unsigned long size)
50 unsigned long sc_lsize = cpu_scache_line_size();
53 pr_debug("mips_sc_inv[%08lx,%08lx]", addr, size);
55 /* Catch bad driver code */
58 a = addr & ~(sc_lsize - 1);
59 end = (addr + size - 1) & ~(sc_lsize - 1);
61 invalidate_scache_line(a); /* Hit_Invalidate_SD */
68 static void mips_sc_enable(void)
70 /* L2 cache is permanently enabled */
73 static void mips_sc_disable(void)
75 /* L2 cache is permanently enabled */
78 static struct bcache_ops mips_sc_ops = {
79 .bc_enable = mips_sc_enable,
80 .bc_disable = mips_sc_disable,
81 .bc_wback_inv = mips_sc_wback_inv,
85 static inline int __init mips_sc_probe(void)
87 struct cpuinfo_mips *c = ¤t_cpu_data;
88 unsigned int config1, config2;
91 /* Mark as not present until probe completed */
92 c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
94 /* Ignore anything but MIPSxx processors */
95 if (c->isa_level != MIPS_CPU_ISA_M32R1 &&
96 c->isa_level != MIPS_CPU_ISA_M32R2 &&
97 c->isa_level != MIPS_CPU_ISA_M64R1 &&
98 c->isa_level != MIPS_CPU_ISA_M64R2)
101 /* Does this MIPS32/MIPS64 CPU have a config2 register? */
102 config1 = read_c0_config1();
103 if (!(config1 & MIPS_CONF_M))
106 config2 = read_c0_config2();
107 tmp = (config2 >> 4) & 0x0f;
108 if (0 < tmp && tmp <= 7)
109 c->scache.linesz = 2 << tmp;
113 tmp = (config2 >> 8) & 0x0f;
114 if (0 <= tmp && tmp <= 7)
115 c->scache.sets = 64 << tmp;
119 tmp = (config2 >> 0) & 0x0f;
120 if (0 <= tmp && tmp <= 7)
121 c->scache.ways = tmp + 1;
125 c->scache.waysize = c->scache.sets * c->scache.linesz;
127 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
132 int __init mips_sc_init(void)
134 int found = mips_sc_probe ();
137 bcops = &mips_sc_ops;