arch/mips/mm/c-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
   7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/hardirq.h>
  11 #include <linux/init.h>
  12 #include <linux/highmem.h>
  13 #include <linux/kernel.h>
  14 #include <linux/linkage.h>
  15 #include <linux/sched.h>
  16 #include <linux/smp.h>
  17 #include <linux/mm.h>
  18 #include <linux/module.h>
  19 #include <linux/bitops.h>
  20
  21 #include <asm/bcache.h>
  22 #include <asm/bootinfo.h>
  23 #include <asm/cache.h>
  24 #include <asm/cacheops.h>
  25 #include <asm/cpu.h>
  26 #include <asm/cpu-features.h>
  27 #include <asm/io.h>
  28 #include <asm/page.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/r4kcache.h>
  31 #include <asm/sections.h>
  32 #include <asm/system.h>
  33 #include <asm/mmu_context.h>
  34 #include <asm/war.h>
  35 #include <asm/cacheflush.h> /* for run_uncached() */
  36
  37
  38 /*
  39  * Special Variant of smp_call_function for use by cache functions:
  40  *
  41  *  o No return value
  42  *  o collapses to normal function call on UP kernels
  43  *  o collapses to normal function call on systems with a single shared
  44  *    primary cache.
  45  *  o doesn't disable interrupts on the local CPU
  46  */
  47 static inline void r4k_on_each_cpu(void (*func) (void *info), void *info,
  48                                    int wait)
  49 {
  50         preempt_disable();
  51
  52 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
  53         smp_call_function(func, info, wait);
  54 #endif
  55         func(info);
  56         preempt_enable();
  57 }
  58
  59 #if defined(CONFIG_MIPS_CMP)
  60 #define cpu_has_safe_index_cacheops 0
  61 #else
  62 #define cpu_has_safe_index_cacheops 1
  63 #endif
  64
  65 /*
  66  * Must die.
  67  */
  68 static unsigned long icache_size __read_mostly;
  69 static unsigned long dcache_size __read_mostly;
  70 static unsigned long scache_size __read_mostly;
  71
  72 /*
  73  * Dummy cache handling routines for machines without boardcaches
  74  */
  75 static void cache_noop(void) {}
  76
  77 static struct bcache_ops no_sc_ops = {
  78         .bc_enable = (void *)cache_noop,
  79         .bc_disable = (void *)cache_noop,
  80         .bc_wback_inv = (void *)cache_noop,
  81         .bc_inv = (void *)cache_noop
  82 };
  83
  84 struct bcache_ops *bcops = &no_sc_ops;
  85
  86 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002010)
  87 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002020)
  88
  89 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
  90 do {                                                                    \
  91         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
  92                 *(volatile unsigned long *)CKSEG1;                      \
  93         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
  94                 __asm__ __volatile__("nop;nop;nop;nop");                \
  95 } while (0)
  96
  97 static void (*r4k_blast_dcache_page)(unsigned long addr);
  98
  99 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
 100 {
 101         R4600_HIT_CACHEOP_WAR_IMPL;
 102         blast_dcache32_page(addr);
 103 }
 104
 105 static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
 106 {
 107         R4600_HIT_CACHEOP_WAR_IMPL;
 108         blast_dcache64_page(addr);
 109 }
 110
 111 static void __cpuinit r4k_blast_dcache_page_setup(void)
 112 {
 113         unsigned long  dc_lsize = cpu_dcache_line_size();
 114
 115         if (dc_lsize == 0)
 116                 r4k_blast_dcache_page = (void *)cache_noop;
 117         else if (dc_lsize == 16)
 118                 r4k_blast_dcache_page = blast_dcache16_page;
 119         else if (dc_lsize == 32)
 120                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
 121         else if (dc_lsize == 64)
 122                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
 123 }
 124
 125 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
 126
 127 static void __cpuinit r4k_blast_dcache_page_indexed_setup(void)
 128 {
 129         unsigned long dc_lsize = cpu_dcache_line_size();
 130
 131         if (dc_lsize == 0)
 132                 r4k_blast_dcache_page_indexed = (void *)cache_noop;
 133         else if (dc_lsize == 16)
 134                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
 135         else if (dc_lsize == 32)
 136                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
 137         else if (dc_lsize == 64)
 138                 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
 139 }
 140
 141 static void (* r4k_blast_dcache)(void);
 142
 143 static void __cpuinit r4k_blast_dcache_setup(void)
 144 {
 145         unsigned long dc_lsize = cpu_dcache_line_size();
 146
 147         if (dc_lsize == 0)
 148                 r4k_blast_dcache = (void *)cache_noop;
 149         else if (dc_lsize == 16)
 150                 r4k_blast_dcache = blast_dcache16;
 151         else if (dc_lsize == 32)
 152                 r4k_blast_dcache = blast_dcache32;
 153         else if (dc_lsize == 64)
 154                 r4k_blast_dcache = blast_dcache64;
 155 }
 156
 157 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
 158 #define JUMP_TO_ALIGN(order) \
 159         __asm__ __volatile__( \
 160                 "b\t1f\n\t" \
 161                 ".align\t" #order "\n\t" \
 162                 "1:\n\t" \
 163                 )
 164 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
 165 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
 166
 167 static inline void blast_r4600_v1_icache32(void)
 168 {
 169         unsigned long flags;
 170
 171         local_irq_save(flags);
 172         blast_icache32();
 173         local_irq_restore(flags);
 174 }
 175
 176 static inline void tx49_blast_icache32(void)
 177 {
 178         unsigned long start = INDEX_BASE;
 179         unsigned long end = start + current_cpu_data.icache.waysize;
 180         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 181         unsigned long ws_end = current_cpu_data.icache.ways <<
 182                                current_cpu_data.icache.waybit;
 183         unsigned long ws, addr;
 184
 185         CACHE32_UNROLL32_ALIGN2;
 186         /* I'm in even chunk.  blast odd chunks */
 187         for (ws = 0; ws < ws_end; ws += ws_inc)
 188                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 189                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 190         CACHE32_UNROLL32_ALIGN;
 191         /* I'm in odd chunk.  blast even chunks */
 192         for (ws = 0; ws < ws_end; ws += ws_inc)
 193                 for (addr = start; addr < end; addr += 0x400 * 2)
 194                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 195 }
 196
 197 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 198 {
 199         unsigned long flags;
 200
 201         local_irq_save(flags);
 202         blast_icache32_page_indexed(page);
 203         local_irq_restore(flags);
 204 }
 205
 206 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 207 {
 208         unsigned long indexmask = current_cpu_data.icache.waysize - 1;
 209         unsigned long start = INDEX_BASE + (page & indexmask);
 210         unsigned long end = start + PAGE_SIZE;
 211         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 212         unsigned long ws_end = current_cpu_data.icache.ways <<
 213                                current_cpu_data.icache.waybit;
 214         unsigned long ws, addr;
 215
 216         CACHE32_UNROLL32_ALIGN2;
 217         /* I'm in even chunk.  blast odd chunks */
 218         for (ws = 0; ws < ws_end; ws += ws_inc)
 219                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 220                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 221         CACHE32_UNROLL32_ALIGN;
 222         /* I'm in odd chunk.  blast even chunks */
 223         for (ws = 0; ws < ws_end; ws += ws_inc)
 224                 for (addr = start; addr < end; addr += 0x400 * 2)
 225                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 226 }
 227
 228 static void (* r4k_blast_icache_page)(unsigned long addr);
 229
 230 static void __cpuinit r4k_blast_icache_page_setup(void)
 231 {
 232         unsigned long ic_lsize = cpu_icache_line_size();
 233
 234         if (ic_lsize == 0)
 235                 r4k_blast_icache_page = (void *)cache_noop;
 236         else if (ic_lsize == 16)
 237                 r4k_blast_icache_page = blast_icache16_page;
 238         else if (ic_lsize == 32)
 239                 r4k_blast_icache_page = blast_icache32_page;
 240         else if (ic_lsize == 64)
 241                 r4k_blast_icache_page = blast_icache64_page;
 242 }
 243
 244
 245 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
 246
 247 static void __cpuinit r4k_blast_icache_page_indexed_setup(void)
 248 {
 249         unsigned long ic_lsize = cpu_icache_line_size();
 250
 251         if (ic_lsize == 0)
 252                 r4k_blast_icache_page_indexed = (void *)cache_noop;
 253         else if (ic_lsize == 16)
 254                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 255         else if (ic_lsize == 32) {
 256                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 257                         r4k_blast_icache_page_indexed =
 258                                 blast_icache32_r4600_v1_page_indexed;
 259                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 260                         r4k_blast_icache_page_indexed =
 261                                 tx49_blast_icache32_page_indexed;
 262                 else
 263                         r4k_blast_icache_page_indexed =
 264                                 blast_icache32_page_indexed;
 265         } else if (ic_lsize == 64)
 266                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
 267 }
 268
 269 static void (* r4k_blast_icache)(void);
 270
 271 static void __cpuinit r4k_blast_icache_setup(void)
 272 {
 273         unsigned long ic_lsize = cpu_icache_line_size();
 274
 275         if (ic_lsize == 0)
 276                 r4k_blast_icache = (void *)cache_noop;
 277         else if (ic_lsize == 16)
 278                 r4k_blast_icache = blast_icache16;
 279         else if (ic_lsize == 32) {
 280                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 281                         r4k_blast_icache = blast_r4600_v1_icache32;
 282                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 283                         r4k_blast_icache = tx49_blast_icache32;
 284                 else
 285                         r4k_blast_icache = blast_icache32;
 286         } else if (ic_lsize == 64)
 287                 r4k_blast_icache = blast_icache64;
 288 }
 289
 290 static void (* r4k_blast_scache_page)(unsigned long addr);
 291
 292 static void __cpuinit r4k_blast_scache_page_setup(void)
 293 {
 294         unsigned long sc_lsize = cpu_scache_line_size();
 295
 296         if (scache_size == 0)
 297                 r4k_blast_scache_page = (void *)cache_noop;
 298         else if (sc_lsize == 16)
 299                 r4k_blast_scache_page = blast_scache16_page;
 300         else if (sc_lsize == 32)
 301                 r4k_blast_scache_page = blast_scache32_page;
 302         else if (sc_lsize == 64)
 303                 r4k_blast_scache_page = blast_scache64_page;
 304         else if (sc_lsize == 128)
 305                 r4k_blast_scache_page = blast_scache128_page;
 306 }
 307
 308 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
 309
 310 static void __cpuinit r4k_blast_scache_page_indexed_setup(void)
 311 {
 312         unsigned long sc_lsize = cpu_scache_line_size();
 313
 314         if (scache_size == 0)
 315                 r4k_blast_scache_page_indexed = (void *)cache_noop;
 316         else if (sc_lsize == 16)
 317                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
 318         else if (sc_lsize == 32)
 319                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
 320         else if (sc_lsize == 64)
 321                 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
 322         else if (sc_lsize == 128)
 323                 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
 324 }
 325
 326 static void (* r4k_blast_scache)(void);
 327
 328 static void __cpuinit r4k_blast_scache_setup(void)
 329 {
 330         unsigned long sc_lsize = cpu_scache_line_size();
 331
 332         if (scache_size == 0)
 333                 r4k_blast_scache = (void *)cache_noop;
 334         else if (sc_lsize == 16)
 335                 r4k_blast_scache = blast_scache16;
 336         else if (sc_lsize == 32)
 337                 r4k_blast_scache = blast_scache32;
 338         else if (sc_lsize == 64)
 339                 r4k_blast_scache = blast_scache64;
 340         else if (sc_lsize == 128)
 341                 r4k_blast_scache = blast_scache128;
 342 }
 343
 344 static inline void local_r4k___flush_cache_all(void * args)
 345 {
 346 #if defined(CONFIG_CPU_LOONGSON2)
 347         r4k_blast_scache();
 348         return;
 349 #endif
 350         r4k_blast_dcache();
 351         r4k_blast_icache();
 352
 353         switch (current_cpu_type()) {
 354         case CPU_R4000SC:
 355         case CPU_R4000MC:
 356         case CPU_R4400SC:
 357         case CPU_R4400MC:
 358         case CPU_R10000:
 359         case CPU_R12000:
 360         case CPU_R14000:
 361                 r4k_blast_scache();
 362         }
 363 }
 364
 365 static void r4k___flush_cache_all(void)
 366 {
 367         r4k_on_each_cpu(local_r4k___flush_cache_all, NULL, 1);
 368 }
 369
 370 static inline int has_valid_asid(const struct mm_struct *mm)
 371 {
 372 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
 373         int i;
 374
 375         for_each_online_cpu(i)
 376                 if (cpu_context(i, mm))
 377                         return 1;
 378
 379         return 0;
 380 #else
 381         return cpu_context(smp_processor_id(), mm);
 382 #endif
 383 }
 384
 385 static void r4k__flush_cache_vmap(void)
 386 {
 387         r4k_blast_dcache();
 388 }
 389
 390 static void r4k__flush_cache_vunmap(void)
 391 {
 392         r4k_blast_dcache();
 393 }
 394
 395 static inline void local_r4k_flush_cache_range(void * args)
 396 {
 397         struct vm_area_struct *vma = args;
 398         int exec = vma->vm_flags & VM_EXEC;
 399
 400         if (!(has_valid_asid(vma->vm_mm)))
 401                 return;
 402
 403         r4k_blast_dcache();
 404         if (exec)
 405                 r4k_blast_icache();
 406 }
 407
 408 static void r4k_flush_cache_range(struct vm_area_struct *vma,
 409         unsigned long start, unsigned long end)
 410 {
 411         int exec = vma->vm_flags & VM_EXEC;
 412
 413         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
 414                 r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1);
 415 }
 416
 417 static inline void local_r4k_flush_cache_mm(void * args)
 418 {
 419         struct mm_struct *mm = args;
 420
 421         if (!has_valid_asid(mm))
 422                 return;
 423
 424         /*
 425          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
 426          * only flush the primary caches but R10000 and R12000 behave sane ...
 427          * R4000SC and R4400SC indexed S-cache ops also invalidate primary
 428          * caches, so we can bail out early.
 429          */
 430         if (current_cpu_type() == CPU_R4000SC ||
 431             current_cpu_type() == CPU_R4000MC ||
 432             current_cpu_type() == CPU_R4400SC ||
 433             current_cpu_type() == CPU_R4400MC) {
 434                 r4k_blast_scache();
 435                 return;
 436         }
 437
 438         r4k_blast_dcache();
 439 }
 440
 441 static void r4k_flush_cache_mm(struct mm_struct *mm)
 442 {
 443         if (!cpu_has_dc_aliases)
 444                 return;
 445
 446         r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1);
 447 }
 448
 449 struct flush_cache_page_args {
 450         struct vm_area_struct *vma;
 451         unsigned long addr;
 452         unsigned long pfn;
 453 };
 454
 455 static inline void local_r4k_flush_cache_page(void *args)
 456 {
 457         struct flush_cache_page_args *fcp_args = args;
 458         struct vm_area_struct *vma = fcp_args->vma;
 459         unsigned long addr = fcp_args->addr;
 460         struct page *page = pfn_to_page(fcp_args->pfn);
 461         int exec = vma->vm_flags & VM_EXEC;
 462         struct mm_struct *mm = vma->vm_mm;
 463         int map_coherent = 0;
 464         pgd_t *pgdp;
 465         pud_t *pudp;
 466         pmd_t *pmdp;
 467         pte_t *ptep;
 468         void *vaddr;
 469
 470         /*
 471          * If ownes no valid ASID yet, cannot possibly have gotten
 472          * this page into the cache.
 473          */
 474         if (!has_valid_asid(mm))
 475                 return;
 476
 477         addr &= PAGE_MASK;
 478         pgdp = pgd_offset(mm, addr);
 479         pudp = pud_offset(pgdp, addr);
 480         pmdp = pmd_offset(pudp, addr);
 481         ptep = pte_offset(pmdp, addr);
 482
 483         /*
 484          * If the page isn't marked valid, the page cannot possibly be
 485          * in the cache.
 486          */
 487         if (!(pte_present(*ptep)))
 488                 return;
 489
 490         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
 491                 vaddr = NULL;
 492         else {
 493                 /*
 494                  * Use kmap_coherent or kmap_atomic to do flushes for
 495                  * another ASID than the current one.
 496                  */
 497                 map_coherent = (cpu_has_dc_aliases &&
 498                                 page_mapped(page) && !Page_dcache_dirty(page));
 499                 if (map_coherent)
 500                         vaddr = kmap_coherent(page, addr);
 501                 else
 502                         vaddr = kmap_atomic(page, KM_USER0);
 503                 addr = (unsigned long)vaddr;
 504         }
 505
 506         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 507                 r4k_blast_dcache_page(addr);
 508                 if (exec && !cpu_icache_snoops_remote_store)
 509                         r4k_blast_scache_page(addr);
 510         }
 511         if (exec) {
 512                 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
 513                         int cpu = smp_processor_id();
 514
 515                         if (cpu_context(cpu, mm) != 0)
 516                                 drop_mmu_context(mm, cpu);
 517                 } else
 518                         r4k_blast_icache_page(addr);
 519         }
 520
 521         if (vaddr) {
 522                 if (map_coherent)
 523                         kunmap_coherent();
 524                 else
 525                         kunmap_atomic(vaddr, KM_USER0);
 526         }
 527 }
 528
 529 static void r4k_flush_cache_page(struct vm_area_struct *vma,
 530         unsigned long addr, unsigned long pfn)
 531 {
 532         struct flush_cache_page_args args;
 533
 534         args.vma = vma;
 535         args.addr = addr;
 536         args.pfn = pfn;
 537
 538         r4k_on_each_cpu(local_r4k_flush_cache_page, &args, 1);
 539 }
 540
 541 static inline void local_r4k_flush_data_cache_page(void * addr)
 542 {
 543         r4k_blast_dcache_page((unsigned long) addr);
 544 }
 545
 546 static void r4k_flush_data_cache_page(unsigned long addr)
 547 {
 548         if (in_atomic())
 549                 local_r4k_flush_data_cache_page((void *)addr);
 550         else
 551                 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr,
 552                                 1);
 553 }
 554
 555 struct flush_icache_range_args {
 556         unsigned long start;
 557         unsigned long end;
 558 };
 559
 560 static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)
 561 {
 562         if (!cpu_has_ic_fills_f_dc) {
 563                 if (end - start >= dcache_size) {
 564                         r4k_blast_dcache();
 565                 } else {
 566                         R4600_HIT_CACHEOP_WAR_IMPL;
 567                         protected_blast_dcache_range(start, end);
 568                 }
 569         }
 570
 571         if (end - start > icache_size)
 572                 r4k_blast_icache();
 573         else
 574                 protected_blast_icache_range(start, end);
 575 }
 576
 577 static inline void local_r4k_flush_icache_range_ipi(void *args)
 578 {
 579         struct flush_icache_range_args *fir_args = args;
 580         unsigned long start = fir_args->start;
 581         unsigned long end = fir_args->end;
 582
 583         local_r4k_flush_icache_range(start, end);
 584 }
 585
 586 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
 587 {
 588         struct flush_icache_range_args args;
 589
 590         args.start = start;
 591         args.end = end;
 592
 593         r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args, 1);
 594         instruction_hazard();
 595 }
 596
 597 #ifdef CONFIG_DMA_NONCOHERENT
 598
 599 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 600 {
 601         /* Catch bad driver code */
 602         BUG_ON(size == 0);
 603
 604         if (cpu_has_inclusive_pcaches) {
 605                 if (size >= scache_size)
 606                         r4k_blast_scache();
 607                 else
 608                         blast_scache_range(addr, addr + size);
 609                 return;
 610         }
 611
 612         /*
 613          * Either no secondary cache or the available caches don't have the
 614          * subset property so we have to flush the primary caches
 615          * explicitly
 616          */
 617         if (cpu_has_safe_index_cacheops && size >= dcache_size) {
 618                 r4k_blast_dcache();
 619         } else {
 620                 R4600_HIT_CACHEOP_WAR_IMPL;
 621                 blast_dcache_range(addr, addr + size);
 622         }
 623
 624         bc_wback_inv(addr, size);
 625 }
 626
 627 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 628 {
 629         /* Catch bad driver code */
 630         BUG_ON(size == 0);
 631
 632         if (cpu_has_inclusive_pcaches) {
 633                 if (size >= scache_size)
 634                         r4k_blast_scache();
 635                 else {
 636                         unsigned long lsize = cpu_scache_line_size();
 637                         unsigned long almask = ~(lsize - 1);
 638
 639                         /*
 640                          * There is no clearly documented alignment requirement
 641                          * for the cache instruction on MIPS processors and
 642                          * some processors, among them the RM5200 and RM7000
 643                          * QED processors will throw an address error for cache
 644                          * hit ops with insufficient alignment.  Solved by
 645                          * aligning the address to cache line size.
 646                          */
 647                         cache_op(Hit_Writeback_Inv_SD, addr & almask);
 648                         cache_op(Hit_Writeback_Inv_SD,
 649                                  (addr + size - 1) & almask);
 650                         blast_inv_scache_range(addr, addr + size);
 651                 }
 652                 return;
 653         }
 654
 655         if (cpu_has_safe_index_cacheops && size >= dcache_size) {
 656                 r4k_blast_dcache();
 657         } else {
 658                 unsigned long lsize = cpu_dcache_line_size();
 659                 unsigned long almask = ~(lsize - 1);
 660
 661                 R4600_HIT_CACHEOP_WAR_IMPL;
 662                 cache_op(Hit_Writeback_Inv_D, addr & almask);
 663                 cache_op(Hit_Writeback_Inv_D, (addr + size - 1)  & almask);
 664                 blast_inv_dcache_range(addr, addr + size);
 665         }
 666
 667         bc_inv(addr, size);
 668 }
 669 #endif /* CONFIG_DMA_NONCOHERENT */
 670
 671 /*
 672  * While we're protected against bad userland addresses we don't care
 673  * very much about what happens in that case.  Usually a segmentation
 674  * fault will dump the process later on anyway ...
 675  */
 676 static void local_r4k_flush_cache_sigtramp(void * arg)
 677 {
 678         unsigned long ic_lsize = cpu_icache_line_size();
 679         unsigned long dc_lsize = cpu_dcache_line_size();
 680         unsigned long sc_lsize = cpu_scache_line_size();
 681         unsigned long addr = (unsigned long) arg;
 682
 683         R4600_HIT_CACHEOP_WAR_IMPL;
 684         if (dc_lsize)
 685                 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
 686         if (!cpu_icache_snoops_remote_store && scache_size)
 687                 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
 688         if (ic_lsize)
 689                 protected_flush_icache_line(addr & ~(ic_lsize - 1));
 690         if (MIPS4K_ICACHE_REFILL_WAR) {
 691                 __asm__ __volatile__ (
 692                         ".set push\n\t"
 693                         ".set noat\n\t"
 694                         ".set mips3\n\t"
 695 #ifdef CONFIG_32BIT
 696                         "la     $at,1f\n\t"
 697 #endif
 698 #ifdef CONFIG_64BIT
 699                         "dla    $at,1f\n\t"
 700 #endif
 701                         "cache  %0,($at)\n\t"
 702                         "nop; nop; nop\n"
 703                         "1:\n\t"
 704                         ".set pop"
 705                         :
 706                         : "i" (Hit_Invalidate_I));
 707         }
 708         if (MIPS_CACHE_SYNC_WAR)
 709                 __asm__ __volatile__ ("sync");
 710 }
 711
 712 static void r4k_flush_cache_sigtramp(unsigned long addr)
 713 {
 714         r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr, 1);
 715 }
 716
 717 static void r4k_flush_icache_all(void)
 718 {
 719         if (cpu_has_vtag_icache)
 720                 r4k_blast_icache();
 721 }
 722
 723 static inline void rm7k_erratum31(void)
 724 {
 725         const unsigned long ic_lsize = 32;
 726         unsigned long addr;
 727
 728         /* RM7000 erratum #31. The icache is screwed at startup. */
 729         write_c0_taglo(0);
 730         write_c0_taghi(0);
 731
 732         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
 733                 __asm__ __volatile__ (
 734                         ".set push\n\t"
 735                         ".set noreorder\n\t"
 736                         ".set mips3\n\t"
 737                         "cache\t%1, 0(%0)\n\t"
 738                         "cache\t%1, 0x1000(%0)\n\t"
 739                         "cache\t%1, 0x2000(%0)\n\t"
 740                         "cache\t%1, 0x3000(%0)\n\t"
 741                         "cache\t%2, 0(%0)\n\t"
 742                         "cache\t%2, 0x1000(%0)\n\t"
 743                         "cache\t%2, 0x2000(%0)\n\t"
 744                         "cache\t%2, 0x3000(%0)\n\t"
 745                         "cache\t%1, 0(%0)\n\t"
 746                         "cache\t%1, 0x1000(%0)\n\t"
 747                         "cache\t%1, 0x2000(%0)\n\t"
 748                         "cache\t%1, 0x3000(%0)\n\t"
 749                         ".set pop\n"
 750                         :
 751                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
 752         }
 753 }
 754
 755 static char *way_string[] __cpuinitdata = { NULL, "direct mapped", "2-way",
 756         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
 757 };
 758
 759 static void __cpuinit probe_pcache(void)
 760 {
 761         struct cpuinfo_mips *c = &current_cpu_data;
 762         unsigned int config = read_c0_config();
 763         unsigned int prid = read_c0_prid();
 764         unsigned long config1;
 765         unsigned int lsize;
 766
 767         switch (c->cputype) {
 768         case CPU_R4600:                 /* QED style two way caches? */
 769         case CPU_R4700:
 770         case CPU_R5000:
 771         case CPU_NEVADA:
 772                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 773                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 774                 c->icache.ways = 2;
 775                 c->icache.waybit = __ffs(icache_size/2);
 776
 777                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 778                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 779                 c->dcache.ways = 2;
 780                 c->dcache.waybit= __ffs(dcache_size/2);
 781
 782                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 783                 break;
 784
 785         case CPU_R5432:
 786         case CPU_R5500:
 787                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 788                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 789                 c->icache.ways = 2;
 790                 c->icache.waybit= 0;
 791
 792                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 793                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 794                 c->dcache.ways = 2;
 795                 c->dcache.waybit = 0;
 796
 797                 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
 798                 break;
 799
 800         case CPU_TX49XX:
 801                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 802                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 803                 c->icache.ways = 4;
 804                 c->icache.waybit= 0;
 805
 806                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 807                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 808                 c->dcache.ways = 4;
 809                 c->dcache.waybit = 0;
 810
 811                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 812                 c->options |= MIPS_CPU_PREFETCH;
 813                 break;
 814
 815         case CPU_R4000PC:
 816         case CPU_R4000SC:
 817         case CPU_R4000MC:
 818         case CPU_R4400PC:
 819         case CPU_R4400SC:
 820         case CPU_R4400MC:
 821         case CPU_R4300:
 822                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 823                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 824                 c->icache.ways = 1;
 825                 c->icache.waybit = 0;   /* doesn't matter */
 826
 827                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 828                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 829                 c->dcache.ways = 1;
 830                 c->dcache.waybit = 0;   /* does not matter */
 831
 832                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 833                 break;
 834
 835         case CPU_R10000:
 836         case CPU_R12000:
 837         case CPU_R14000:
 838                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
 839                 c->icache.linesz = 64;
 840                 c->icache.ways = 2;
 841                 c->icache.waybit = 0;
 842
 843                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
 844                 c->dcache.linesz = 32;
 845                 c->dcache.ways = 2;
 846                 c->dcache.waybit = 0;
 847
 848                 c->options |= MIPS_CPU_PREFETCH;
 849                 break;
 850
 851         case CPU_VR4133:
 852                 write_c0_config(config & ~VR41_CONF_P4K);
 853         case CPU_VR4131:
 854                 /* Workaround for cache instruction bug of VR4131 */
 855                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
 856                     c->processor_id == 0x0c82U) {
 857                         config |= 0x00400000U;
 858                         if (c->processor_id == 0x0c80U)
 859                                 config |= VR41_CONF_BP;
 860                         write_c0_config(config);
 861                 } else
 862                         c->options |= MIPS_CPU_CACHE_CDEX_P;
 863
 864                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 865                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 866                 c->icache.ways = 2;
 867                 c->icache.waybit = __ffs(icache_size/2);
 868
 869                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 870                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 871                 c->dcache.ways = 2;
 872                 c->dcache.waybit = __ffs(dcache_size/2);
 873                 break;
 874
 875         case CPU_VR41XX:
 876         case CPU_VR4111:
 877         case CPU_VR4121:
 878         case CPU_VR4122:
 879         case CPU_VR4181:
 880         case CPU_VR4181A:
 881                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 882                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 883                 c->icache.ways = 1;
 884                 c->icache.waybit = 0;   /* doesn't matter */
 885
 886                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 887                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 888                 c->dcache.ways = 1;
 889                 c->dcache.waybit = 0;   /* does not matter */
 890
 891                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 892                 break;
 893
 894         case CPU_RM7000:
 895                 rm7k_erratum31();
 896
 897         case CPU_RM9000:
 898                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 899                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 900                 c->icache.ways = 4;
 901                 c->icache.waybit = __ffs(icache_size / c->icache.ways);
 902
 903                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 904                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 905                 c->dcache.ways = 4;
 906                 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
 907
 908 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
 909                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 910 #endif
 911                 c->options |= MIPS_CPU_PREFETCH;
 912                 break;
 913
 914         case CPU_LOONGSON2:
 915                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 916                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 917                 if (prid & 0x3)
 918                         c->icache.ways = 4;
 919                 else
 920                         c->icache.ways = 2;
 921                 c->icache.waybit = 0;
 922
 923                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 924                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 925                 if (prid & 0x3)
 926                         c->dcache.ways = 4;
 927                 else
 928                         c->dcache.ways = 2;
 929                 c->dcache.waybit = 0;
 930                 break;
 931
 932         default:
 933                 if (!(config & MIPS_CONF_M))
 934                         panic("Don't know how to probe P-caches on this cpu.");
 935
 936                 /*
 937                  * So we seem to be a MIPS32 or MIPS64 CPU
 938                  * So let's probe the I-cache ...
 939                  */
 940                 config1 = read_c0_config1();
 941
 942                 if ((lsize = ((config1 >> 19) & 7)))
 943                         c->icache.linesz = 2 << lsize;
 944                 else
 945                         c->icache.linesz = lsize;
 946                 c->icache.sets = 64 << ((config1 >> 22) & 7);
 947                 c->icache.ways = 1 + ((config1 >> 16) & 7);
 948
 949                 icache_size = c->icache.sets *
 950                               c->icache.ways *
 951                               c->icache.linesz;
 952                 c->icache.waybit = __ffs(icache_size/c->icache.ways);
 953
 954                 if (config & 0x8)               /* VI bit */
 955                         c->icache.flags |= MIPS_CACHE_VTAG;
 956
 957                 /*
 958                  * Now probe the MIPS32 / MIPS64 data cache.
 959                  */
 960                 c->dcache.flags = 0;
 961
 962                 if ((lsize = ((config1 >> 10) & 7)))
 963                         c->dcache.linesz = 2 << lsize;
 964                 else
 965                         c->dcache.linesz= lsize;
 966                 c->dcache.sets = 64 << ((config1 >> 13) & 7);
 967                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
 968
 969                 dcache_size = c->dcache.sets *
 970                               c->dcache.ways *
 971                               c->dcache.linesz;
 972                 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
 973
 974                 c->options |= MIPS_CPU_PREFETCH;
 975                 break;
 976         }
 977
 978         /*
 979          * Processor configuration sanity check for the R4000SC erratum
 980          * #5.  With page sizes larger than 32kB there is no possibility
 981          * to get a VCE exception anymore so we don't care about this
 982          * misconfiguration.  The case is rather theoretical anyway;
 983          * presumably no vendor is shipping his hardware in the "bad"
 984          * configuration.
 985          */
 986         if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 &&
 987             !(config & CONF_SC) && c->icache.linesz != 16 &&
 988             PAGE_SIZE <= 0x8000)
 989                 panic("Improper R4000SC processor configuration detected");
 990
 991         /* compute a couple of other cache variables */
 992         c->icache.waysize = icache_size / c->icache.ways;
 993         c->dcache.waysize = dcache_size / c->dcache.ways;
 994
 995         c->icache.sets = c->icache.linesz ?
 996                 icache_size / (c->icache.linesz * c->icache.ways) : 0;
 997         c->dcache.sets = c->dcache.linesz ?
 998                 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
 999
1000         /*
1001          * R10000 and R12000 P-caches are odd in a positive way.  They're 32kB
1002          * 2-way virtually indexed so normally would suffer from aliases.  So
1003          * normally they'd suffer from aliases but magic in the hardware deals
1004          * with that for us so we don't need to take care ourselves.
1005          */
1006         switch (c->cputype) {
1007         case CPU_20KC:
1008         case CPU_25KF:
1009         case CPU_SB1:
1010         case CPU_SB1A:
1011                 c->dcache.flags |= MIPS_CACHE_PINDEX;
1012                 break;
1013
1014         case CPU_R10000:
1015         case CPU_R12000:
1016         case CPU_R14000:
1017                 break;
1018
1019         case CPU_24K:
1020         case CPU_34K:
1021         case CPU_74K:
1022         case CPU_1004K:
1023                 if ((read_c0_config7() & (1 << 16))) {
1024                         /* effectively physically indexed dcache,
1025                            thus no virtual aliases. */
1026                         c->dcache.flags |= MIPS_CACHE_PINDEX;
1027                         break;
1028                 }
1029         default:
1030                 if (c->dcache.waysize > PAGE_SIZE)
1031                         c->dcache.flags |= MIPS_CACHE_ALIASES;
1032         }
1033
1034         switch (c->cputype) {
1035         case CPU_20KC:
1036                 /*
1037                  * Some older 20Kc chips doesn't have the 'VI' bit in
1038                  * the config register.
1039                  */
1040                 c->icache.flags |= MIPS_CACHE_VTAG;
1041                 break;
1042
1043         case CPU_ALCHEMY:
1044                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1045                 break;
1046         }
1047
1048 #ifdef  CONFIG_CPU_LOONGSON2
1049         /*
1050          * LOONGSON2 has 4 way icache, but when using indexed cache op,
1051          * one op will act on all 4 ways
1052          */
1053         c->icache.ways = 1;
1054 #endif
1055
1056         printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1057                icache_size >> 10,
1058                c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1059                way_string[c->icache.ways], c->icache.linesz);
1060
1061         printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1062                dcache_size >> 10, way_string[c->dcache.ways],
1063                (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1064                (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1065                         "cache aliases" : "no aliases",
1066                c->dcache.linesz);
1067 }
1068
1069 /*
1070  * If you even _breathe_ on this function, look at the gcc output and make sure
1071  * it does not pop things on and off the stack for the cache sizing loop that
1072  * executes in KSEG1 space or else you will crash and burn badly.  You have
1073  * been warned.
1074  */
1075 static int __cpuinit probe_scache(void)
1076 {
1077         unsigned long flags, addr, begin, end, pow2;
1078         unsigned int config = read_c0_config();
1079         struct cpuinfo_mips *c = &current_cpu_data;
1080         int tmp;
1081
1082         if (config & CONF_SC)
1083                 return 0;
1084
1085         begin = (unsigned long) &_stext;
1086         begin &= ~((4 * 1024 * 1024) - 1);
1087         end = begin + (4 * 1024 * 1024);
1088
1089         /*
1090          * This is such a bitch, you'd think they would make it easy to do
1091          * this.  Away you daemons of stupidity!
1092          */
1093         local_irq_save(flags);
1094
1095         /* Fill each size-multiple cache line with a valid tag. */
1096         pow2 = (64 * 1024);
1097         for (addr = begin; addr < end; addr = (begin + pow2)) {
1098                 unsigned long *p = (unsigned long *) addr;
1099                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1100                 pow2 <<= 1;
1101         }
1102
1103         /* Load first line with zero (therefore invalid) tag. */
1104         write_c0_taglo(0);
1105         write_c0_taghi(0);
1106         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1107         cache_op(Index_Store_Tag_I, begin);
1108         cache_op(Index_Store_Tag_D, begin);
1109         cache_op(Index_Store_Tag_SD, begin);
1110
1111         /* Now search for the wrap around point. */
1112         pow2 = (128 * 1024);
1113         tmp = 0;
1114         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1115                 cache_op(Index_Load_Tag_SD, addr);
1116                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1117                 if (!read_c0_taglo())
1118                         break;
1119                 pow2 <<= 1;
1120         }
1121         local_irq_restore(flags);
1122         addr -= begin;
1123
1124         scache_size = addr;
1125         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1126         c->scache.ways = 1;
1127         c->dcache.waybit = 0;           /* does not matter */
1128
1129         return 1;
1130 }
1131
1132 #if defined(CONFIG_CPU_LOONGSON2)
1133 static void __init loongson2_sc_init(void)
1134 {
1135         struct cpuinfo_mips *c = &current_cpu_data;
1136
1137         scache_size = 512*1024;
1138         c->scache.linesz = 32;
1139         c->scache.ways = 4;
1140         c->scache.waybit = 0;
1141         c->scache.waysize = scache_size / (c->scache.ways);
1142         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1143         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1144                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1145
1146         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1147 }
1148 #endif
1149
1150 extern int r5k_sc_init(void);
1151 extern int rm7k_sc_init(void);
1152 extern int mips_sc_init(void);
1153
1154 static void __cpuinit setup_scache(void)
1155 {
1156         struct cpuinfo_mips *c = &current_cpu_data;
1157         unsigned int config = read_c0_config();
1158         int sc_present = 0;
1159
1160         /*
1161          * Do the probing thing on R4000SC and R4400SC processors.  Other
1162          * processors don't have a S-cache that would be relevant to the
1163          * Linux memory management.
1164          */
1165         switch (c->cputype) {
1166         case CPU_R4000SC:
1167         case CPU_R4000MC:
1168         case CPU_R4400SC:
1169         case CPU_R4400MC:
1170                 sc_present = run_uncached(probe_scache);
1171                 if (sc_present)
1172                         c->options |= MIPS_CPU_CACHE_CDEX_S;
1173                 break;
1174
1175         case CPU_R10000:
1176         case CPU_R12000:
1177         case CPU_R14000:
1178                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1179                 c->scache.linesz = 64 << ((config >> 13) & 1);
1180                 c->scache.ways = 2;
1181                 c->scache.waybit= 0;
1182                 sc_present = 1;
1183                 break;
1184
1185         case CPU_R5000:
1186         case CPU_NEVADA:
1187 #ifdef CONFIG_R5000_CPU_SCACHE
1188                 r5k_sc_init();
1189 #endif
1190                 return;
1191
1192         case CPU_RM7000:
1193         case CPU_RM9000:
1194 #ifdef CONFIG_RM7000_CPU_SCACHE
1195                 rm7k_sc_init();
1196 #endif
1197                 return;
1198
1199 #if defined(CONFIG_CPU_LOONGSON2)
1200         case CPU_LOONGSON2:
1201                 loongson2_sc_init();
1202                 return;
1203 #endif
1204
1205         default:
1206                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1207                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
1208                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
1209                     c->isa_level == MIPS_CPU_ISA_M64R2) {
1210 #ifdef CONFIG_MIPS_CPU_SCACHE
1211                         if (mips_sc_init ()) {
1212                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1213                                 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1214                                        scache_size >> 10,
1215                                        way_string[c->scache.ways], c->scache.linesz);
1216                         }
1217 #else
1218                         if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1219                                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1220 #endif
1221                         return;
1222                 }
1223                 sc_present = 0;
1224         }
1225
1226         if (!sc_present)
1227                 return;
1228
1229         /* compute a couple of other cache variables */
1230         c->scache.waysize = scache_size / c->scache.ways;
1231
1232         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1233
1234         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1235                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1236
1237         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1238 }
1239
1240 void au1x00_fixup_config_od(void)
1241 {
1242         /*
1243          * c0_config.od (bit 19) was write only (and read as 0)
1244          * on the early revisions of Alchemy SOCs.  It disables the bus
1245          * transaction overlapping and needs to be set to fix various errata.
1246          */
1247         switch (read_c0_prid()) {
1248         case 0x00030100: /* Au1000 DA */
1249         case 0x00030201: /* Au1000 HA */
1250         case 0x00030202: /* Au1000 HB */
1251         case 0x01030200: /* Au1500 AB */
1252         /*
1253          * Au1100 errata actually keeps silence about this bit, so we set it
1254          * just in case for those revisions that require it to be set according
1255          * to the (now gone) cpu table.
1256          */
1257         case 0x02030200: /* Au1100 AB */
1258         case 0x02030201: /* Au1100 BA */
1259         case 0x02030202: /* Au1100 BC */
1260                 set_c0_config(1 << 19);
1261                 break;
1262         }
1263 }
1264
1265 /* CP0 hazard avoidance. */
1266 #define NXP_BARRIER()                                                   \
1267          __asm__ __volatile__(                                          \
1268         ".set noreorder\n\t"                                            \
1269         "nop; nop; nop; nop; nop; nop;\n\t"                             \
1270         ".set reorder\n\t")
1271
1272 static void nxp_pr4450_fixup_config(void)
1273 {
1274         unsigned long config0;
1275
1276         config0 = read_c0_config();
1277
1278         /* clear all three cache coherency fields */
1279         config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1280         config0 |= (((_page_cachable_default >> _CACHE_SHIFT) <<  0) |
1281                     ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1282                     ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1283         write_c0_config(config0);
1284         NXP_BARRIER();
1285 }
1286
1287 static int __cpuinitdata cca = -1;
1288
1289 static int __init cca_setup(char *str)
1290 {
1291         get_option(&str, &cca);
1292
1293         return 1;
1294 }
1295
1296 __setup("cca=", cca_setup);
1297
1298 static void __cpuinit coherency_setup(void)
1299 {
1300         if (cca < 0 || cca > 7)
1301                 cca = read_c0_config() & CONF_CM_CMASK;
1302         _page_cachable_default = cca << _CACHE_SHIFT;
1303
1304         pr_debug("Using cache attribute %d\n", cca);
1305         change_c0_config(CONF_CM_CMASK, cca);
1306
1307         /*
1308          * c0_status.cu=0 specifies that updates by the sc instruction use
1309          * the coherency mode specified by the TLB; 1 means cachable
1310          * coherent update on write will be used.  Not all processors have
1311          * this bit and; some wire it to zero, others like Toshiba had the
1312          * silly idea of putting something else there ...
1313          */
1314         switch (current_cpu_type()) {
1315         case CPU_R4000PC:
1316         case CPU_R4000SC:
1317         case CPU_R4000MC:
1318         case CPU_R4400PC:
1319         case CPU_R4400SC:
1320         case CPU_R4400MC:
1321                 clear_c0_config(CONF_CU);
1322                 break;
1323         /*
1324          * We need to catch the early Alchemy SOCs with
1325          * the write-only co_config.od bit and set it back to one on:
1326          * Au1000 rev DA, HA, HB;  Au1100 AB, BA, BC, Au1500 AB
1327          */
1328         case CPU_ALCHEMY:
1329                 au1x00_fixup_config_od();
1330                 break;
1331
1332         case PRID_IMP_PR4450:
1333                 nxp_pr4450_fixup_config();
1334                 break;
1335         }
1336 }
1337
1338 #if defined(CONFIG_DMA_NONCOHERENT)
1339
1340 static int __cpuinitdata coherentio;
1341
1342 static int __init setcoherentio(char *str)
1343 {
1344         coherentio = 1;
1345
1346         return 1;
1347 }
1348
1349 __setup("coherentio", setcoherentio);
1350 #endif
1351
1352 void __cpuinit r4k_cache_init(void)
1353 {
1354         extern void build_clear_page(void);
1355         extern void build_copy_page(void);
1356         extern char __weak except_vec2_generic;
1357         extern char __weak except_vec2_sb1;
1358         struct cpuinfo_mips *c = &current_cpu_data;
1359
1360         switch (c->cputype) {
1361         case CPU_SB1:
1362         case CPU_SB1A:
1363                 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1364                 break;
1365
1366         default:
1367                 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1368                 break;
1369         }
1370
1371         probe_pcache();
1372         setup_scache();
1373
1374         r4k_blast_dcache_page_setup();
1375         r4k_blast_dcache_page_indexed_setup();
1376         r4k_blast_dcache_setup();
1377         r4k_blast_icache_page_setup();
1378         r4k_blast_icache_page_indexed_setup();
1379         r4k_blast_icache_setup();
1380         r4k_blast_scache_page_setup();
1381         r4k_blast_scache_page_indexed_setup();
1382         r4k_blast_scache_setup();
1383
1384         /*
1385          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1386          * This code supports virtually indexed processors and will be
1387          * unnecessarily inefficient on physically indexed processors.
1388          */
1389         if (c->dcache.linesz)
1390                 shm_align_mask = max_t( unsigned long,
1391                                         c->dcache.sets * c->dcache.linesz - 1,
1392                                         PAGE_SIZE - 1);
1393         else
1394                 shm_align_mask = PAGE_SIZE-1;
1395
1396         __flush_cache_vmap      = r4k__flush_cache_vmap;
1397         __flush_cache_vunmap    = r4k__flush_cache_vunmap;
1398
1399         flush_cache_all         = cache_noop;
1400         __flush_cache_all       = r4k___flush_cache_all;
1401         flush_cache_mm          = r4k_flush_cache_mm;
1402         flush_cache_page        = r4k_flush_cache_page;
1403         flush_cache_range       = r4k_flush_cache_range;
1404
1405         flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
1406         flush_icache_all        = r4k_flush_icache_all;
1407         local_flush_data_cache_page     = local_r4k_flush_data_cache_page;
1408         flush_data_cache_page   = r4k_flush_data_cache_page;
1409         flush_icache_range      = r4k_flush_icache_range;
1410         local_flush_icache_range        = local_r4k_flush_icache_range;
1411
1412 #if defined(CONFIG_DMA_NONCOHERENT)
1413         if (coherentio) {
1414                 _dma_cache_wback_inv    = (void *)cache_noop;
1415                 _dma_cache_wback        = (void *)cache_noop;
1416                 _dma_cache_inv          = (void *)cache_noop;
1417         } else {
1418                 _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1419                 _dma_cache_wback        = r4k_dma_cache_wback_inv;
1420                 _dma_cache_inv          = r4k_dma_cache_inv;
1421         }
1422 #endif
1423
1424         build_clear_page();
1425         build_copy_page();
1426 #if !defined(CONFIG_MIPS_CMP)
1427         local_r4k___flush_cache_all(NULL);
1428 #endif
1429         coherency_setup();
1430 }