arch/mips/math-emu/cp1emu.c

   1 /*
   2  * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
   3  *
   4  * MIPS floating point support
   5  * Copyright (C) 1994-2000 Algorithmics Ltd.
   6  *
   7  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
   8  * Copyright (C) 2000  MIPS Technologies, Inc.
   9  *
  10  *  This program is free software; you can distribute it and/or modify it
  11  *  under the terms of the GNU General Public License (Version 2) as
  12  *  published by the Free Software Foundation.
  13  *
  14  *  This program is distributed in the hope it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, write to the Free Software Foundation, Inc.,
  21  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  22  *
  23  * A complete emulator for MIPS coprocessor 1 instructions.  This is
  24  * required for #float(switch) or #float(trap), where it catches all
  25  * COP1 instructions via the "CoProcessor Unusable" exception.
  26  *
  27  * More surprisingly it is also required for #float(ieee), to help out
  28  * the hardware fpu at the boundaries of the IEEE-754 representation
  29  * (denormalised values, infinities, underflow, etc).  It is made
  30  * quite nasty because emulation of some non-COP1 instructions is
  31  * required, e.g. in branch delay slots.
  32  *
  33  * Note if you know that you won't have an fpu, then you'll get much
  34  * better performance by compiling with -msoft-float!
  35  */
  36 #include <linux/sched.h>
  37 #include <linux/module.h>
  38 #include <linux/debugfs.h>
  39 #include <linux/perf_event.h>
  40
  41 #include <asm/inst.h>
  42 #include <asm/bootinfo.h>
  43 #include <asm/processor.h>
  44 #include <asm/ptrace.h>
  45 #include <asm/signal.h>
  46 #include <asm/mipsregs.h>
  47 #include <asm/fpu_emulator.h>
  48 #include <asm/fpu.h>
  49 #include <asm/uaccess.h>
  50 #include <asm/branch.h>
  51
  52 #include "ieee754.h"
  53
  54 /* Strap kernel emulator for full MIPS IV emulation */
  55
  56 #ifdef __mips
  57 #undef __mips
  58 #endif
  59 #define __mips 4
  60
  61 /* Function which emulates a floating point instruction. */
  62
  63 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
  64         mips_instruction);
  65
  66 #if __mips >= 4 && __mips != 32
  67 static int fpux_emu(struct pt_regs *,
  68         struct mips_fpu_struct *, mips_instruction, void *__user *);
  69 #endif
  70
  71 /* Further private data for which no space exists in mips_fpu_struct */
  72
  73 #ifdef CONFIG_DEBUG_FS
  74 DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
  75 #endif
  76
  77 /* Control registers */
  78
  79 #define FPCREG_RID      0       /* $0  = revision id */
  80 #define FPCREG_CSR      31      /* $31 = csr */
  81
  82 /* Determine rounding mode from the RM bits of the FCSR */
  83 #define modeindex(v) ((v) & FPU_CSR_RM)
  84
  85 /* microMIPS bitfields */
  86 #define MM_POOL32A_MINOR_MASK   0x3f
  87 #define MM_POOL32A_MINOR_SHIFT  0x6
  88 #define MM_MIPS32_COND_FC       0x30
  89
  90 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
  91 static const unsigned char ieee_rm[4] = {
  92         [FPU_CSR_RN] = IEEE754_RN,
  93         [FPU_CSR_RZ] = IEEE754_RZ,
  94         [FPU_CSR_RU] = IEEE754_RU,
  95         [FPU_CSR_RD] = IEEE754_RD,
  96 };
  97 /* Convert IEEE library modes to Mips rounding mode (0..3). */
  98 static const unsigned char mips_rm[4] = {
  99         [IEEE754_RN] = FPU_CSR_RN,
 100         [IEEE754_RZ] = FPU_CSR_RZ,
 101         [IEEE754_RD] = FPU_CSR_RD,
 102         [IEEE754_RU] = FPU_CSR_RU,
 103 };
 104
 105 #if __mips >= 4
 106 /* convert condition code register number to csr bit */
 107 static const unsigned int fpucondbit[8] = {
 108         FPU_CSR_COND0,
 109         FPU_CSR_COND1,
 110         FPU_CSR_COND2,
 111         FPU_CSR_COND3,
 112         FPU_CSR_COND4,
 113         FPU_CSR_COND5,
 114         FPU_CSR_COND6,
 115         FPU_CSR_COND7
 116 };
 117 #endif
 118
 119 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
 120 static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
 121
 122 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
 123 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
 124 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
 125 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
 126 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
 127
 128 /*
 129  * This functions translates a 32-bit microMIPS instruction
 130  * into a 32-bit MIPS32 instruction. Returns 0 on success
 131  * and SIGILL otherwise.
 132  */
 133 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
 134 {
 135         union mips_instruction insn = *insn_ptr;
 136         union mips_instruction mips32_insn = insn;
 137         int func, fmt, op;
 138
 139         switch (insn.mm_i_format.opcode) {
 140         case mm_ldc132_op:
 141                 mips32_insn.mm_i_format.opcode = ldc1_op;
 142                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 143                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 144                 break;
 145         case mm_lwc132_op:
 146                 mips32_insn.mm_i_format.opcode = lwc1_op;
 147                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 148                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 149                 break;
 150         case mm_sdc132_op:
 151                 mips32_insn.mm_i_format.opcode = sdc1_op;
 152                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 153                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 154                 break;
 155         case mm_swc132_op:
 156                 mips32_insn.mm_i_format.opcode = swc1_op;
 157                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 158                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 159                 break;
 160         case mm_pool32i_op:
 161                 /* NOTE: offset is << by 1 if in microMIPS mode. */
 162                 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
 163                     (insn.mm_i_format.rt == mm_bc1t_op)) {
 164                         mips32_insn.fb_format.opcode = cop1_op;
 165                         mips32_insn.fb_format.bc = bc_op;
 166                         mips32_insn.fb_format.flag =
 167                                 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
 168                 } else
 169                         return SIGILL;
 170                 break;
 171         case mm_pool32f_op:
 172                 switch (insn.mm_fp0_format.func) {
 173                 case mm_32f_01_op:
 174                 case mm_32f_11_op:
 175                 case mm_32f_02_op:
 176                 case mm_32f_12_op:
 177                 case mm_32f_41_op:
 178                 case mm_32f_51_op:
 179                 case mm_32f_42_op:
 180                 case mm_32f_52_op:
 181                         op = insn.mm_fp0_format.func;
 182                         if (op == mm_32f_01_op)
 183                                 func = madd_s_op;
 184                         else if (op == mm_32f_11_op)
 185                                 func = madd_d_op;
 186                         else if (op == mm_32f_02_op)
 187                                 func = nmadd_s_op;
 188                         else if (op == mm_32f_12_op)
 189                                 func = nmadd_d_op;
 190                         else if (op == mm_32f_41_op)
 191                                 func = msub_s_op;
 192                         else if (op == mm_32f_51_op)
 193                                 func = msub_d_op;
 194                         else if (op == mm_32f_42_op)
 195                                 func = nmsub_s_op;
 196                         else
 197                                 func = nmsub_d_op;
 198                         mips32_insn.fp6_format.opcode = cop1x_op;
 199                         mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
 200                         mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
 201                         mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
 202                         mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
 203                         mips32_insn.fp6_format.func = func;
 204                         break;
 205                 case mm_32f_10_op:
 206                         func = -1;      /* Invalid */
 207                         op = insn.mm_fp5_format.op & 0x7;
 208                         if (op == mm_ldxc1_op)
 209                                 func = ldxc1_op;
 210                         else if (op == mm_sdxc1_op)
 211                                 func = sdxc1_op;
 212                         else if (op == mm_lwxc1_op)
 213                                 func = lwxc1_op;
 214                         else if (op == mm_swxc1_op)
 215                                 func = swxc1_op;
 216
 217                         if (func != -1) {
 218                                 mips32_insn.r_format.opcode = cop1x_op;
 219                                 mips32_insn.r_format.rs =
 220                                         insn.mm_fp5_format.base;
 221                                 mips32_insn.r_format.rt =
 222                                         insn.mm_fp5_format.index;
 223                                 mips32_insn.r_format.rd = 0;
 224                                 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
 225                                 mips32_insn.r_format.func = func;
 226                         } else
 227                                 return SIGILL;
 228                         break;
 229                 case mm_32f_40_op:
 230                         op = -1;        /* Invalid */
 231                         if (insn.mm_fp2_format.op == mm_fmovt_op)
 232                                 op = 1;
 233                         else if (insn.mm_fp2_format.op == mm_fmovf_op)
 234                                 op = 0;
 235                         if (op != -1) {
 236                                 mips32_insn.fp0_format.opcode = cop1_op;
 237                                 mips32_insn.fp0_format.fmt =
 238                                         sdps_format[insn.mm_fp2_format.fmt];
 239                                 mips32_insn.fp0_format.ft =
 240                                         (insn.mm_fp2_format.cc<<2) + op;
 241                                 mips32_insn.fp0_format.fs =
 242                                         insn.mm_fp2_format.fs;
 243                                 mips32_insn.fp0_format.fd =
 244                                         insn.mm_fp2_format.fd;
 245                                 mips32_insn.fp0_format.func = fmovc_op;
 246                         } else
 247                                 return SIGILL;
 248                         break;
 249                 case mm_32f_60_op:
 250                         func = -1;      /* Invalid */
 251                         if (insn.mm_fp0_format.op == mm_fadd_op)
 252                                 func = fadd_op;
 253                         else if (insn.mm_fp0_format.op == mm_fsub_op)
 254                                 func = fsub_op;
 255                         else if (insn.mm_fp0_format.op == mm_fmul_op)
 256                                 func = fmul_op;
 257                         else if (insn.mm_fp0_format.op == mm_fdiv_op)
 258                                 func = fdiv_op;
 259                         if (func != -1) {
 260                                 mips32_insn.fp0_format.opcode = cop1_op;
 261                                 mips32_insn.fp0_format.fmt =
 262                                         sdps_format[insn.mm_fp0_format.fmt];
 263                                 mips32_insn.fp0_format.ft =
 264                                         insn.mm_fp0_format.ft;
 265                                 mips32_insn.fp0_format.fs =
 266                                         insn.mm_fp0_format.fs;
 267                                 mips32_insn.fp0_format.fd =
 268                                         insn.mm_fp0_format.fd;
 269                                 mips32_insn.fp0_format.func = func;
 270                         } else
 271                                 return SIGILL;
 272                         break;
 273                 case mm_32f_70_op:
 274                         func = -1;      /* Invalid */
 275                         if (insn.mm_fp0_format.op == mm_fmovn_op)
 276                                 func = fmovn_op;
 277                         else if (insn.mm_fp0_format.op == mm_fmovz_op)
 278                                 func = fmovz_op;
 279                         if (func != -1) {
 280                                 mips32_insn.fp0_format.opcode = cop1_op;
 281                                 mips32_insn.fp0_format.fmt =
 282                                         sdps_format[insn.mm_fp0_format.fmt];
 283                                 mips32_insn.fp0_format.ft =
 284                                         insn.mm_fp0_format.ft;
 285                                 mips32_insn.fp0_format.fs =
 286                                         insn.mm_fp0_format.fs;
 287                                 mips32_insn.fp0_format.fd =
 288                                         insn.mm_fp0_format.fd;
 289                                 mips32_insn.fp0_format.func = func;
 290                         } else
 291                                 return SIGILL;
 292                         break;
 293                 case mm_32f_73_op:    /* POOL32FXF */
 294                         switch (insn.mm_fp1_format.op) {
 295                         case mm_movf0_op:
 296                         case mm_movf1_op:
 297                         case mm_movt0_op:
 298                         case mm_movt1_op:
 299                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 300                                     mm_movf0_op)
 301                                         op = 0;
 302                                 else
 303                                         op = 1;
 304                                 mips32_insn.r_format.opcode = spec_op;
 305                                 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
 306                                 mips32_insn.r_format.rt =
 307                                         (insn.mm_fp4_format.cc << 2) + op;
 308                                 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
 309                                 mips32_insn.r_format.re = 0;
 310                                 mips32_insn.r_format.func = movc_op;
 311                                 break;
 312                         case mm_fcvtd0_op:
 313                         case mm_fcvtd1_op:
 314                         case mm_fcvts0_op:
 315                         case mm_fcvts1_op:
 316                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 317                                     mm_fcvtd0_op) {
 318                                         func = fcvtd_op;
 319                                         fmt = swl_format[insn.mm_fp3_format.fmt];
 320                                 } else {
 321                                         func = fcvts_op;
 322                                         fmt = dwl_format[insn.mm_fp3_format.fmt];
 323                                 }
 324                                 mips32_insn.fp0_format.opcode = cop1_op;
 325                                 mips32_insn.fp0_format.fmt = fmt;
 326                                 mips32_insn.fp0_format.ft = 0;
 327                                 mips32_insn.fp0_format.fs =
 328                                         insn.mm_fp3_format.fs;
 329                                 mips32_insn.fp0_format.fd =
 330                                         insn.mm_fp3_format.rt;
 331                                 mips32_insn.fp0_format.func = func;
 332                                 break;
 333                         case mm_fmov0_op:
 334                         case mm_fmov1_op:
 335                         case mm_fabs0_op:
 336                         case mm_fabs1_op:
 337                         case mm_fneg0_op:
 338                         case mm_fneg1_op:
 339                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 340                                     mm_fmov0_op)
 341                                         func = fmov_op;
 342                                 else if ((insn.mm_fp1_format.op & 0x7f) ==
 343                                          mm_fabs0_op)
 344                                         func = fabs_op;
 345                                 else
 346                                         func = fneg_op;
 347                                 mips32_insn.fp0_format.opcode = cop1_op;
 348                                 mips32_insn.fp0_format.fmt =
 349                                         sdps_format[insn.mm_fp3_format.fmt];
 350                                 mips32_insn.fp0_format.ft = 0;
 351                                 mips32_insn.fp0_format.fs =
 352                                         insn.mm_fp3_format.fs;
 353                                 mips32_insn.fp0_format.fd =
 354                                         insn.mm_fp3_format.rt;
 355                                 mips32_insn.fp0_format.func = func;
 356                                 break;
 357                         case mm_ffloorl_op:
 358                         case mm_ffloorw_op:
 359                         case mm_fceill_op:
 360                         case mm_fceilw_op:
 361                         case mm_ftruncl_op:
 362                         case mm_ftruncw_op:
 363                         case mm_froundl_op:
 364                         case mm_froundw_op:
 365                         case mm_fcvtl_op:
 366                         case mm_fcvtw_op:
 367                                 if (insn.mm_fp1_format.op == mm_ffloorl_op)
 368                                         func = ffloorl_op;
 369                                 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
 370                                         func = ffloor_op;
 371                                 else if (insn.mm_fp1_format.op == mm_fceill_op)
 372                                         func = fceill_op;
 373                                 else if (insn.mm_fp1_format.op == mm_fceilw_op)
 374                                         func = fceil_op;
 375                                 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
 376                                         func = ftruncl_op;
 377                                 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
 378                                         func = ftrunc_op;
 379                                 else if (insn.mm_fp1_format.op == mm_froundl_op)
 380                                         func = froundl_op;
 381                                 else if (insn.mm_fp1_format.op == mm_froundw_op)
 382                                         func = fround_op;
 383                                 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
 384                                         func = fcvtl_op;
 385                                 else
 386                                         func = fcvtw_op;
 387                                 mips32_insn.fp0_format.opcode = cop1_op;
 388                                 mips32_insn.fp0_format.fmt =
 389                                         sd_format[insn.mm_fp1_format.fmt];
 390                                 mips32_insn.fp0_format.ft = 0;
 391                                 mips32_insn.fp0_format.fs =
 392                                         insn.mm_fp1_format.fs;
 393                                 mips32_insn.fp0_format.fd =
 394                                         insn.mm_fp1_format.rt;
 395                                 mips32_insn.fp0_format.func = func;
 396                                 break;
 397                         case mm_frsqrt_op:
 398                         case mm_fsqrt_op:
 399                         case mm_frecip_op:
 400                                 if (insn.mm_fp1_format.op == mm_frsqrt_op)
 401                                         func = frsqrt_op;
 402                                 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
 403                                         func = fsqrt_op;
 404                                 else
 405                                         func = frecip_op;
 406                                 mips32_insn.fp0_format.opcode = cop1_op;
 407                                 mips32_insn.fp0_format.fmt =
 408                                         sdps_format[insn.mm_fp1_format.fmt];
 409                                 mips32_insn.fp0_format.ft = 0;
 410                                 mips32_insn.fp0_format.fs =
 411                                         insn.mm_fp1_format.fs;
 412                                 mips32_insn.fp0_format.fd =
 413                                         insn.mm_fp1_format.rt;
 414                                 mips32_insn.fp0_format.func = func;
 415                                 break;
 416                         case mm_mfc1_op:
 417                         case mm_mtc1_op:
 418                         case mm_cfc1_op:
 419                         case mm_ctc1_op:
 420                                 if (insn.mm_fp1_format.op == mm_mfc1_op)
 421                                         op = mfc_op;
 422                                 else if (insn.mm_fp1_format.op == mm_mtc1_op)
 423                                         op = mtc_op;
 424                                 else if (insn.mm_fp1_format.op == mm_cfc1_op)
 425                                         op = cfc_op;
 426                                 else
 427                                         op = ctc_op;
 428                                 mips32_insn.fp1_format.opcode = cop1_op;
 429                                 mips32_insn.fp1_format.op = op;
 430                                 mips32_insn.fp1_format.rt =
 431                                         insn.mm_fp1_format.rt;
 432                                 mips32_insn.fp1_format.fs =
 433                                         insn.mm_fp1_format.fs;
 434                                 mips32_insn.fp1_format.fd = 0;
 435                                 mips32_insn.fp1_format.func = 0;
 436                                 break;
 437                         default:
 438                                 return SIGILL;
 439                                 break;
 440                         }
 441                         break;
 442                 case mm_32f_74_op:      /* c.cond.fmt */
 443                         mips32_insn.fp0_format.opcode = cop1_op;
 444                         mips32_insn.fp0_format.fmt =
 445                                 sdps_format[insn.mm_fp4_format.fmt];
 446                         mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
 447                         mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
 448                         mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
 449                         mips32_insn.fp0_format.func =
 450                                 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
 451                         break;
 452                 default:
 453                         return SIGILL;
 454                         break;
 455                 }
 456                 break;
 457         default:
 458                 return SIGILL;
 459                 break;
 460         }
 461
 462         *insn_ptr = mips32_insn;
 463         return 0;
 464 }
 465
 466 int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 467                      unsigned long *contpc)
 468 {
 469         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 470         int bc_false = 0;
 471         unsigned int fcr31;
 472         unsigned int bit;
 473
 474         if (!cpu_has_mmips)
 475                 return 0;
 476
 477         switch (insn.mm_i_format.opcode) {
 478         case mm_pool32a_op:
 479                 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
 480                     mm_pool32axf_op) {
 481                         switch (insn.mm_i_format.simmediate >>
 482                                 MM_POOL32A_MINOR_SHIFT) {
 483                         case mm_jalr_op:
 484                         case mm_jalrhb_op:
 485                         case mm_jalrs_op:
 486                         case mm_jalrshb_op:
 487                                 if (insn.mm_i_format.rt != 0)   /* Not mm_jr */
 488                                         regs->regs[insn.mm_i_format.rt] =
 489                                                 regs->cp0_epc +
 490                                                 dec_insn.pc_inc +
 491                                                 dec_insn.next_pc_inc;
 492                                 *contpc = regs->regs[insn.mm_i_format.rs];
 493                                 return 1;
 494                                 break;
 495                         }
 496                 }
 497                 break;
 498         case mm_pool32i_op:
 499                 switch (insn.mm_i_format.rt) {
 500                 case mm_bltzals_op:
 501                 case mm_bltzal_op:
 502                         regs->regs[31] = regs->cp0_epc +
 503                                 dec_insn.pc_inc +
 504                                 dec_insn.next_pc_inc;
 505                         /* Fall through */
 506                 case mm_bltz_op:
 507                         if ((long)regs->regs[insn.mm_i_format.rs] < 0)
 508                                 *contpc = regs->cp0_epc +
 509                                         dec_insn.pc_inc +
 510                                         (insn.mm_i_format.simmediate << 1);
 511                         else
 512                                 *contpc = regs->cp0_epc +
 513                                         dec_insn.pc_inc +
 514                                         dec_insn.next_pc_inc;
 515                         return 1;
 516                         break;
 517                 case mm_bgezals_op:
 518                 case mm_bgezal_op:
 519                         regs->regs[31] = regs->cp0_epc +
 520                                         dec_insn.pc_inc +
 521                                         dec_insn.next_pc_inc;
 522                         /* Fall through */
 523                 case mm_bgez_op:
 524                         if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
 525                                 *contpc = regs->cp0_epc +
 526                                         dec_insn.pc_inc +
 527                                         (insn.mm_i_format.simmediate << 1);
 528                         else
 529                                 *contpc = regs->cp0_epc +
 530                                         dec_insn.pc_inc +
 531                                         dec_insn.next_pc_inc;
 532                         return 1;
 533                         break;
 534                 case mm_blez_op:
 535                         if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
 536                                 *contpc = regs->cp0_epc +
 537                                         dec_insn.pc_inc +
 538                                         (insn.mm_i_format.simmediate << 1);
 539                         else
 540                                 *contpc = regs->cp0_epc +
 541                                         dec_insn.pc_inc +
 542                                         dec_insn.next_pc_inc;
 543                         return 1;
 544                         break;
 545                 case mm_bgtz_op:
 546                         if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
 547                                 *contpc = regs->cp0_epc +
 548                                         dec_insn.pc_inc +
 549                                         (insn.mm_i_format.simmediate << 1);
 550                         else
 551                                 *contpc = regs->cp0_epc +
 552                                         dec_insn.pc_inc +
 553                                         dec_insn.next_pc_inc;
 554                         return 1;
 555                         break;
 556                 case mm_bc2f_op:
 557                 case mm_bc1f_op:
 558                         bc_false = 1;
 559                         /* Fall through */
 560                 case mm_bc2t_op:
 561                 case mm_bc1t_op:
 562                         preempt_disable();
 563                         if (is_fpu_owner())
 564                                 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
 565                         else
 566                                 fcr31 = current->thread.fpu.fcr31;
 567                         preempt_enable();
 568
 569                         if (bc_false)
 570                                 fcr31 = ~fcr31;
 571
 572                         bit = (insn.mm_i_format.rs >> 2);
 573                         bit += (bit != 0);
 574                         bit += 23;
 575                         if (fcr31 & (1 << bit))
 576                                 *contpc = regs->cp0_epc +
 577                                         dec_insn.pc_inc +
 578                                         (insn.mm_i_format.simmediate << 1);
 579                         else
 580                                 *contpc = regs->cp0_epc +
 581                                         dec_insn.pc_inc + dec_insn.next_pc_inc;
 582                         return 1;
 583                         break;
 584                 }
 585                 break;
 586         case mm_pool16c_op:
 587                 switch (insn.mm_i_format.rt) {
 588                 case mm_jalr16_op:
 589                 case mm_jalrs16_op:
 590                         regs->regs[31] = regs->cp0_epc +
 591                                 dec_insn.pc_inc + dec_insn.next_pc_inc;
 592                         /* Fall through */
 593                 case mm_jr16_op:
 594                         *contpc = regs->regs[insn.mm_i_format.rs];
 595                         return 1;
 596                         break;
 597                 }
 598                 break;
 599         case mm_beqz16_op:
 600                 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
 601                         *contpc = regs->cp0_epc +
 602                                 dec_insn.pc_inc +
 603                                 (insn.mm_b1_format.simmediate << 1);
 604                 else
 605                         *contpc = regs->cp0_epc +
 606                                 dec_insn.pc_inc + dec_insn.next_pc_inc;
 607                 return 1;
 608                 break;
 609         case mm_bnez16_op:
 610                 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
 611                         *contpc = regs->cp0_epc +
 612                                 dec_insn.pc_inc +
 613                                 (insn.mm_b1_format.simmediate << 1);
 614                 else
 615                         *contpc = regs->cp0_epc +
 616                                 dec_insn.pc_inc + dec_insn.next_pc_inc;
 617                 return 1;
 618                 break;
 619         case mm_b16_op:
 620                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 621                          (insn.mm_b0_format.simmediate << 1);
 622                 return 1;
 623                 break;
 624         case mm_beq32_op:
 625                 if (regs->regs[insn.mm_i_format.rs] ==
 626                     regs->regs[insn.mm_i_format.rt])
 627                         *contpc = regs->cp0_epc +
 628                                 dec_insn.pc_inc +
 629                                 (insn.mm_i_format.simmediate << 1);
 630                 else
 631                         *contpc = regs->cp0_epc +
 632                                 dec_insn.pc_inc +
 633                                 dec_insn.next_pc_inc;
 634                 return 1;
 635                 break;
 636         case mm_bne32_op:
 637                 if (regs->regs[insn.mm_i_format.rs] !=
 638                     regs->regs[insn.mm_i_format.rt])
 639                         *contpc = regs->cp0_epc +
 640                                 dec_insn.pc_inc +
 641                                 (insn.mm_i_format.simmediate << 1);
 642                 else
 643                         *contpc = regs->cp0_epc +
 644                                 dec_insn.pc_inc + dec_insn.next_pc_inc;
 645                 return 1;
 646                 break;
 647         case mm_jalx32_op:
 648                 regs->regs[31] = regs->cp0_epc +
 649                         dec_insn.pc_inc + dec_insn.next_pc_inc;
 650                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 651                 *contpc >>= 28;
 652                 *contpc <<= 28;
 653                 *contpc |= (insn.j_format.target << 2);
 654                 return 1;
 655                 break;
 656         case mm_jals32_op:
 657         case mm_jal32_op:
 658                 regs->regs[31] = regs->cp0_epc +
 659                         dec_insn.pc_inc + dec_insn.next_pc_inc;
 660                 /* Fall through */
 661         case mm_j32_op:
 662                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 663                 *contpc >>= 27;
 664                 *contpc <<= 27;
 665                 *contpc |= (insn.j_format.target << 1);
 666                 set_isa16_mode(*contpc);
 667                 return 1;
 668                 break;
 669         }
 670         return 0;
 671 }
 672
 673 /*
 674  * Redundant with logic already in kernel/branch.c,
 675  * embedded in compute_return_epc.  At some point,
 676  * a single subroutine should be used across both
 677  * modules.
 678  */
 679 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 680                          unsigned long *contpc)
 681 {
 682         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 683         unsigned int fcr31;
 684         unsigned int bit = 0;
 685
 686         switch (insn.i_format.opcode) {
 687         case spec_op:
 688                 switch (insn.r_format.func) {
 689                 case jalr_op:
 690                         regs->regs[insn.r_format.rd] =
 691                                 regs->cp0_epc + dec_insn.pc_inc +
 692                                 dec_insn.next_pc_inc;
 693                         /* Fall through */
 694                 case jr_op:
 695                         *contpc = regs->regs[insn.r_format.rs];
 696                         return 1;
 697                         break;
 698                 }
 699                 break;
 700         case bcond_op:
 701                 switch (insn.i_format.rt) {
 702                 case bltzal_op:
 703                 case bltzall_op:
 704                         regs->regs[31] = regs->cp0_epc +
 705                                 dec_insn.pc_inc +
 706                                 dec_insn.next_pc_inc;
 707                         /* Fall through */
 708                 case bltz_op:
 709                 case bltzl_op:
 710                         if ((long)regs->regs[insn.i_format.rs] < 0)
 711                                 *contpc = regs->cp0_epc +
 712                                         dec_insn.pc_inc +
 713                                         (insn.i_format.simmediate << 2);
 714                         else
 715                                 *contpc = regs->cp0_epc +
 716                                         dec_insn.pc_inc +
 717                                         dec_insn.next_pc_inc;
 718                         return 1;
 719                         break;
 720                 case bgezal_op:
 721                 case bgezall_op:
 722                         regs->regs[31] = regs->cp0_epc +
 723                                 dec_insn.pc_inc +
 724                                 dec_insn.next_pc_inc;
 725                         /* Fall through */
 726                 case bgez_op:
 727                 case bgezl_op:
 728                         if ((long)regs->regs[insn.i_format.rs] >= 0)
 729                                 *contpc = regs->cp0_epc +
 730                                         dec_insn.pc_inc +
 731                                         (insn.i_format.simmediate << 2);
 732                         else
 733                                 *contpc = regs->cp0_epc +
 734                                         dec_insn.pc_inc +
 735                                         dec_insn.next_pc_inc;
 736                         return 1;
 737                         break;
 738                 }
 739                 break;
 740         case jalx_op:
 741                 set_isa16_mode(bit);
 742         case jal_op:
 743                 regs->regs[31] = regs->cp0_epc +
 744                         dec_insn.pc_inc +
 745                         dec_insn.next_pc_inc;
 746                 /* Fall through */
 747         case j_op:
 748                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 749                 *contpc >>= 28;
 750                 *contpc <<= 28;
 751                 *contpc |= (insn.j_format.target << 2);
 752                 /* Set microMIPS mode bit: XOR for jalx. */
 753                 *contpc ^= bit;
 754                 return 1;
 755                 break;
 756         case beq_op:
 757         case beql_op:
 758                 if (regs->regs[insn.i_format.rs] ==
 759                     regs->regs[insn.i_format.rt])
 760                         *contpc = regs->cp0_epc +
 761                                 dec_insn.pc_inc +
 762                                 (insn.i_format.simmediate << 2);
 763                 else
 764                         *contpc = regs->cp0_epc +
 765                                 dec_insn.pc_inc +
 766                                 dec_insn.next_pc_inc;
 767                 return 1;
 768                 break;
 769         case bne_op:
 770         case bnel_op:
 771                 if (regs->regs[insn.i_format.rs] !=
 772                     regs->regs[insn.i_format.rt])
 773                         *contpc = regs->cp0_epc +
 774                                 dec_insn.pc_inc +
 775                                 (insn.i_format.simmediate << 2);
 776                 else
 777                         *contpc = regs->cp0_epc +
 778                                 dec_insn.pc_inc +
 779                                 dec_insn.next_pc_inc;
 780                 return 1;
 781                 break;
 782         case blez_op:
 783         case blezl_op:
 784                 if ((long)regs->regs[insn.i_format.rs] <= 0)
 785                         *contpc = regs->cp0_epc +
 786                                 dec_insn.pc_inc +
 787                                 (insn.i_format.simmediate << 2);
 788                 else
 789                         *contpc = regs->cp0_epc +
 790                                 dec_insn.pc_inc +
 791                                 dec_insn.next_pc_inc;
 792                 return 1;
 793                 break;
 794         case bgtz_op:
 795         case bgtzl_op:
 796                 if ((long)regs->regs[insn.i_format.rs] > 0)
 797                         *contpc = regs->cp0_epc +
 798                                 dec_insn.pc_inc +
 799                                 (insn.i_format.simmediate << 2);
 800                 else
 801                         *contpc = regs->cp0_epc +
 802                                 dec_insn.pc_inc +
 803                                 dec_insn.next_pc_inc;
 804                 return 1;
 805                 break;
 806         case cop0_op:
 807         case cop1_op:
 808         case cop2_op:
 809         case cop1x_op:
 810                 if (insn.i_format.rs == bc_op) {
 811                         preempt_disable();
 812                         if (is_fpu_owner())
 813                                 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
 814                         else
 815                                 fcr31 = current->thread.fpu.fcr31;
 816                         preempt_enable();
 817
 818                         bit = (insn.i_format.rt >> 2);
 819                         bit += (bit != 0);
 820                         bit += 23;
 821                         switch (insn.i_format.rt & 3) {
 822                         case 0: /* bc1f */
 823                         case 2: /* bc1fl */
 824                                 if (~fcr31 & (1 << bit))
 825                                         *contpc = regs->cp0_epc +
 826                                                 dec_insn.pc_inc +
 827                                                 (insn.i_format.simmediate << 2);
 828                                 else
 829                                         *contpc = regs->cp0_epc +
 830                                                 dec_insn.pc_inc +
 831                                                 dec_insn.next_pc_inc;
 832                                 return 1;
 833                                 break;
 834                         case 1: /* bc1t */
 835                         case 3: /* bc1tl */
 836                                 if (fcr31 & (1 << bit))
 837                                         *contpc = regs->cp0_epc +
 838                                                 dec_insn.pc_inc +
 839                                                 (insn.i_format.simmediate << 2);
 840                                 else
 841                                         *contpc = regs->cp0_epc +
 842                                                 dec_insn.pc_inc +
 843                                                 dec_insn.next_pc_inc;
 844                                 return 1;
 845                                 break;
 846                         }
 847                 }
 848                 break;
 849         }
 850         return 0;
 851 }
 852
 853 /*
 854  * In the Linux kernel, we support selection of FPR format on the
 855  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
 856  * is hardwired to zero, which would imply a 32-bit FPU even for
 857  * 64-bit CPUs so we rather look at TIF_32BIT_REGS.
 858  * FPU emu is slow and bulky and optimizing this function offers fairly
 859  * sizeable benefits so we try to be clever and make this function return
 860  * a constant whenever possible, that is on 64-bit kernels without O32
 861  * compatibility enabled and on 32-bit kernels.
 862  */
 863 static inline int cop1_64bit(struct pt_regs *xcp)
 864 {
 865 #if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
 866         return 1;
 867 #elif defined(CONFIG_64BIT) && defined(CONFIG_MIPS32_O32)
 868         return !test_thread_flag(TIF_32BIT_REGS);
 869 #else
 870         return 0;
 871 #endif
 872 }
 873
 874 #define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
 875                         (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
 876
 877 #define SITOREG(si, x)  (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
 878                         cop1_64bit(xcp) || !(x & 1) ? \
 879                         ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
 880                         ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
 881
 882 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
 883 #define DITOREG(di, x)  (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
 884
 885 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
 886 #define SPTOREG(sp, x)  SITOREG((sp).bits, x)
 887 #define DPFROMREG(dp, x)        DIFROMREG((dp).bits, x)
 888 #define DPTOREG(dp, x)  DITOREG((dp).bits, x)
 889
 890 /*
 891  * Emulate the single floating point instruction pointed at by EPC.
 892  * Two instructions if the instruction is in a branch delay slot.
 893  */
 894
 895 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 896                 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
 897 {
 898         mips_instruction ir;
 899         unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
 900         unsigned int cond;
 901         int pc_inc;
 902
 903         /* XXX NEC Vr54xx bug workaround */
 904         if (xcp->cp0_cause & CAUSEF_BD) {
 905                 if (dec_insn.micro_mips_mode) {
 906                         if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
 907                                 xcp->cp0_cause &= ~CAUSEF_BD;
 908                 } else {
 909                         if (!isBranchInstr(xcp, dec_insn, &contpc))
 910                                 xcp->cp0_cause &= ~CAUSEF_BD;
 911                 }
 912         }
 913
 914         if (xcp->cp0_cause & CAUSEF_BD) {
 915                 /*
 916                  * The instruction to be emulated is in a branch delay slot
 917                  * which means that we have to  emulate the branch instruction
 918                  * BEFORE we do the cop1 instruction.
 919                  *
 920                  * This branch could be a COP1 branch, but in that case we
 921                  * would have had a trap for that instruction, and would not
 922                  * come through this route.
 923                  *
 924                  * Linux MIPS branch emulator operates on context, updating the
 925                  * cp0_epc.
 926                  */
 927                 ir = dec_insn.next_insn;  /* process delay slot instr */
 928                 pc_inc = dec_insn.next_pc_inc;
 929         } else {
 930                 ir = dec_insn.insn;       /* process current instr */
 931                 pc_inc = dec_insn.pc_inc;
 932         }
 933
 934         /*
 935          * Since microMIPS FPU instructios are a subset of MIPS32 FPU
 936          * instructions, we want to convert microMIPS FPU instructions
 937          * into MIPS32 instructions so that we could reuse all of the
 938          * FPU emulation code.
 939          *
 940          * NOTE: We cannot do this for branch instructions since they
 941          *       are not a subset. Example: Cannot emulate a 16-bit
 942          *       aligned target address with a MIPS32 instruction.
 943          */
 944         if (dec_insn.micro_mips_mode) {
 945                 /*
 946                  * If next instruction is a 16-bit instruction, then it
 947                  * it cannot be a FPU instruction. This could happen
 948                  * since we can be called for non-FPU instructions.
 949                  */
 950                 if ((pc_inc == 2) ||
 951                         (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
 952                          == SIGILL))
 953                         return SIGILL;
 954         }
 955
 956       emul:
 957         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
 958         MIPS_FPU_EMU_INC_STATS(emulated);
 959         switch (MIPSInst_OPCODE(ir)) {
 960         case ldc1_op:{
 961                 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 962                         MIPSInst_SIMM(ir));
 963                 u64 val;
 964
 965                 MIPS_FPU_EMU_INC_STATS(loads);
 966
 967                 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
 968                         MIPS_FPU_EMU_INC_STATS(errors);
 969                         *fault_addr = va;
 970                         return SIGBUS;
 971                 }
 972                 if (__get_user(val, va)) {
 973                         MIPS_FPU_EMU_INC_STATS(errors);
 974                         *fault_addr = va;
 975                         return SIGSEGV;
 976                 }
 977                 DITOREG(val, MIPSInst_RT(ir));
 978                 break;
 979         }
 980
 981         case sdc1_op:{
 982                 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 983                         MIPSInst_SIMM(ir));
 984                 u64 val;
 985
 986                 MIPS_FPU_EMU_INC_STATS(stores);
 987                 DIFROMREG(val, MIPSInst_RT(ir));
 988                 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
 989                         MIPS_FPU_EMU_INC_STATS(errors);
 990                         *fault_addr = va;
 991                         return SIGBUS;
 992                 }
 993                 if (__put_user(val, va)) {
 994                         MIPS_FPU_EMU_INC_STATS(errors);
 995                         *fault_addr = va;
 996                         return SIGSEGV;
 997                 }
 998                 break;
 999         }
1000
1001         case lwc1_op:{
1002                 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1003                         MIPSInst_SIMM(ir));
1004                 u32 val;
1005
1006                 MIPS_FPU_EMU_INC_STATS(loads);
1007                 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1008                         MIPS_FPU_EMU_INC_STATS(errors);
1009                         *fault_addr = va;
1010                         return SIGBUS;
1011                 }
1012                 if (__get_user(val, va)) {
1013                         MIPS_FPU_EMU_INC_STATS(errors);
1014                         *fault_addr = va;
1015                         return SIGSEGV;
1016                 }
1017                 SITOREG(val, MIPSInst_RT(ir));
1018                 break;
1019         }
1020
1021         case swc1_op:{
1022                 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1023                         MIPSInst_SIMM(ir));
1024                 u32 val;
1025
1026                 MIPS_FPU_EMU_INC_STATS(stores);
1027                 SIFROMREG(val, MIPSInst_RT(ir));
1028                 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1029                         MIPS_FPU_EMU_INC_STATS(errors);
1030                         *fault_addr = va;
1031                         return SIGBUS;
1032                 }
1033                 if (__put_user(val, va)) {
1034                         MIPS_FPU_EMU_INC_STATS(errors);
1035                         *fault_addr = va;
1036                         return SIGSEGV;
1037                 }
1038                 break;
1039         }
1040
1041         case cop1_op:
1042                 switch (MIPSInst_RS(ir)) {
1043
1044 #if defined(__mips64)
1045                 case dmfc_op:
1046                         /* copregister fs -> gpr[rt] */
1047                         if (MIPSInst_RT(ir) != 0) {
1048                                 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1049                                         MIPSInst_RD(ir));
1050                         }
1051                         break;
1052
1053                 case dmtc_op:
1054                         /* copregister fs <- rt */
1055                         DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1056                         break;
1057 #endif
1058
1059                 case mfc_op:
1060                         /* copregister rd -> gpr[rt] */
1061                         if (MIPSInst_RT(ir) != 0) {
1062                                 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1063                                         MIPSInst_RD(ir));
1064                         }
1065                         break;
1066
1067                 case mtc_op:
1068                         /* copregister rd <- rt */
1069                         SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1070                         break;
1071
1072                 case cfc_op:{
1073                         /* cop control register rd -> gpr[rt] */
1074                         u32 value;
1075
1076                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
1077                                 value = ctx->fcr31;
1078                                 value = (value & ~FPU_CSR_RM) |
1079                                         mips_rm[modeindex(value)];
1080 #ifdef CSRTRACE
1081                                 printk("%p gpr[%d]<-csr=%08x\n",
1082                                         (void *) (xcp->cp0_epc),
1083                                         MIPSInst_RT(ir), value);
1084 #endif
1085                         }
1086                         else if (MIPSInst_RD(ir) == FPCREG_RID)
1087                                 value = 0;
1088                         else
1089                                 value = 0;
1090                         if (MIPSInst_RT(ir))
1091                                 xcp->regs[MIPSInst_RT(ir)] = value;
1092                         break;
1093                 }
1094
1095                 case ctc_op:{
1096                         /* copregister rd <- rt */
1097                         u32 value;
1098
1099                         if (MIPSInst_RT(ir) == 0)
1100                                 value = 0;
1101                         else
1102                                 value = xcp->regs[MIPSInst_RT(ir)];
1103
1104                         /* we only have one writable control reg
1105                          */
1106                         if (MIPSInst_RD(ir) == FPCREG_CSR) {
1107 #ifdef CSRTRACE
1108                                 printk("%p gpr[%d]->csr=%08x\n",
1109                                         (void *) (xcp->cp0_epc),
1110                                         MIPSInst_RT(ir), value);
1111 #endif
1112
1113                                 /*
1114                                  * Don't write reserved bits,
1115                                  * and convert to ieee library modes
1116                                  */
1117                                 ctx->fcr31 = (value &
1118                                                 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
1119                                                 ieee_rm[modeindex(value)];
1120                         }
1121                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1122                                 return SIGFPE;
1123                         }
1124                         break;
1125                 }
1126
1127                 case bc_op:{
1128                         int likely = 0;
1129
1130                         if (xcp->cp0_cause & CAUSEF_BD)
1131                                 return SIGILL;
1132
1133 #if __mips >= 4
1134                         cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
1135 #else
1136                         cond = ctx->fcr31 & FPU_CSR_COND;
1137 #endif
1138                         switch (MIPSInst_RT(ir) & 3) {
1139                         case bcfl_op:
1140                                 likely = 1;
1141                         case bcf_op:
1142                                 cond = !cond;
1143                                 break;
1144                         case bctl_op:
1145                                 likely = 1;
1146                         case bct_op:
1147                                 break;
1148                         default:
1149                                 /* thats an illegal instruction */
1150                                 return SIGILL;
1151                         }
1152
1153                         xcp->cp0_cause |= CAUSEF_BD;
1154                         if (cond) {
1155                                 /* branch taken: emulate dslot
1156                                  * instruction
1157                                  */
1158                                 xcp->cp0_epc += dec_insn.pc_inc;
1159
1160                                 contpc = MIPSInst_SIMM(ir);
1161                                 ir = dec_insn.next_insn;
1162                                 if (dec_insn.micro_mips_mode) {
1163                                         contpc = (xcp->cp0_epc + (contpc << 1));
1164
1165                                         /* If 16-bit instruction, not FPU. */
1166                                         if ((dec_insn.next_pc_inc == 2) ||
1167                                                 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1168
1169                                                 /*
1170                                                  * Since this instruction will
1171                                                  * be put on the stack with
1172                                                  * 32-bit words, get around
1173                                                  * this problem by putting a
1174                                                  * NOP16 as the second one.
1175                                                  */
1176                                                 if (dec_insn.next_pc_inc == 2)
1177                                                         ir = (ir & (~0xffff)) | MM_NOP16;
1178
1179                                                 /*
1180                                                  * Single step the non-CP1
1181                                                  * instruction in the dslot.
1182                                                  */
1183                                                 return mips_dsemul(xcp, ir, contpc);
1184                                         }
1185                                 } else
1186                                         contpc = (xcp->cp0_epc + (contpc << 2));
1187
1188                                 switch (MIPSInst_OPCODE(ir)) {
1189                                 case lwc1_op:
1190                                 case swc1_op:
1191 #if (__mips >= 2 || defined(__mips64))
1192                                 case ldc1_op:
1193                                 case sdc1_op:
1194 #endif
1195                                 case cop1_op:
1196 #if __mips >= 4 && __mips != 32
1197                                 case cop1x_op:
1198 #endif
1199                                         /* its one of ours */
1200                                         goto emul;
1201 #if __mips >= 4
1202                                 case spec_op:
1203                                         if (MIPSInst_FUNC(ir) == movc_op)
1204                                                 goto emul;
1205                                         break;
1206 #endif
1207                                 }
1208
1209                                 /*
1210                                  * Single step the non-cp1
1211                                  * instruction in the dslot
1212                                  */
1213                                 return mips_dsemul(xcp, ir, contpc);
1214                         }
1215                         else {
1216                                 /* branch not taken */
1217                                 if (likely) {
1218                                         /*
1219                                          * branch likely nullifies
1220                                          * dslot if not taken
1221                                          */
1222                                         xcp->cp0_epc += dec_insn.pc_inc;
1223                                         contpc += dec_insn.pc_inc;
1224                                         /*
1225                                          * else continue & execute
1226                                          * dslot as normal insn
1227                                          */
1228                                 }
1229                         }
1230                         break;
1231                 }
1232
1233                 default:
1234                         if (!(MIPSInst_RS(ir) & 0x10))
1235                                 return SIGILL;
1236                         {
1237                                 int sig;
1238
1239                                 /* a real fpu computation instruction */
1240                                 if ((sig = fpu_emu(xcp, ctx, ir)))
1241                                         return sig;
1242                         }
1243                 }
1244                 break;
1245
1246 #if __mips >= 4 && __mips != 32
1247         case cop1x_op:{
1248                 int sig = fpux_emu(xcp, ctx, ir, fault_addr);
1249                 if (sig)
1250                         return sig;
1251                 break;
1252         }
1253 #endif
1254
1255 #if __mips >= 4
1256         case spec_op:
1257                 if (MIPSInst_FUNC(ir) != movc_op)
1258                         return SIGILL;
1259                 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1260                 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1261                         xcp->regs[MIPSInst_RD(ir)] =
1262                                 xcp->regs[MIPSInst_RS(ir)];
1263                 break;
1264 #endif
1265
1266         default:
1267                 return SIGILL;
1268         }
1269
1270         /* we did it !! */
1271         xcp->cp0_epc = contpc;
1272         xcp->cp0_cause &= ~CAUSEF_BD;
1273
1274         return 0;
1275 }
1276
1277 /*
1278  * Conversion table from MIPS compare ops 48-63
1279  * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1280  */
1281 static const unsigned char cmptab[8] = {
1282         0,                      /* cmp_0 (sig) cmp_sf */
1283         IEEE754_CUN,            /* cmp_un (sig) cmp_ngle */
1284         IEEE754_CEQ,            /* cmp_eq (sig) cmp_seq */
1285         IEEE754_CEQ | IEEE754_CUN,      /* cmp_ueq (sig) cmp_ngl  */
1286         IEEE754_CLT,            /* cmp_olt (sig) cmp_lt */
1287         IEEE754_CLT | IEEE754_CUN,      /* cmp_ult (sig) cmp_nge */
1288         IEEE754_CLT | IEEE754_CEQ,      /* cmp_ole (sig) cmp_le */
1289         IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN,        /* cmp_ule (sig) cmp_ngt */
1290 };
1291
1292
1293 #if __mips >= 4 && __mips != 32
1294
1295 /*
1296  * Additional MIPS4 instructions
1297  */
1298
1299 #define DEF3OP(name, p, f1, f2, f3) \
1300 static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
1301     ieee754##p t) \
1302 { \
1303         struct _ieee754_csr ieee754_csr_save; \
1304         s = f1(s, t); \
1305         ieee754_csr_save = ieee754_csr; \
1306         s = f2(s, r); \
1307         ieee754_csr_save.cx |= ieee754_csr.cx; \
1308         ieee754_csr_save.sx |= ieee754_csr.sx; \
1309         s = f3(s); \
1310         ieee754_csr.cx |= ieee754_csr_save.cx; \
1311         ieee754_csr.sx |= ieee754_csr_save.sx; \
1312         return s; \
1313 }
1314
1315 static ieee754dp fpemu_dp_recip(ieee754dp d)
1316 {
1317         return ieee754dp_div(ieee754dp_one(0), d);
1318 }
1319
1320 static ieee754dp fpemu_dp_rsqrt(ieee754dp d)
1321 {
1322         return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1323 }
1324
1325 static ieee754sp fpemu_sp_recip(ieee754sp s)
1326 {
1327         return ieee754sp_div(ieee754sp_one(0), s);
1328 }
1329
1330 static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
1331 {
1332         return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1333 }
1334
1335 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1336 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1337 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1338 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1339 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1340 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1341 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1342 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1343
1344 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1345         mips_instruction ir, void *__user *fault_addr)
1346 {
1347         unsigned rcsr = 0;      /* resulting csr */
1348
1349         MIPS_FPU_EMU_INC_STATS(cp1xops);
1350
1351         switch (MIPSInst_FMA_FFMT(ir)) {
1352         case s_fmt:{            /* 0 */
1353
1354                 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
1355                 ieee754sp fd, fr, fs, ft;
1356                 u32 __user *va;
1357                 u32 val;
1358
1359                 switch (MIPSInst_FUNC(ir)) {
1360                 case lwxc1_op:
1361                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1362                                 xcp->regs[MIPSInst_FT(ir)]);
1363
1364                         MIPS_FPU_EMU_INC_STATS(loads);
1365                         if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1366                                 MIPS_FPU_EMU_INC_STATS(errors);
1367                                 *fault_addr = va;
1368                                 return SIGBUS;
1369                         }
1370                         if (__get_user(val, va)) {
1371                                 MIPS_FPU_EMU_INC_STATS(errors);
1372                                 *fault_addr = va;
1373                                 return SIGSEGV;
1374                         }
1375                         SITOREG(val, MIPSInst_FD(ir));
1376                         break;
1377
1378                 case swxc1_op:
1379                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1380                                 xcp->regs[MIPSInst_FT(ir)]);
1381
1382                         MIPS_FPU_EMU_INC_STATS(stores);
1383
1384                         SIFROMREG(val, MIPSInst_FS(ir));
1385                         if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1386                                 MIPS_FPU_EMU_INC_STATS(errors);
1387                                 *fault_addr = va;
1388                                 return SIGBUS;
1389                         }
1390                         if (put_user(val, va)) {
1391                                 MIPS_FPU_EMU_INC_STATS(errors);
1392                                 *fault_addr = va;
1393                                 return SIGSEGV;
1394                         }
1395                         break;
1396
1397                 case madd_s_op:
1398                         handler = fpemu_sp_madd;
1399                         goto scoptop;
1400                 case msub_s_op:
1401                         handler = fpemu_sp_msub;
1402                         goto scoptop;
1403                 case nmadd_s_op:
1404                         handler = fpemu_sp_nmadd;
1405                         goto scoptop;
1406                 case nmsub_s_op:
1407                         handler = fpemu_sp_nmsub;
1408                         goto scoptop;
1409
1410                       scoptop:
1411                         SPFROMREG(fr, MIPSInst_FR(ir));
1412                         SPFROMREG(fs, MIPSInst_FS(ir));
1413                         SPFROMREG(ft, MIPSInst_FT(ir));
1414                         fd = (*handler) (fr, fs, ft);
1415                         SPTOREG(fd, MIPSInst_FD(ir));
1416
1417                       copcsr:
1418                         if (ieee754_cxtest(IEEE754_INEXACT))
1419                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1420                         if (ieee754_cxtest(IEEE754_UNDERFLOW))
1421                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1422                         if (ieee754_cxtest(IEEE754_OVERFLOW))
1423                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1424                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1425                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1426
1427                         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1428                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1429                                 /*printk ("SIGFPE: fpu csr = %08x\n",
1430                                    ctx->fcr31); */
1431                                 return SIGFPE;
1432                         }
1433
1434                         break;
1435
1436                 default:
1437                         return SIGILL;
1438                 }
1439                 break;
1440         }
1441
1442         case d_fmt:{            /* 1 */
1443                 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
1444                 ieee754dp fd, fr, fs, ft;
1445                 u64 __user *va;
1446                 u64 val;
1447
1448                 switch (MIPSInst_FUNC(ir)) {
1449                 case ldxc1_op:
1450                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1451                                 xcp->regs[MIPSInst_FT(ir)]);
1452
1453                         MIPS_FPU_EMU_INC_STATS(loads);
1454                         if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1455                                 MIPS_FPU_EMU_INC_STATS(errors);
1456                                 *fault_addr = va;
1457                                 return SIGBUS;
1458                         }
1459                         if (__get_user(val, va)) {
1460                                 MIPS_FPU_EMU_INC_STATS(errors);
1461                                 *fault_addr = va;
1462                                 return SIGSEGV;
1463                         }
1464                         DITOREG(val, MIPSInst_FD(ir));
1465                         break;
1466
1467                 case sdxc1_op:
1468                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1469                                 xcp->regs[MIPSInst_FT(ir)]);
1470
1471                         MIPS_FPU_EMU_INC_STATS(stores);
1472                         DIFROMREG(val, MIPSInst_FS(ir));
1473                         if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1474                                 MIPS_FPU_EMU_INC_STATS(errors);
1475                                 *fault_addr = va;
1476                                 return SIGBUS;
1477                         }
1478                         if (__put_user(val, va)) {
1479                                 MIPS_FPU_EMU_INC_STATS(errors);
1480                                 *fault_addr = va;
1481                                 return SIGSEGV;
1482                         }
1483                         break;
1484
1485                 case madd_d_op:
1486                         handler = fpemu_dp_madd;
1487                         goto dcoptop;
1488                 case msub_d_op:
1489                         handler = fpemu_dp_msub;
1490                         goto dcoptop;
1491                 case nmadd_d_op:
1492                         handler = fpemu_dp_nmadd;
1493                         goto dcoptop;
1494                 case nmsub_d_op:
1495                         handler = fpemu_dp_nmsub;
1496                         goto dcoptop;
1497
1498                       dcoptop:
1499                         DPFROMREG(fr, MIPSInst_FR(ir));
1500                         DPFROMREG(fs, MIPSInst_FS(ir));
1501                         DPFROMREG(ft, MIPSInst_FT(ir));
1502                         fd = (*handler) (fr, fs, ft);
1503                         DPTOREG(fd, MIPSInst_FD(ir));
1504                         goto copcsr;
1505
1506                 default:
1507                         return SIGILL;
1508                 }
1509                 break;
1510         }
1511
1512         case 0x7:               /* 7 */
1513                 if (MIPSInst_FUNC(ir) != pfetch_op) {
1514                         return SIGILL;
1515                 }
1516                 /* ignore prefx operation */
1517                 break;
1518
1519         default:
1520                 return SIGILL;
1521         }
1522
1523         return 0;
1524 }
1525 #endif
1526
1527
1528
1529 /*
1530  * Emulate a single COP1 arithmetic instruction.
1531  */
1532 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1533         mips_instruction ir)
1534 {
1535         int rfmt;               /* resulting format */
1536         unsigned rcsr = 0;      /* resulting csr */
1537         unsigned cond;
1538         union {
1539                 ieee754dp d;
1540                 ieee754sp s;
1541                 int w;
1542 #ifdef __mips64
1543                 s64 l;
1544 #endif
1545         } rv;                   /* resulting value */
1546
1547         MIPS_FPU_EMU_INC_STATS(cp1ops);
1548         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1549         case s_fmt:{            /* 0 */
1550                 union {
1551                         ieee754sp(*b) (ieee754sp, ieee754sp);
1552                         ieee754sp(*u) (ieee754sp);
1553                 } handler;
1554
1555                 switch (MIPSInst_FUNC(ir)) {
1556                         /* binary ops */
1557                 case fadd_op:
1558                         handler.b = ieee754sp_add;
1559                         goto scopbop;
1560                 case fsub_op:
1561                         handler.b = ieee754sp_sub;
1562                         goto scopbop;
1563                 case fmul_op:
1564                         handler.b = ieee754sp_mul;
1565                         goto scopbop;
1566                 case fdiv_op:
1567                         handler.b = ieee754sp_div;
1568                         goto scopbop;
1569
1570                         /* unary  ops */
1571 #if __mips >= 2 || defined(__mips64)
1572                 case fsqrt_op:
1573                         handler.u = ieee754sp_sqrt;
1574                         goto scopuop;
1575 #endif
1576 #if __mips >= 4 && __mips != 32
1577                 case frsqrt_op:
1578                         handler.u = fpemu_sp_rsqrt;
1579                         goto scopuop;
1580                 case frecip_op:
1581                         handler.u = fpemu_sp_recip;
1582                         goto scopuop;
1583 #endif
1584 #if __mips >= 4
1585                 case fmovc_op:
1586                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1587                         if (((ctx->fcr31 & cond) != 0) !=
1588                                 ((MIPSInst_FT(ir) & 1) != 0))
1589                                 return 0;
1590                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1591                         break;
1592                 case fmovz_op:
1593                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1594                                 return 0;
1595                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1596                         break;
1597                 case fmovn_op:
1598                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1599                                 return 0;
1600                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1601                         break;
1602 #endif
1603                 case fabs_op:
1604                         handler.u = ieee754sp_abs;
1605                         goto scopuop;
1606                 case fneg_op:
1607                         handler.u = ieee754sp_neg;
1608                         goto scopuop;
1609                 case fmov_op:
1610                         /* an easy one */
1611                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1612                         goto copcsr;
1613
1614                         /* binary op on handler */
1615                       scopbop:
1616                         {
1617                                 ieee754sp fs, ft;
1618
1619                                 SPFROMREG(fs, MIPSInst_FS(ir));
1620                                 SPFROMREG(ft, MIPSInst_FT(ir));
1621
1622                                 rv.s = (*handler.b) (fs, ft);
1623                                 goto copcsr;
1624                         }
1625                       scopuop:
1626                         {
1627                                 ieee754sp fs;
1628
1629                                 SPFROMREG(fs, MIPSInst_FS(ir));
1630                                 rv.s = (*handler.u) (fs);
1631                                 goto copcsr;
1632                         }
1633                       copcsr:
1634                         if (ieee754_cxtest(IEEE754_INEXACT))
1635                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1636                         if (ieee754_cxtest(IEEE754_UNDERFLOW))
1637                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1638                         if (ieee754_cxtest(IEEE754_OVERFLOW))
1639                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1640                         if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
1641                                 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1642                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1643                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1644                         break;
1645
1646                         /* unary conv ops */
1647                 case fcvts_op:
1648                         return SIGILL;  /* not defined */
1649                 case fcvtd_op:{
1650                         ieee754sp fs;
1651
1652                         SPFROMREG(fs, MIPSInst_FS(ir));
1653                         rv.d = ieee754dp_fsp(fs);
1654                         rfmt = d_fmt;
1655                         goto copcsr;
1656                 }
1657                 case fcvtw_op:{
1658                         ieee754sp fs;
1659
1660                         SPFROMREG(fs, MIPSInst_FS(ir));
1661                         rv.w = ieee754sp_tint(fs);
1662                         rfmt = w_fmt;
1663                         goto copcsr;
1664                 }
1665
1666 #if __mips >= 2 || defined(__mips64)
1667                 case fround_op:
1668                 case ftrunc_op:
1669                 case fceil_op:
1670                 case ffloor_op:{
1671                         unsigned int oldrm = ieee754_csr.rm;
1672                         ieee754sp fs;
1673
1674                         SPFROMREG(fs, MIPSInst_FS(ir));
1675                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1676                         rv.w = ieee754sp_tint(fs);
1677                         ieee754_csr.rm = oldrm;
1678                         rfmt = w_fmt;
1679                         goto copcsr;
1680                 }
1681 #endif /* __mips >= 2 */
1682
1683 #if defined(__mips64)
1684                 case fcvtl_op:{
1685                         ieee754sp fs;
1686
1687                         SPFROMREG(fs, MIPSInst_FS(ir));
1688                         rv.l = ieee754sp_tlong(fs);
1689                         rfmt = l_fmt;
1690                         goto copcsr;
1691                 }
1692
1693                 case froundl_op:
1694                 case ftruncl_op:
1695                 case fceill_op:
1696                 case ffloorl_op:{
1697                         unsigned int oldrm = ieee754_csr.rm;
1698                         ieee754sp fs;
1699
1700                         SPFROMREG(fs, MIPSInst_FS(ir));
1701                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1702                         rv.l = ieee754sp_tlong(fs);
1703                         ieee754_csr.rm = oldrm;
1704                         rfmt = l_fmt;
1705                         goto copcsr;
1706                 }
1707 #endif /* defined(__mips64) */
1708
1709                 default:
1710                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1711                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1712                                 ieee754sp fs, ft;
1713
1714                                 SPFROMREG(fs, MIPSInst_FS(ir));
1715                                 SPFROMREG(ft, MIPSInst_FT(ir));
1716                                 rv.w = ieee754sp_cmp(fs, ft,
1717                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1718                                 rfmt = -1;
1719                                 if ((cmpop & 0x8) && ieee754_cxtest
1720                                         (IEEE754_INVALID_OPERATION))
1721                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1722                                 else
1723                                         goto copcsr;
1724
1725                         }
1726                         else {
1727                                 return SIGILL;
1728                         }
1729                         break;
1730                 }
1731                 break;
1732         }
1733
1734         case d_fmt:{
1735                 union {
1736                         ieee754dp(*b) (ieee754dp, ieee754dp);
1737                         ieee754dp(*u) (ieee754dp);
1738                 } handler;
1739
1740                 switch (MIPSInst_FUNC(ir)) {
1741                         /* binary ops */
1742                 case fadd_op:
1743                         handler.b = ieee754dp_add;
1744                         goto dcopbop;
1745                 case fsub_op:
1746                         handler.b = ieee754dp_sub;
1747                         goto dcopbop;
1748                 case fmul_op:
1749                         handler.b = ieee754dp_mul;
1750                         goto dcopbop;
1751                 case fdiv_op:
1752                         handler.b = ieee754dp_div;
1753                         goto dcopbop;
1754
1755                         /* unary  ops */
1756 #if __mips >= 2 || defined(__mips64)
1757                 case fsqrt_op:
1758                         handler.u = ieee754dp_sqrt;
1759                         goto dcopuop;
1760 #endif
1761 #if __mips >= 4 && __mips != 32
1762                 case frsqrt_op:
1763                         handler.u = fpemu_dp_rsqrt;
1764                         goto dcopuop;
1765                 case frecip_op:
1766                         handler.u = fpemu_dp_recip;
1767                         goto dcopuop;
1768 #endif
1769 #if __mips >= 4
1770                 case fmovc_op:
1771                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1772                         if (((ctx->fcr31 & cond) != 0) !=
1773                                 ((MIPSInst_FT(ir) & 1) != 0))
1774                                 return 0;
1775                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1776                         break;
1777                 case fmovz_op:
1778                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1779                                 return 0;
1780                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1781                         break;
1782                 case fmovn_op:
1783                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1784                                 return 0;
1785                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1786                         break;
1787 #endif
1788                 case fabs_op:
1789                         handler.u = ieee754dp_abs;
1790                         goto dcopuop;
1791
1792                 case fneg_op:
1793                         handler.u = ieee754dp_neg;
1794                         goto dcopuop;
1795
1796                 case fmov_op:
1797                         /* an easy one */
1798                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1799                         goto copcsr;
1800
1801                         /* binary op on handler */
1802                       dcopbop:{
1803                                 ieee754dp fs, ft;
1804
1805                                 DPFROMREG(fs, MIPSInst_FS(ir));
1806                                 DPFROMREG(ft, MIPSInst_FT(ir));
1807
1808                                 rv.d = (*handler.b) (fs, ft);
1809                                 goto copcsr;
1810                         }
1811                       dcopuop:{
1812                                 ieee754dp fs;
1813
1814                                 DPFROMREG(fs, MIPSInst_FS(ir));
1815                                 rv.d = (*handler.u) (fs);
1816                                 goto copcsr;
1817                         }
1818
1819                         /* unary conv ops */
1820                 case fcvts_op:{
1821                         ieee754dp fs;
1822
1823                         DPFROMREG(fs, MIPSInst_FS(ir));
1824                         rv.s = ieee754sp_fdp(fs);
1825                         rfmt = s_fmt;
1826                         goto copcsr;
1827                 }
1828                 case fcvtd_op:
1829                         return SIGILL;  /* not defined */
1830
1831                 case fcvtw_op:{
1832                         ieee754dp fs;
1833
1834                         DPFROMREG(fs, MIPSInst_FS(ir));
1835                         rv.w = ieee754dp_tint(fs);      /* wrong */
1836                         rfmt = w_fmt;
1837                         goto copcsr;
1838                 }
1839
1840 #if __mips >= 2 || defined(__mips64)
1841                 case fround_op:
1842                 case ftrunc_op:
1843                 case fceil_op:
1844                 case ffloor_op:{
1845                         unsigned int oldrm = ieee754_csr.rm;
1846                         ieee754dp fs;
1847
1848                         DPFROMREG(fs, MIPSInst_FS(ir));
1849                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1850                         rv.w = ieee754dp_tint(fs);
1851                         ieee754_csr.rm = oldrm;
1852                         rfmt = w_fmt;
1853                         goto copcsr;
1854                 }
1855 #endif
1856
1857 #if defined(__mips64)
1858                 case fcvtl_op:{
1859                         ieee754dp fs;
1860
1861                         DPFROMREG(fs, MIPSInst_FS(ir));
1862                         rv.l = ieee754dp_tlong(fs);
1863                         rfmt = l_fmt;
1864                         goto copcsr;
1865                 }
1866
1867                 case froundl_op:
1868                 case ftruncl_op:
1869                 case fceill_op:
1870                 case ffloorl_op:{
1871                         unsigned int oldrm = ieee754_csr.rm;
1872                         ieee754dp fs;
1873
1874                         DPFROMREG(fs, MIPSInst_FS(ir));
1875                         ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1876                         rv.l = ieee754dp_tlong(fs);
1877                         ieee754_csr.rm = oldrm;
1878                         rfmt = l_fmt;
1879                         goto copcsr;
1880                 }
1881 #endif /* __mips >= 3 */
1882
1883                 default:
1884                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1885                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1886                                 ieee754dp fs, ft;
1887
1888                                 DPFROMREG(fs, MIPSInst_FS(ir));
1889                                 DPFROMREG(ft, MIPSInst_FT(ir));
1890                                 rv.w = ieee754dp_cmp(fs, ft,
1891                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1892                                 rfmt = -1;
1893                                 if ((cmpop & 0x8)
1894                                         &&
1895                                         ieee754_cxtest
1896                                         (IEEE754_INVALID_OPERATION))
1897                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1898                                 else
1899                                         goto copcsr;
1900
1901                         }
1902                         else {
1903                                 return SIGILL;
1904                         }
1905                         break;
1906                 }
1907                 break;
1908         }
1909
1910         case w_fmt:{
1911                 ieee754sp fs;
1912
1913                 switch (MIPSInst_FUNC(ir)) {
1914                 case fcvts_op:
1915                         /* convert word to single precision real */
1916                         SPFROMREG(fs, MIPSInst_FS(ir));
1917                         rv.s = ieee754sp_fint(fs.bits);
1918                         rfmt = s_fmt;
1919                         goto copcsr;
1920                 case fcvtd_op:
1921                         /* convert word to double precision real */
1922                         SPFROMREG(fs, MIPSInst_FS(ir));
1923                         rv.d = ieee754dp_fint(fs.bits);
1924                         rfmt = d_fmt;
1925                         goto copcsr;
1926                 default:
1927                         return SIGILL;
1928                 }
1929                 break;
1930         }
1931
1932 #if defined(__mips64)
1933         case l_fmt:{
1934                 switch (MIPSInst_FUNC(ir)) {
1935                 case fcvts_op:
1936                         /* convert long to single precision real */
1937                         rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1938                         rfmt = s_fmt;
1939                         goto copcsr;
1940                 case fcvtd_op:
1941                         /* convert long to double precision real */
1942                         rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1943                         rfmt = d_fmt;
1944                         goto copcsr;
1945                 default:
1946                         return SIGILL;
1947                 }
1948                 break;
1949         }
1950 #endif
1951
1952         default:
1953                 return SIGILL;
1954         }
1955
1956         /*
1957          * Update the fpu CSR register for this operation.
1958          * If an exception is required, generate a tidy SIGFPE exception,
1959          * without updating the result register.
1960          * Note: cause exception bits do not accumulate, they are rewritten
1961          * for each op; only the flag/sticky bits accumulate.
1962          */
1963         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1964         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1965                 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1966                 return SIGFPE;
1967         }
1968
1969         /*
1970          * Now we can safely write the result back to the register file.
1971          */
1972         switch (rfmt) {
1973         case -1:{
1974 #if __mips >= 4
1975                 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
1976 #else
1977                 cond = FPU_CSR_COND;
1978 #endif
1979                 if (rv.w)
1980                         ctx->fcr31 |= cond;
1981                 else
1982                         ctx->fcr31 &= ~cond;
1983                 break;
1984         }
1985         case d_fmt:
1986                 DPTOREG(rv.d, MIPSInst_FD(ir));
1987                 break;
1988         case s_fmt:
1989                 SPTOREG(rv.s, MIPSInst_FD(ir));
1990                 break;
1991         case w_fmt:
1992                 SITOREG(rv.w, MIPSInst_FD(ir));
1993                 break;
1994 #if defined(__mips64)
1995         case l_fmt:
1996                 DITOREG(rv.l, MIPSInst_FD(ir));
1997                 break;
1998 #endif
1999         default:
2000                 return SIGILL;
2001         }
2002
2003         return 0;
2004 }
2005
2006 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2007         int has_fpu, void *__user *fault_addr)
2008 {
2009         unsigned long oldepc, prevepc;
2010         struct mm_decoded_insn dec_insn;
2011         u16 instr[4];
2012         u16 *instr_ptr;
2013         int sig = 0;
2014
2015         oldepc = xcp->cp0_epc;
2016         do {
2017                 prevepc = xcp->cp0_epc;
2018
2019                 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2020                         /*
2021                          * Get next 2 microMIPS instructions and convert them
2022                          * into 32-bit instructions.
2023                          */
2024                         if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2025                             (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2026                             (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2027                             (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2028                                 MIPS_FPU_EMU_INC_STATS(errors);
2029                                 return SIGBUS;
2030                         }
2031                         instr_ptr = instr;
2032
2033                         /* Get first instruction. */
2034                         if (mm_insn_16bit(*instr_ptr)) {
2035                                 /* Duplicate the half-word. */
2036                                 dec_insn.insn = (*instr_ptr << 16) |
2037                                         (*instr_ptr);
2038                                 /* 16-bit instruction. */
2039                                 dec_insn.pc_inc = 2;
2040                                 instr_ptr += 1;
2041                         } else {
2042                                 dec_insn.insn = (*instr_ptr << 16) |
2043                                         *(instr_ptr+1);
2044                                 /* 32-bit instruction. */
2045                                 dec_insn.pc_inc = 4;
2046                                 instr_ptr += 2;
2047                         }
2048                         /* Get second instruction. */
2049                         if (mm_insn_16bit(*instr_ptr)) {
2050                                 /* Duplicate the half-word. */
2051                                 dec_insn.next_insn = (*instr_ptr << 16) |
2052                                         (*instr_ptr);
2053                                 /* 16-bit instruction. */
2054                                 dec_insn.next_pc_inc = 2;
2055                         } else {
2056                                 dec_insn.next_insn = (*instr_ptr << 16) |
2057                                         *(instr_ptr+1);
2058                                 /* 32-bit instruction. */
2059                                 dec_insn.next_pc_inc = 4;
2060                         }
2061                         dec_insn.micro_mips_mode = 1;
2062                 } else {
2063                         if ((get_user(dec_insn.insn,
2064                             (mips_instruction __user *) xcp->cp0_epc)) ||
2065                             (get_user(dec_insn.next_insn,
2066                             (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2067                                 MIPS_FPU_EMU_INC_STATS(errors);
2068                                 return SIGBUS;
2069                         }
2070                         dec_insn.pc_inc = 4;
2071                         dec_insn.next_pc_inc = 4;
2072                         dec_insn.micro_mips_mode = 0;
2073                 }
2074
2075                 if ((dec_insn.insn == 0) ||
2076                    ((dec_insn.pc_inc == 2) &&
2077                    ((dec_insn.insn & 0xffff) == MM_NOP16)))
2078                         xcp->cp0_epc += dec_insn.pc_inc;        /* Skip NOPs */
2079                 else {
2080                         /*
2081                          * The 'ieee754_csr' is an alias of
2082                          * ctx->fcr31.  No need to copy ctx->fcr31 to
2083                          * ieee754_csr.  But ieee754_csr.rm is ieee
2084                          * library modes. (not mips rounding mode)
2085                          */
2086                         /* convert to ieee library modes */
2087                         ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
2088                         sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2089                         /* revert to mips rounding mode */
2090                         ieee754_csr.rm = mips_rm[ieee754_csr.rm];
2091                 }
2092
2093                 if (has_fpu)
2094                         break;
2095                 if (sig)
2096                         break;
2097
2098                 cond_resched();
2099         } while (xcp->cp0_epc > prevepc);
2100
2101         /* SIGILL indicates a non-fpu instruction */
2102         if (sig == SIGILL && xcp->cp0_epc != oldepc)
2103                 /* but if epc has advanced, then ignore it */
2104                 sig = 0;
2105
2106         return sig;
2107 }
2108
2109 #ifdef CONFIG_DEBUG_FS
2110
2111 static int fpuemu_stat_get(void *data, u64 *val)
2112 {
2113         int cpu;
2114         unsigned long sum = 0;
2115         for_each_online_cpu(cpu) {
2116                 struct mips_fpu_emulator_stats *ps;
2117                 local_t *pv;
2118                 ps = &per_cpu(fpuemustats, cpu);
2119                 pv = (void *)ps + (unsigned long)data;
2120                 sum += local_read(pv);
2121         }
2122         *val = sum;
2123         return 0;
2124 }
2125 DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
2126
2127 extern struct dentry *mips_debugfs_dir;
2128 static int __init debugfs_fpuemu(void)
2129 {
2130         struct dentry *d, *dir;
2131
2132         if (!mips_debugfs_dir)
2133                 return -ENODEV;
2134         dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
2135         if (!dir)
2136                 return -ENOMEM;
2137
2138 #define FPU_STAT_CREATE(M)                                              \
2139         do {                                                            \
2140                 d = debugfs_create_file(#M , S_IRUGO, dir,              \
2141                         (void *)offsetof(struct mips_fpu_emulator_stats, M), \
2142                         &fops_fpuemu_stat);                             \
2143                 if (!d)                                                 \
2144                         return -ENOMEM;                                 \
2145         } while (0)
2146
2147         FPU_STAT_CREATE(emulated);
2148         FPU_STAT_CREATE(loads);
2149         FPU_STAT_CREATE(stores);
2150         FPU_STAT_CREATE(cp1ops);
2151         FPU_STAT_CREATE(cp1xops);
2152         FPU_STAT_CREATE(errors);
2153
2154         return 0;
2155 }
2156 __initcall(debugfs_fpuemu);
2157 #endif