1 // SPDX-License-Identifier: GPL-2.0+
4 * Purna Chandra Mandal <purna.mandal@microchip.com>
12 #include <mach/pic32.h>
14 #include <dt-bindings/clock/microchip,clock.h>
23 #define CLK_MHZ(x) ((x) / 1000000)
25 DECLARE_GLOBAL_DATA_PTR;
27 static ulong rate(int id)
34 ret = uclass_get_device(UCLASS_CLK, 0, &dev);
36 printf("clk-uclass not found\n");
41 ret = clk_request(dev, &clk);
45 rate = clk_get_rate(&clk);
52 static ulong clk_get_cpu_rate(void)
57 /* initialize prefetch module related to cpu_clk */
58 static void prefetch_init(void)
60 struct pic32_reg_atomic *regs;
61 const void __iomem *base;
65 /* cpu frequency in MHZ */
66 rate = clk_get_cpu_rate() / 1000000;
68 /* get flash ECC type */
69 base = pic32_get_syscfg_base();
70 v = (readl(base + CFGCON) >> ECC_SHIFT) & ECC_MASK;
88 regs = ioremap(PREFETCH_BASE + PRECON, sizeof(*regs));
89 writel(nr_waits, ®s->raw);
91 /* Enable prefetch for all */
92 writel(0x30, ®s->set);
96 /* arch specific CPU init after DM */
97 int arch_cpu_init_dm(void)
104 /* Un-gate DDR2 modules (gated by default) */
105 static void ddr2_pmd_ungate(void)
109 regs = pic32_get_syscfg_base();
110 writel(0, regs + PMD7);
113 /* initialize the DDR2 Controller and DDR2 PHY */
119 gd->ram_size = ddr2_calculate_size();
124 int misc_init_r(void)
130 #ifdef CONFIG_DISPLAY_BOARDINFO
131 const char *get_core_name(void)
136 proc_id = read_c0_prid();
148 #ifdef CONFIG_CMD_CLK
150 int soc_clk_dump(void)
154 printf("PLL Speed: %lu MHz\n",
155 CLK_MHZ(rate(PLLCLK)));
157 printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK)));
159 printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL)));
161 for (i = PB1CLK; i <= PB7CLK; i++)
162 printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
165 for (i = REF1CLK; i <= REF5CLK; i++)
166 printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,