1 // SPDX-License-Identifier: GPL-2.0+
3 * JZ4780 DDR initialization
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
8 * Based on spl/common/{jz4780_ddr,jz_ddr3_init}.c from X-Boot
9 * Copyright (c) 2006-2013 Ingenic Semiconductor
16 #include <mach/jz4780.h>
17 #include <mach/jz4780_dram.h>
19 static const u32 get_mem_clk(void)
21 const u32 mpll_out = ((u64)JZ4780_SYS_EXTAL * JZ4780_MPLL_M) /
22 (JZ4780_MPLL_N * JZ4780_MPLL_OD);
23 return mpll_out / JZ4780_SYS_MEM_DIV;
26 u32 sdram_size(int cs)
28 u32 dw = DDR_DW32 ? 4 : 2;
29 u32 banks = DDR_BANK8 ? 8 : 4;
32 if ((cs == 0) && DDR_CS0EN) {
33 size = (1 << (DDR_ROW + DDR_COL)) * dw * banks;
34 if (DDR_CS1EN && (size > 0x20000000))
36 } else if ((cs == 1) && DDR_CS1EN) {
37 size = (1 << (DDR_ROW + DDR_COL)) * dw * banks;
43 static void ddr_cfg_init(void)
45 void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE;
54 ddrc_cfg = DDRC_CFG_TYPE_DDR3 | DDRC_CFG_IMBA |
55 DDR_DW32 | DDRC_CFG_MPRT | ((tmp | 0x8) << 2) |
56 ((DDR_ROW - 12) << 11) | ((DDR_COL - 8) << 8) |
57 (DDR_CS0EN << 6) | (DDR_BANK8 << 1) |
58 ((DDR_ROW - 12) << 27) | ((DDR_COL - 8) << 24) |
59 (DDR_CS1EN << 7) | (DDR_BANK8 << 23);
64 writel(ddrc_cfg, ddr_ctl_regs + DDRC_CFG);
67 static void ddr_phy_init(const struct jz4780_ddr_config *ddr_config)
69 void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE;
70 void __iomem *ddr_phy_regs = ddr_ctl_regs + DDR_PHY_OFFSET;
71 unsigned int count = 0, i;
74 writel(DDRP_DCR_TYPE_DDR3 | (DDR_BANK8 << 3), ddr_phy_regs + DDRP_DCR);
76 writel(ddr_config->mr0, ddr_phy_regs + DDRP_MR0);
77 writel(ddr_config->mr1, ddr_phy_regs + DDRP_MR1);
78 writel(0, ddr_phy_regs + DDRP_ODTCR);
79 writel(0, ddr_phy_regs + DDRP_MR2);
81 writel(ddr_config->ptr0, ddr_phy_regs + DDRP_PTR0);
82 writel(ddr_config->ptr1, ddr_phy_regs + DDRP_PTR1);
83 writel(ddr_config->ptr2, ddr_phy_regs + DDRP_PTR2);
85 writel(ddr_config->dtpr0, ddr_phy_regs + DDRP_DTPR0);
86 writel(ddr_config->dtpr1, ddr_phy_regs + DDRP_DTPR1);
87 writel(ddr_config->dtpr2, ddr_phy_regs + DDRP_DTPR2);
89 writel(DDRP_PGCR_DQSCFG | (7 << DDRP_PGCR_CKEN_BIT) |
90 (2 << DDRP_PGCR_CKDV_BIT) |
91 (DDR_CS0EN | (DDR_CS1EN << 1)) << DDRP_PGCR_RANKEN_BIT |
92 DDRP_PGCR_ZCKSEL_32 | DDRP_PGCR_PDDISDX,
93 ddr_phy_regs + DDRP_PGCR);
95 for (i = 0; i < 8; i++)
96 clrbits_le32(ddr_phy_regs + DDRP_DXGCR(i), 0x3 << 9);
99 mask = DDRP_PGSR_IDONE | DDRP_PGSR_DLDONE | DDRP_PGSR_ZCDONE;
101 reg = readl(ddr_phy_regs + DDRP_PGSR);
102 if ((reg == mask) || (reg == 0x1f))
104 if (count++ == 10000)
108 /* DQS extension and early set to 1 */
109 clrsetbits_le32(ddr_phy_regs + DDRP_DSGCR, 0x7E << 4, 0x12 << 4);
111 /* 500 pull up and 500 pull down */
112 clrsetbits_le32(ddr_phy_regs + DDRP_DXCCR, 0xFF << 4, 0xC4 << 4);
115 writel(DDRP_PIR_INIT | DDRP_PIR_DRAMINT | DDRP_PIR_DRAMRST,
116 ddr_phy_regs + DDRP_PIR);
119 mask |= DDRP_PGSR_DIDONE;
121 reg = readl(ddr_phy_regs + DDRP_PGSR);
122 if ((reg == mask) || (reg == 0x1f))
124 if (count++ == 20000)
128 writel(DDRP_PIR_INIT | DDRP_PIR_QSTRN, ddr_phy_regs + DDRP_PIR);
131 mask |= DDRP_PGSR_DTDONE;
133 reg = readl(ddr_phy_regs + DDRP_PGSR);
136 if (count++ != 50000)
138 reg &= DDRP_PGSR_DTDONE | DDRP_PGSR_DTERR | DDRP_PGSR_DTIERR;
144 /* Override impedance */
145 clrsetbits_le32(ddr_phy_regs + DDRP_ZQXCR0(0), 0x3ff,
146 ((ddr_config->pullup & 0x1f) << DDRP_ZQXCR_PULLUP_IMPE_BIT) |
147 ((ddr_config->pulldn & 0x1f) << DDRP_ZQXCR_PULLDOWN_IMPE_BIT) |
151 #define JZBIT(bit) ((bit % 4) * 8)
152 #define JZMASK(bit) (0x1f << JZBIT(bit))
154 static void remap_swap(int a, int b)
156 void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE;
157 u32 remmap[2], tmp[2];
159 remmap[0] = readl(ddr_ctl_regs + DDRC_REMMAP(a / 4));
160 remmap[1] = readl(ddr_ctl_regs + DDRC_REMMAP(b / 4));
162 tmp[0] = (remmap[0] & JZMASK(a)) >> JZBIT(a);
163 tmp[1] = (remmap[1] & JZMASK(b)) >> JZBIT(b);
165 remmap[0] &= ~JZMASK(a);
166 remmap[1] &= ~JZMASK(b);
168 writel(remmap[0] | (tmp[1] << JZBIT(a)),
169 ddr_ctl_regs + DDRC_REMMAP(a / 4));
170 writel(remmap[1] | (tmp[0] << JZBIT(b)),
171 ddr_ctl_regs + DDRC_REMMAP(b / 4));
174 static void mem_remap(void)
176 u32 start = (DDR_ROW + DDR_COL + (DDR_DW32 ? 4 : 2) / 2) - 12;
177 u32 num = DDR_BANK8 ? 3 : 2;
179 if (DDR_CS0EN && DDR_CS1EN)
182 for (; num > 0; num--)
183 remap_swap(0 + num - 1, start + num - 1);
186 /* Fetch DRAM config from board file */
187 __weak const struct jz4780_ddr_config *jz4780_get_ddr_config(void)
192 void sdram_init(void)
194 const struct jz4780_ddr_config *ddr_config = jz4780_get_ddr_config();
195 void __iomem *ddr_ctl_regs = (void __iomem *)DDRC_BASE;
196 void __iomem *ddr_phy_regs = ddr_ctl_regs + DDR_PHY_OFFSET;
197 void __iomem *cpm_regs = (void __iomem *)CPM_BASE;
199 u32 mem_base0, mem_base1;
200 u32 mem_mask0, mem_mask1;
201 u32 mem_size0, mem_size1;
206 /* Reset DLL in DDR PHY */
207 writel(0x3, cpm_regs + 0xd0);
209 writel(0x1, cpm_regs + 0xd0);
213 writel(0xf << 20, ddr_ctl_regs + DDRC_CTRL);
215 mem_clk = get_mem_clk();
217 tmp = 1000000000 / mem_clk;
218 if (1000000000 % mem_clk)
220 tmp = DDR_tREFI / tmp;
221 tmp = tmp / (16 * (1 << DDR_CLK_DIV)) - 1;
227 writel(0x0, ddr_ctl_regs + DDRC_CTRL);
229 writel(0x150000, ddr_phy_regs + DDRP_DTAR);
230 ddr_phy_init(ddr_config);
232 writel(DDRC_CTRL_CKE | DDRC_CTRL_ALH, ddr_ctl_regs + DDRC_CTRL);
233 writel(0x0, ddr_ctl_regs + DDRC_CTRL);
237 for (i = 0; i < 6; i++)
238 writel(ddr_config->timing[i], ddr_ctl_regs + DDRC_TIMING(i));
240 mem_size0 = sdram_size(0);
241 mem_size1 = sdram_size(1);
243 if (!mem_size1 && mem_size0 > 0x20000000) {
245 mem_mask0 = ~(((mem_size0 * 2) >> 24) - 1) & DDRC_MMAP_MASK_MASK;
247 mem_base0 = (DDR_MEM_PHY_BASE >> 24) & 0xff;
248 mem_mask0 = ~((mem_size0 >> 24) - 1) & DDRC_MMAP_MASK_MASK;
252 mem_mask1 = ~((mem_size1 >> 24) - 1) & DDRC_MMAP_MASK_MASK;
253 mem_base1 = ((DDR_MEM_PHY_BASE + mem_size0) >> 24) & 0xff;
259 writel(mem_base0 << DDRC_MMAP_BASE_BIT | mem_mask0,
260 ddr_ctl_regs + DDRC_MMAP0);
261 writel(mem_base1 << DDRC_MMAP_BASE_BIT | mem_mask1,
262 ddr_ctl_regs + DDRC_MMAP1);
263 writel(DDRC_CTRL_CKE | DDRC_CTRL_ALH, ddr_ctl_regs + DDRC_CTRL);
264 writel((DDR_CLK_DIV << 1) | DDRC_REFCNT_REF_EN |
265 (tmp << DDRC_REFCNT_CON_BIT),
266 ddr_ctl_regs + DDRC_REFCNT);
267 writel((1 << 15) | (4 << 12) | (1 << 11) | (1 << 8) | (0 << 6) |
268 (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1),
269 ddr_ctl_regs + DDRC_CTRL);
271 clrbits_le32(ddr_ctl_regs + DDRC_ST, 0x40);