arch/mips/kernel/ptrace.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1992 Ross Biro
   7  * Copyright (C) Linus Torvalds
   8  * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
   9  * Copyright (C) 1996 David S. Miller
  10  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  11  * Copyright (C) 1999 MIPS Technologies, Inc.
  12  * Copyright (C) 2000 Ulf Carlsson
  13  *
  14  * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
  15  * binaries.
  16  */
  17 #include <linux/compiler.h>
  18 #include <linux/kernel.h>
  19 #include <linux/sched.h>
  20 #include <linux/mm.h>
  21 #include <linux/errno.h>
  22 #include <linux/ptrace.h>
  23 #include <linux/smp.h>
  24 #include <linux/user.h>
  25 #include <linux/security.h>
  26 #include <linux/audit.h>
  27 #include <linux/seccomp.h>
  28
  29 #include <asm/byteorder.h>
  30 #include <asm/cpu.h>
  31 #include <asm/dsp.h>
  32 #include <asm/fpu.h>
  33 #include <asm/mipsregs.h>
  34 #include <asm/mipsmtregs.h>
  35 #include <asm/pgtable.h>
  36 #include <asm/page.h>
  37 #include <asm/system.h>
  38 #include <asm/uaccess.h>
  39 #include <asm/bootinfo.h>
  40 #include <asm/reg.h>
  41
  42 /*
  43  * Called by kernel/ptrace.c when detaching..
  44  *
  45  * Make sure single step bits etc are not set.
  46  */
  47 void ptrace_disable(struct task_struct *child)
  48 {
  49         /* Don't load the watchpoint registers for the ex-child. */
  50         clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
  51 }
  52
  53 /*
  54  * Read a general register set.  We always use the 64-bit format, even
  55  * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
  56  * Registers are sign extended to fill the available space.
  57  */
  58 int ptrace_getregs(struct task_struct *child, __s64 __user *data)
  59 {
  60         struct pt_regs *regs;
  61         int i;
  62
  63         if (!access_ok(VERIFY_WRITE, data, 38 * 8))
  64                 return -EIO;
  65
  66         regs = task_pt_regs(child);
  67
  68         for (i = 0; i < 32; i++)
  69                 __put_user((long)regs->regs[i], data + i);
  70         __put_user((long)regs->lo, data + EF_LO - EF_R0);
  71         __put_user((long)regs->hi, data + EF_HI - EF_R0);
  72         __put_user((long)regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
  73         __put_user((long)regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
  74         __put_user((long)regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
  75         __put_user((long)regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);
  76
  77         return 0;
  78 }
  79
  80 /*
  81  * Write a general register set.  As for PTRACE_GETREGS, we always use
  82  * the 64-bit format.  On a 32-bit kernel only the lower order half
  83  * (according to endianness) will be used.
  84  */
  85 int ptrace_setregs(struct task_struct *child, __s64 __user *data)
  86 {
  87         struct pt_regs *regs;
  88         int i;
  89
  90         if (!access_ok(VERIFY_READ, data, 38 * 8))
  91                 return -EIO;
  92
  93         regs = task_pt_regs(child);
  94
  95         for (i = 0; i < 32; i++)
  96                 __get_user(regs->regs[i], data + i);
  97         __get_user(regs->lo, data + EF_LO - EF_R0);
  98         __get_user(regs->hi, data + EF_HI - EF_R0);
  99         __get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
 100
 101         /* badvaddr, status, and cause may not be written.  */
 102
 103         return 0;
 104 }
 105
 106 int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
 107 {
 108         int i;
 109         unsigned int tmp;
 110
 111         if (!access_ok(VERIFY_WRITE, data, 33 * 8))
 112                 return -EIO;
 113
 114         if (tsk_used_math(child)) {
 115                 fpureg_t *fregs = get_fpu_regs(child);
 116                 for (i = 0; i < 32; i++)
 117                         __put_user(fregs[i], i + (__u64 __user *) data);
 118         } else {
 119                 for (i = 0; i < 32; i++)
 120                         __put_user((__u64) -1, i + (__u64 __user *) data);
 121         }
 122
 123         __put_user(child->thread.fpu.fcr31, data + 64);
 124
 125         preempt_disable();
 126         if (cpu_has_fpu) {
 127                 unsigned int flags;
 128
 129                 if (cpu_has_mipsmt) {
 130                         unsigned int vpflags = dvpe();
 131                         flags = read_c0_status();
 132                         __enable_fpu();
 133                         __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
 134                         write_c0_status(flags);
 135                         evpe(vpflags);
 136                 } else {
 137                         flags = read_c0_status();
 138                         __enable_fpu();
 139                         __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
 140                         write_c0_status(flags);
 141                 }
 142         } else {
 143                 tmp = 0;
 144         }
 145         preempt_enable();
 146         __put_user(tmp, data + 65);
 147
 148         return 0;
 149 }
 150
 151 int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
 152 {
 153         fpureg_t *fregs;
 154         int i;
 155
 156         if (!access_ok(VERIFY_READ, data, 33 * 8))
 157                 return -EIO;
 158
 159         fregs = get_fpu_regs(child);
 160
 161         for (i = 0; i < 32; i++)
 162                 __get_user(fregs[i], i + (__u64 __user *) data);
 163
 164         __get_user(child->thread.fpu.fcr31, data + 64);
 165         child->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
 166
 167         /* FIR may not be written.  */
 168
 169         return 0;
 170 }
 171
 172 int ptrace_get_watch_regs(struct task_struct *child,
 173                           struct pt_watch_regs __user *addr)
 174 {
 175         enum pt_watch_style style;
 176         int i;
 177
 178         if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
 179                 return -EIO;
 180         if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
 181                 return -EIO;
 182
 183 #ifdef CONFIG_32BIT
 184         style = pt_watch_style_mips32;
 185 #define WATCH_STYLE mips32
 186 #else
 187         style = pt_watch_style_mips64;
 188 #define WATCH_STYLE mips64
 189 #endif
 190
 191         __put_user(style, &addr->style);
 192         __put_user(current_cpu_data.watch_reg_use_cnt,
 193                    &addr->WATCH_STYLE.num_valid);
 194         for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
 195                 __put_user(child->thread.watch.mips3264.watchlo[i],
 196                            &addr->WATCH_STYLE.watchlo[i]);
 197                 __put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
 198                            &addr->WATCH_STYLE.watchhi[i]);
 199                 __put_user(current_cpu_data.watch_reg_masks[i],
 200                            &addr->WATCH_STYLE.watch_masks[i]);
 201         }
 202         for (; i < 8; i++) {
 203                 __put_user(0, &addr->WATCH_STYLE.watchlo[i]);
 204                 __put_user(0, &addr->WATCH_STYLE.watchhi[i]);
 205                 __put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
 206         }
 207
 208         return 0;
 209 }
 210
 211 int ptrace_set_watch_regs(struct task_struct *child,
 212                           struct pt_watch_regs __user *addr)
 213 {
 214         int i;
 215         int watch_active = 0;
 216         unsigned long lt[NUM_WATCH_REGS];
 217         u16 ht[NUM_WATCH_REGS];
 218
 219         if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
 220                 return -EIO;
 221         if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
 222                 return -EIO;
 223         /* Check the values. */
 224         for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
 225                 __get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
 226 #ifdef CONFIG_32BIT
 227                 if (lt[i] & __UA_LIMIT)
 228                         return -EINVAL;
 229 #else
 230                 if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
 231                         if (lt[i] & 0xffffffff80000000UL)
 232                                 return -EINVAL;
 233                 } else {
 234                         if (lt[i] & __UA_LIMIT)
 235                                 return -EINVAL;
 236                 }
 237 #endif
 238                 __get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
 239                 if (ht[i] & ~0xff8)
 240                         return -EINVAL;
 241         }
 242         /* Install them. */
 243         for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
 244                 if (lt[i] & 7)
 245                         watch_active = 1;
 246                 child->thread.watch.mips3264.watchlo[i] = lt[i];
 247                 /* Set the G bit. */
 248                 child->thread.watch.mips3264.watchhi[i] = ht[i];
 249         }
 250
 251         if (watch_active)
 252                 set_tsk_thread_flag(child, TIF_LOAD_WATCH);
 253         else
 254                 clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
 255
 256         return 0;
 257 }
 258
 259 long arch_ptrace(struct task_struct *child, long request,
 260                  unsigned long addr, unsigned long data)
 261 {
 262         int ret;
 263         void __user *addrp = (void __user *) addr;
 264         void __user *datavp = (void __user *) data;
 265         unsigned long __user *datalp = (void __user *) data;
 266
 267         switch (request) {
 268         /* when I and D space are separate, these will need to be fixed. */
 269         case PTRACE_PEEKTEXT: /* read word at location addr. */
 270         case PTRACE_PEEKDATA:
 271                 ret = generic_ptrace_peekdata(child, addr, data);
 272                 break;
 273
 274         /* Read the word at location addr in the USER area. */
 275         case PTRACE_PEEKUSR: {
 276                 struct pt_regs *regs;
 277                 unsigned long tmp = 0;
 278
 279                 regs = task_pt_regs(child);
 280                 ret = 0;  /* Default return value. */
 281
 282                 switch (addr) {
 283                 case 0 ... 31:
 284                         tmp = regs->regs[addr];
 285                         break;
 286                 case FPR_BASE ... FPR_BASE + 31:
 287                         if (tsk_used_math(child)) {
 288                                 fpureg_t *fregs = get_fpu_regs(child);
 289
 290 #ifdef CONFIG_32BIT
 291                                 /*
 292                                  * The odd registers are actually the high
 293                                  * order bits of the values stored in the even
 294                                  * registers - unless we're using r2k_switch.S.
 295                                  */
 296                                 if (addr & 1)
 297                                         tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32);
 298                                 else
 299                                         tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff);
 300 #endif
 301 #ifdef CONFIG_64BIT
 302                                 tmp = fregs[addr - FPR_BASE];
 303 #endif
 304                         } else {
 305                                 tmp = -1;       /* FP not yet used  */
 306                         }
 307                         break;
 308                 case PC:
 309                         tmp = regs->cp0_epc;
 310                         break;
 311                 case CAUSE:
 312                         tmp = regs->cp0_cause;
 313                         break;
 314                 case BADVADDR:
 315                         tmp = regs->cp0_badvaddr;
 316                         break;
 317                 case MMHI:
 318                         tmp = regs->hi;
 319                         break;
 320                 case MMLO:
 321                         tmp = regs->lo;
 322                         break;
 323 #ifdef CONFIG_CPU_HAS_SMARTMIPS
 324                 case ACX:
 325                         tmp = regs->acx;
 326                         break;
 327 #endif
 328                 case FPC_CSR:
 329                         tmp = child->thread.fpu.fcr31;
 330                         break;
 331                 case FPC_EIR: { /* implementation / version register */
 332                         unsigned int flags;
 333 #ifdef CONFIG_MIPS_MT_SMTC
 334                         unsigned long irqflags;
 335                         unsigned int mtflags;
 336 #endif /* CONFIG_MIPS_MT_SMTC */
 337
 338                         preempt_disable();
 339                         if (!cpu_has_fpu) {
 340                                 preempt_enable();
 341                                 break;
 342                         }
 343
 344 #ifdef CONFIG_MIPS_MT_SMTC
 345                         /* Read-modify-write of Status must be atomic */
 346                         local_irq_save(irqflags);
 347                         mtflags = dmt();
 348 #endif /* CONFIG_MIPS_MT_SMTC */
 349                         if (cpu_has_mipsmt) {
 350                                 unsigned int vpflags = dvpe();
 351                                 flags = read_c0_status();
 352                                 __enable_fpu();
 353                                 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
 354                                 write_c0_status(flags);
 355                                 evpe(vpflags);
 356                         } else {
 357                                 flags = read_c0_status();
 358                                 __enable_fpu();
 359                                 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
 360                                 write_c0_status(flags);
 361                         }
 362 #ifdef CONFIG_MIPS_MT_SMTC
 363                         emt(mtflags);
 364                         local_irq_restore(irqflags);
 365 #endif /* CONFIG_MIPS_MT_SMTC */
 366                         preempt_enable();
 367                         break;
 368                 }
 369                 case DSP_BASE ... DSP_BASE + 5: {
 370                         dspreg_t *dregs;
 371
 372                         if (!cpu_has_dsp) {
 373                                 tmp = 0;
 374                                 ret = -EIO;
 375                                 goto out;
 376                         }
 377                         dregs = __get_dsp_regs(child);
 378                         tmp = (unsigned long) (dregs[addr - DSP_BASE]);
 379                         break;
 380                 }
 381                 case DSP_CONTROL:
 382                         if (!cpu_has_dsp) {
 383                                 tmp = 0;
 384                                 ret = -EIO;
 385                                 goto out;
 386                         }
 387                         tmp = child->thread.dsp.dspcontrol;
 388                         break;
 389                 default:
 390                         tmp = 0;
 391                         ret = -EIO;
 392                         goto out;
 393                 }
 394                 ret = put_user(tmp, datalp);
 395                 break;
 396         }
 397
 398         /* when I and D space are separate, this will have to be fixed. */
 399         case PTRACE_POKETEXT: /* write the word at location addr. */
 400         case PTRACE_POKEDATA:
 401                 ret = generic_ptrace_pokedata(child, addr, data);
 402                 break;
 403
 404         case PTRACE_POKEUSR: {
 405                 struct pt_regs *regs;
 406                 ret = 0;
 407                 regs = task_pt_regs(child);
 408
 409                 switch (addr) {
 410                 case 0 ... 31:
 411                         regs->regs[addr] = data;
 412                         break;
 413                 case FPR_BASE ... FPR_BASE + 31: {
 414                         fpureg_t *fregs = get_fpu_regs(child);
 415
 416                         if (!tsk_used_math(child)) {
 417                                 /* FP not yet used  */
 418                                 memset(&child->thread.fpu, ~0,
 419                                        sizeof(child->thread.fpu));
 420                                 child->thread.fpu.fcr31 = 0;
 421                         }
 422 #ifdef CONFIG_32BIT
 423                         /*
 424                          * The odd registers are actually the high order bits
 425                          * of the values stored in the even registers - unless
 426                          * we're using r2k_switch.S.
 427                          */
 428                         if (addr & 1) {
 429                                 fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff;
 430                                 fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long long) data) << 32;
 431                         } else {
 432                                 fregs[addr - FPR_BASE] &= ~0xffffffffLL;
 433                                 fregs[addr - FPR_BASE] |= data;
 434                         }
 435 #endif
 436 #ifdef CONFIG_64BIT
 437                         fregs[addr - FPR_BASE] = data;
 438 #endif
 439                         break;
 440                 }
 441                 case PC:
 442                         regs->cp0_epc = data;
 443                         break;
 444                 case MMHI:
 445                         regs->hi = data;
 446                         break;
 447                 case MMLO:
 448                         regs->lo = data;
 449                         break;
 450 #ifdef CONFIG_CPU_HAS_SMARTMIPS
 451                 case ACX:
 452                         regs->acx = data;
 453                         break;
 454 #endif
 455                 case FPC_CSR:
 456                         child->thread.fpu.fcr31 = data & ~FPU_CSR_ALL_X;
 457                         break;
 458                 case DSP_BASE ... DSP_BASE + 5: {
 459                         dspreg_t *dregs;
 460
 461                         if (!cpu_has_dsp) {
 462                                 ret = -EIO;
 463                                 break;
 464                         }
 465
 466                         dregs = __get_dsp_regs(child);
 467                         dregs[addr - DSP_BASE] = data;
 468                         break;
 469                 }
 470                 case DSP_CONTROL:
 471                         if (!cpu_has_dsp) {
 472                                 ret = -EIO;
 473                                 break;
 474                         }
 475                         child->thread.dsp.dspcontrol = data;
 476                         break;
 477                 default:
 478                         /* The rest are not allowed. */
 479                         ret = -EIO;
 480                         break;
 481                 }
 482                 break;
 483                 }
 484
 485         case PTRACE_GETREGS:
 486                 ret = ptrace_getregs(child, datavp);
 487                 break;
 488
 489         case PTRACE_SETREGS:
 490                 ret = ptrace_setregs(child, datavp);
 491                 break;
 492
 493         case PTRACE_GETFPREGS:
 494                 ret = ptrace_getfpregs(child, datavp);
 495                 break;
 496
 497         case PTRACE_SETFPREGS:
 498                 ret = ptrace_setfpregs(child, datavp);
 499                 break;
 500
 501         case PTRACE_GET_THREAD_AREA:
 502                 ret = put_user(task_thread_info(child)->tp_value, datalp);
 503                 break;
 504
 505         case PTRACE_GET_WATCH_REGS:
 506                 ret = ptrace_get_watch_regs(child, addrp);
 507                 break;
 508
 509         case PTRACE_SET_WATCH_REGS:
 510                 ret = ptrace_set_watch_regs(child, addrp);
 511                 break;
 512
 513         default:
 514                 ret = ptrace_request(child, request, addr, data);
 515                 break;
 516         }
 517  out:
 518         return ret;
 519 }
 520
 521 static inline int audit_arch(void)
 522 {
 523         int arch = EM_MIPS;
 524 #ifdef CONFIG_64BIT
 525         arch |=  __AUDIT_ARCH_64BIT;
 526 #endif
 527 #if defined(__LITTLE_ENDIAN)
 528         arch |=  __AUDIT_ARCH_LE;
 529 #endif
 530         return arch;
 531 }
 532
 533 /*
 534  * Notification of system call entry/exit
 535  * - triggered by current->work.syscall_trace
 536  */
 537 asmlinkage void syscall_trace_enter(struct pt_regs *regs)
 538 {
 539         /* do the secure computing check first */
 540         secure_computing(regs->regs[2]);
 541
 542         if (!(current->ptrace & PT_PTRACED))
 543                 goto out;
 544
 545         if (!test_thread_flag(TIF_SYSCALL_TRACE))
 546                 goto out;
 547
 548         /* The 0x80 provides a way for the tracing parent to distinguish
 549            between a syscall stop and SIGTRAP delivery */
 550         ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
 551                                  0x80 : 0));
 552
 553         /*
 554          * this isn't the same as continuing with a signal, but it will do
 555          * for normal use.  strace only continues with a signal if the
 556          * stopping signal is not SIGTRAP.  -brl
 557          */
 558         if (current->exit_code) {
 559                 send_sig(current->exit_code, current, 1);
 560                 current->exit_code = 0;
 561         }
 562
 563 out:
 564         if (unlikely(current->audit_context))
 565                 audit_syscall_entry(audit_arch(), regs->regs[2],
 566                                     regs->regs[4], regs->regs[5],
 567                                     regs->regs[6], regs->regs[7]);
 568 }
 569
 570 /*
 571  * Notification of system call entry/exit
 572  * - triggered by current->work.syscall_trace
 573  */
 574 asmlinkage void syscall_trace_leave(struct pt_regs *regs)
 575 {
 576         if (unlikely(current->audit_context))
 577                 audit_syscall_exit(AUDITSC_RESULT(regs->regs[7]),
 578                                    -regs->regs[2]);
 579
 580         if (!(current->ptrace & PT_PTRACED))
 581                 return;
 582
 583         if (!test_thread_flag(TIF_SYSCALL_TRACE))
 584                 return;
 585
 586         /* The 0x80 provides a way for the tracing parent to distinguish
 587            between a syscall stop and SIGTRAP delivery */
 588         ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
 589                                  0x80 : 0));
 590
 591         /*
 592          * this isn't the same as continuing with a signal, but it will do
 593          * for normal use.  strace only continues with a signal if the
 594          * stopping signal is not SIGTRAP.  -brl
 595          */
 596         if (current->exit_code) {
 597                 send_sig(current->exit_code, current, 1);
 598                 current->exit_code = 0;
 599         }
 600 }