2 * Linux performance counter support for MIPS.
4 * Copyright (C) 2010 MIPS Technologies, Inc.
5 * Copyright (C) 2011 Cavium Networks, Inc.
6 * Author: Deng-Cheng Zhu
8 * This code is based on the implementation for ARM, which is in turn
9 * based on the sparc64 perf event code and the x86 code. Performance
10 * counter access is based on the MIPS Oprofile code. And the callchain
11 * support references the code of MIPS stacktrace.c.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/cpumask.h>
19 #include <linux/interrupt.h>
20 #include <linux/smp.h>
21 #include <linux/kernel.h>
22 #include <linux/perf_event.h>
23 #include <linux/uaccess.h>
26 #include <asm/irq_regs.h>
27 #include <asm/stacktrace.h>
28 #include <asm/time.h> /* For perf_irq */
30 #define MIPS_MAX_HWEVENTS 4
32 struct cpu_hw_events {
33 /* Array of events on this cpu. */
34 struct perf_event *events[MIPS_MAX_HWEVENTS];
37 * Set the bit (indexed by the counter number) when the counter
38 * is used for an event.
40 unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
43 * Software copy of the control register for each performance counter.
44 * MIPS CPUs vary in performance counters. They use this differently,
45 * and even may not use it.
47 unsigned int saved_ctrl[MIPS_MAX_HWEVENTS];
49 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
53 /* The description of MIPS performance events. */
54 struct mips_perf_event {
55 unsigned int event_id;
57 * MIPS performance counters are indexed starting from 0.
58 * CNTR_EVEN indicates the indexes of the counters to be used are
61 unsigned int cntr_mask;
62 #define CNTR_EVEN 0x55555555
63 #define CNTR_ODD 0xaaaaaaaa
64 #define CNTR_ALL 0xffffffff
65 #ifdef CONFIG_MIPS_MT_SMP
78 static struct mips_perf_event raw_event;
79 static DEFINE_MUTEX(raw_event_mutex);
81 #define UNSUPPORTED_PERF_EVENT_ID 0xffffffff
82 #define C(x) PERF_COUNT_HW_CACHE_##x
90 u64 (*read_counter)(unsigned int idx);
91 void (*write_counter)(unsigned int idx, u64 val);
92 const struct mips_perf_event *(*map_raw_event)(u64 config);
93 const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
94 const struct mips_perf_event (*cache_event_map)
95 [PERF_COUNT_HW_CACHE_MAX]
96 [PERF_COUNT_HW_CACHE_OP_MAX]
97 [PERF_COUNT_HW_CACHE_RESULT_MAX];
98 unsigned int num_counters;
101 static struct mips_pmu mipspmu;
103 #define M_CONFIG1_PC (1 << 4)
105 #define M_PERFCTL_EXL (1 << 0)
106 #define M_PERFCTL_KERNEL (1 << 1)
107 #define M_PERFCTL_SUPERVISOR (1 << 2)
108 #define M_PERFCTL_USER (1 << 3)
109 #define M_PERFCTL_INTERRUPT_ENABLE (1 << 4)
110 #define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
111 #define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
112 #define M_PERFCTL_MT_EN(filter) ((filter) << 20)
113 #define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
114 #define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
115 #define M_TC_EN_TC M_PERFCTL_MT_EN(2)
116 #define M_PERFCTL_TCID(tcid) ((tcid) << 22)
117 #define M_PERFCTL_WIDE (1 << 30)
118 #define M_PERFCTL_MORE (1 << 31)
120 #define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL | \
123 M_PERFCTL_SUPERVISOR | \
124 M_PERFCTL_INTERRUPT_ENABLE)
126 #ifdef CONFIG_MIPS_MT_SMP
127 #define M_PERFCTL_CONFIG_MASK 0x3fff801f
129 #define M_PERFCTL_CONFIG_MASK 0x1f
131 #define M_PERFCTL_EVENT_MASK 0xfe0
134 #ifdef CONFIG_MIPS_MT_SMP
135 static int cpu_has_mipsmt_pertccounters;
137 static DEFINE_RWLOCK(pmuint_rwlock);
140 * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because
141 * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs.
143 #if defined(CONFIG_HW_PERF_EVENTS)
144 #define vpe_id() (cpu_has_mipsmt_pertccounters ? \
145 0 : smp_processor_id())
147 #define vpe_id() (cpu_has_mipsmt_pertccounters ? \
148 0 : cpu_data[smp_processor_id()].vpe_id)
151 /* Copied from op_model_mipsxx.c */
152 static unsigned int vpe_shift(void)
154 if (num_possible_cpus() > 1)
160 static unsigned int counters_total_to_per_cpu(unsigned int counters)
162 return counters >> vpe_shift();
165 static unsigned int counters_per_cpu_to_total(unsigned int counters)
167 return counters << vpe_shift();
170 #else /* !CONFIG_MIPS_MT_SMP */
173 #endif /* CONFIG_MIPS_MT_SMP */
175 static void resume_local_counters(void);
176 static void pause_local_counters(void);
177 static irqreturn_t mipsxx_pmu_handle_irq(int, void *);
178 static int mipsxx_pmu_handle_shared_irq(void);
180 static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx)
187 static u64 mipsxx_pmu_read_counter(unsigned int idx)
189 idx = mipsxx_pmu_swizzle_perf_idx(idx);
194 * The counters are unsigned, we must cast to truncate
197 return (u32)read_c0_perfcntr0();
199 return (u32)read_c0_perfcntr1();
201 return (u32)read_c0_perfcntr2();
203 return (u32)read_c0_perfcntr3();
205 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
210 static u64 mipsxx_pmu_read_counter_64(unsigned int idx)
212 idx = mipsxx_pmu_swizzle_perf_idx(idx);
216 return read_c0_perfcntr0_64();
218 return read_c0_perfcntr1_64();
220 return read_c0_perfcntr2_64();
222 return read_c0_perfcntr3_64();
224 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
229 static void mipsxx_pmu_write_counter(unsigned int idx, u64 val)
231 idx = mipsxx_pmu_swizzle_perf_idx(idx);
235 write_c0_perfcntr0(val);
238 write_c0_perfcntr1(val);
241 write_c0_perfcntr2(val);
244 write_c0_perfcntr3(val);
249 static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val)
251 idx = mipsxx_pmu_swizzle_perf_idx(idx);
255 write_c0_perfcntr0_64(val);
258 write_c0_perfcntr1_64(val);
261 write_c0_perfcntr2_64(val);
264 write_c0_perfcntr3_64(val);
269 static unsigned int mipsxx_pmu_read_control(unsigned int idx)
271 idx = mipsxx_pmu_swizzle_perf_idx(idx);
275 return read_c0_perfctrl0();
277 return read_c0_perfctrl1();
279 return read_c0_perfctrl2();
281 return read_c0_perfctrl3();
283 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
288 static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
290 idx = mipsxx_pmu_swizzle_perf_idx(idx);
294 write_c0_perfctrl0(val);
297 write_c0_perfctrl1(val);
300 write_c0_perfctrl2(val);
303 write_c0_perfctrl3(val);
308 static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
309 struct hw_perf_event *hwc)
314 * We only need to care the counter mask. The range has been
315 * checked definitely.
317 unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff;
319 for (i = mipspmu.num_counters - 1; i >= 0; i--) {
321 * Note that some MIPS perf events can be counted by both
322 * even and odd counters, wheresas many other are only by
323 * even _or_ odd counters. This introduces an issue that
324 * when the former kind of event takes the counter the
325 * latter kind of event wants to use, then the "counter
326 * allocation" for the latter event will fail. In fact if
327 * they can be dynamically swapped, they both feel happy.
328 * But here we leave this issue alone for now.
330 if (test_bit(i, &cntr_mask) &&
331 !test_and_set_bit(i, cpuc->used_mask))
338 static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
340 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
342 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
344 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
345 (evt->config_base & M_PERFCTL_CONFIG_MASK) |
346 /* Make sure interrupt enabled. */
347 M_PERFCTL_INTERRUPT_ENABLE;
349 * We do not actually let the counter run. Leave it until start().
353 static void mipsxx_pmu_disable_event(int idx)
355 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
358 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
360 local_irq_save(flags);
361 cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) &
362 ~M_PERFCTL_COUNT_EVENT_WHENEVER;
363 mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);
364 local_irq_restore(flags);
367 static int mipspmu_event_set_period(struct perf_event *event,
368 struct hw_perf_event *hwc,
371 u64 left = local64_read(&hwc->period_left);
372 u64 period = hwc->sample_period;
375 if (unlikely((left + period) & (1ULL << 63))) {
376 /* left underflowed by more than period. */
378 local64_set(&hwc->period_left, left);
379 hwc->last_period = period;
381 } else if (unlikely((left + period) <= period)) {
382 /* left underflowed by less than period. */
384 local64_set(&hwc->period_left, left);
385 hwc->last_period = period;
389 if (left > mipspmu.max_period) {
390 left = mipspmu.max_period;
391 local64_set(&hwc->period_left, left);
394 local64_set(&hwc->prev_count, mipspmu.overflow - left);
396 mipspmu.write_counter(idx, mipspmu.overflow - left);
398 perf_event_update_userpage(event);
403 static void mipspmu_event_update(struct perf_event *event,
404 struct hw_perf_event *hwc,
407 u64 prev_raw_count, new_raw_count;
411 prev_raw_count = local64_read(&hwc->prev_count);
412 new_raw_count = mipspmu.read_counter(idx);
414 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
415 new_raw_count) != prev_raw_count)
418 delta = new_raw_count - prev_raw_count;
420 local64_add(delta, &event->count);
421 local64_sub(delta, &hwc->period_left);
424 static void mipspmu_start(struct perf_event *event, int flags)
426 struct hw_perf_event *hwc = &event->hw;
428 if (flags & PERF_EF_RELOAD)
429 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
433 /* Set the period for the event. */
434 mipspmu_event_set_period(event, hwc, hwc->idx);
436 /* Enable the event. */
437 mipsxx_pmu_enable_event(hwc, hwc->idx);
440 static void mipspmu_stop(struct perf_event *event, int flags)
442 struct hw_perf_event *hwc = &event->hw;
444 if (!(hwc->state & PERF_HES_STOPPED)) {
445 /* We are working on a local event. */
446 mipsxx_pmu_disable_event(hwc->idx);
448 mipspmu_event_update(event, hwc, hwc->idx);
449 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
453 static int mipspmu_add(struct perf_event *event, int flags)
455 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
456 struct hw_perf_event *hwc = &event->hw;
460 perf_pmu_disable(event->pmu);
462 /* To look for a free counter for this event. */
463 idx = mipsxx_pmu_alloc_counter(cpuc, hwc);
470 * If there is an event in the counter we are going to use then
471 * make sure it is disabled.
474 mipsxx_pmu_disable_event(idx);
475 cpuc->events[idx] = event;
477 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
478 if (flags & PERF_EF_START)
479 mipspmu_start(event, PERF_EF_RELOAD);
481 /* Propagate our changes to the userspace mapping. */
482 perf_event_update_userpage(event);
485 perf_pmu_enable(event->pmu);
489 static void mipspmu_del(struct perf_event *event, int flags)
491 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
492 struct hw_perf_event *hwc = &event->hw;
495 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
497 mipspmu_stop(event, PERF_EF_UPDATE);
498 cpuc->events[idx] = NULL;
499 clear_bit(idx, cpuc->used_mask);
501 perf_event_update_userpage(event);
504 static void mipspmu_read(struct perf_event *event)
506 struct hw_perf_event *hwc = &event->hw;
508 /* Don't read disabled counters! */
512 mipspmu_event_update(event, hwc, hwc->idx);
515 static void mipspmu_enable(struct pmu *pmu)
517 #ifdef CONFIG_MIPS_MT_SMP
518 write_unlock(&pmuint_rwlock);
520 resume_local_counters();
524 * MIPS performance counters can be per-TC. The control registers can
525 * not be directly accessed accross CPUs. Hence if we want to do global
526 * control, we need cross CPU calls. on_each_cpu() can help us, but we
527 * can not make sure this function is called with interrupts enabled. So
528 * here we pause local counters and then grab a rwlock and leave the
529 * counters on other CPUs alone. If any counter interrupt raises while
530 * we own the write lock, simply pause local counters on that CPU and
531 * spin in the handler. Also we know we won't be switched to another
532 * CPU after pausing local counters and before grabbing the lock.
534 static void mipspmu_disable(struct pmu *pmu)
536 pause_local_counters();
537 #ifdef CONFIG_MIPS_MT_SMP
538 write_lock(&pmuint_rwlock);
542 static atomic_t active_events = ATOMIC_INIT(0);
543 static DEFINE_MUTEX(pmu_reserve_mutex);
544 static int (*save_perf_irq)(void);
546 static int mipspmu_get_irq(void)
550 if (mipspmu.irq >= 0) {
551 /* Request my own irq handler. */
552 err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,
553 IRQF_PERCPU | IRQF_NOBALANCING,
554 "mips_perf_pmu", NULL);
556 pr_warning("Unable to request IRQ%d for MIPS "
557 "performance counters!\n", mipspmu.irq);
559 } else if (cp0_perfcount_irq < 0) {
561 * We are sharing the irq number with the timer interrupt.
563 save_perf_irq = perf_irq;
564 perf_irq = mipsxx_pmu_handle_shared_irq;
567 pr_warning("The platform hasn't properly defined its "
568 "interrupt controller.\n");
575 static void mipspmu_free_irq(void)
577 if (mipspmu.irq >= 0)
578 free_irq(mipspmu.irq, NULL);
579 else if (cp0_perfcount_irq < 0)
580 perf_irq = save_perf_irq;
584 * mipsxx/rm9000/loongson2 have different performance counters, they have
585 * specific low-level init routines.
587 static void reset_counters(void *arg);
588 static int __hw_perf_event_init(struct perf_event *event);
590 static void hw_perf_event_destroy(struct perf_event *event)
592 if (atomic_dec_and_mutex_lock(&active_events,
593 &pmu_reserve_mutex)) {
595 * We must not call the destroy function with interrupts
598 on_each_cpu(reset_counters,
599 (void *)(long)mipspmu.num_counters, 1);
601 mutex_unlock(&pmu_reserve_mutex);
605 static int mipspmu_event_init(struct perf_event *event)
609 /* does not support taken branch sampling */
610 if (has_branch_stack(event))
613 switch (event->attr.type) {
615 case PERF_TYPE_HARDWARE:
616 case PERF_TYPE_HW_CACHE:
623 if (event->cpu >= nr_cpumask_bits ||
624 (event->cpu >= 0 && !cpu_online(event->cpu)))
627 if (!atomic_inc_not_zero(&active_events)) {
628 mutex_lock(&pmu_reserve_mutex);
629 if (atomic_read(&active_events) == 0)
630 err = mipspmu_get_irq();
633 atomic_inc(&active_events);
634 mutex_unlock(&pmu_reserve_mutex);
640 return __hw_perf_event_init(event);
643 static struct pmu pmu = {
644 .pmu_enable = mipspmu_enable,
645 .pmu_disable = mipspmu_disable,
646 .event_init = mipspmu_event_init,
649 .start = mipspmu_start,
650 .stop = mipspmu_stop,
651 .read = mipspmu_read,
654 static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)
657 * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
660 #ifdef CONFIG_MIPS_MT_SMP
661 return ((unsigned int)pev->range << 24) |
662 (pev->cntr_mask & 0xffff00) |
663 (pev->event_id & 0xff);
665 return (pev->cntr_mask & 0xffff00) |
666 (pev->event_id & 0xff);
670 static const struct mips_perf_event *mipspmu_map_general_event(int idx)
672 const struct mips_perf_event *pev;
674 pev = ((*mipspmu.general_event_map)[idx].event_id ==
675 UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) :
676 &(*mipspmu.general_event_map)[idx]);
681 static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
683 unsigned int cache_type, cache_op, cache_result;
684 const struct mips_perf_event *pev;
686 cache_type = (config >> 0) & 0xff;
687 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
688 return ERR_PTR(-EINVAL);
690 cache_op = (config >> 8) & 0xff;
691 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
692 return ERR_PTR(-EINVAL);
694 cache_result = (config >> 16) & 0xff;
695 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
696 return ERR_PTR(-EINVAL);
698 pev = &((*mipspmu.cache_event_map)
703 if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID)
704 return ERR_PTR(-EOPNOTSUPP);
710 static int validate_group(struct perf_event *event)
712 struct perf_event *sibling, *leader = event->group_leader;
713 struct cpu_hw_events fake_cpuc;
715 memset(&fake_cpuc, 0, sizeof(fake_cpuc));
717 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0)
720 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
721 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0)
725 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0)
731 /* This is needed by specific irq handlers in perf_event_*.c */
732 static void handle_associated_event(struct cpu_hw_events *cpuc,
733 int idx, struct perf_sample_data *data,
734 struct pt_regs *regs)
736 struct perf_event *event = cpuc->events[idx];
737 struct hw_perf_event *hwc = &event->hw;
739 mipspmu_event_update(event, hwc, idx);
740 data->period = event->hw.last_period;
741 if (!mipspmu_event_set_period(event, hwc, idx))
744 if (perf_event_overflow(event, data, regs))
745 mipsxx_pmu_disable_event(idx);
749 static int __n_counters(void)
751 if (!(read_c0_config1() & M_CONFIG1_PC))
753 if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
755 if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
757 if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
763 static int n_counters(void)
767 switch (current_cpu_type()) {
778 counters = __n_counters();
784 static void reset_counters(void *arg)
786 int counters = (int)(long)arg;
789 mipsxx_pmu_write_control(3, 0);
790 mipspmu.write_counter(3, 0);
792 mipsxx_pmu_write_control(2, 0);
793 mipspmu.write_counter(2, 0);
795 mipsxx_pmu_write_control(1, 0);
796 mipspmu.write_counter(1, 0);
798 mipsxx_pmu_write_control(0, 0);
799 mipspmu.write_counter(0, 0);
803 /* 24K/34K/1004K cores can share the same event map. */
804 static const struct mips_perf_event mipsxxcore_event_map
805 [PERF_COUNT_HW_MAX] = {
806 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
807 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
808 [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
809 [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
810 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
811 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
812 [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
815 /* 74K core has different branch event code. */
816 static const struct mips_perf_event mipsxx74Kcore_event_map
817 [PERF_COUNT_HW_MAX] = {
818 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
819 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
820 [PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
821 [PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
822 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
823 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
824 [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
827 static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
828 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
829 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
830 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL },
831 [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL },
832 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL },
833 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL },
834 [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL },
837 /* 24K/34K/1004K cores can share the same cache event map. */
838 static const struct mips_perf_event mipsxxcore_cache_map
839 [PERF_COUNT_HW_CACHE_MAX]
840 [PERF_COUNT_HW_CACHE_OP_MAX]
841 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
844 * Like some other architectures (e.g. ARM), the performance
845 * counters don't differentiate between read and write
846 * accesses/misses, so this isn't strictly correct, but it's the
847 * best we can do. Writes and reads get combined.
850 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
851 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
854 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
855 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
858 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
859 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
864 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
865 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
868 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
869 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
872 [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T },
874 * Note that MIPS has only "hit" events countable for
875 * the prefetch operation.
877 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
882 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
883 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
886 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
887 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
890 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
891 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
896 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
897 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
900 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
901 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
904 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
905 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
910 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
911 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
914 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
915 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
918 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
919 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
923 /* Using the same code for *HW_BRANCH* */
925 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
926 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
929 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
930 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
933 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
934 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
939 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
940 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
943 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
944 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
947 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
948 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
953 /* 74K core has completely different cache event map. */
954 static const struct mips_perf_event mipsxx74Kcore_cache_map
955 [PERF_COUNT_HW_CACHE_MAX]
956 [PERF_COUNT_HW_CACHE_OP_MAX]
957 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
960 * Like some other architectures (e.g. ARM), the performance
961 * counters don't differentiate between read and write
962 * accesses/misses, so this isn't strictly correct, but it's the
963 * best we can do. Writes and reads get combined.
966 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
967 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
970 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
971 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
974 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
975 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
980 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
981 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
984 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
985 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
988 [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T },
990 * Note that MIPS has only "hit" events countable for
991 * the prefetch operation.
993 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
998 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
999 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
1002 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
1003 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
1005 [C(OP_PREFETCH)] = {
1006 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1007 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1011 /* 74K core does not have specific DTLB events. */
1013 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1014 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1017 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1018 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1020 [C(OP_PREFETCH)] = {
1021 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1022 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1027 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1028 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1031 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1032 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1034 [C(OP_PREFETCH)] = {
1035 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1036 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1040 /* Using the same code for *HW_BRANCH* */
1042 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1043 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1046 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1047 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1049 [C(OP_PREFETCH)] = {
1050 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1051 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1056 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1057 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1060 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1061 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1063 [C(OP_PREFETCH)] = {
1064 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1065 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1071 static const struct mips_perf_event octeon_cache_map
1072 [PERF_COUNT_HW_CACHE_MAX]
1073 [PERF_COUNT_HW_CACHE_OP_MAX]
1074 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1077 [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL },
1078 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL },
1081 [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL },
1082 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1084 [C(OP_PREFETCH)] = {
1085 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1086 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1091 [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL },
1092 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1095 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1096 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1098 [C(OP_PREFETCH)] = {
1099 [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL },
1100 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1105 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1106 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1109 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1110 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1112 [C(OP_PREFETCH)] = {
1113 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1114 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1119 * Only general DTLB misses are counted use the same event for
1123 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1124 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1127 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1128 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1130 [C(OP_PREFETCH)] = {
1131 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1132 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1137 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1138 [C(RESULT_MISS)] = { 0x37, CNTR_ALL },
1141 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1142 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1144 [C(OP_PREFETCH)] = {
1145 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1146 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1150 /* Using the same code for *HW_BRANCH* */
1152 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1153 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1156 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1157 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1159 [C(OP_PREFETCH)] = {
1160 [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1161 [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1166 #ifdef CONFIG_MIPS_MT_SMP
1167 static void check_and_calc_range(struct perf_event *event,
1168 const struct mips_perf_event *pev)
1170 struct hw_perf_event *hwc = &event->hw;
1172 if (event->cpu >= 0) {
1173 if (pev->range > V) {
1175 * The user selected an event that is processor
1176 * wide, while expecting it to be VPE wide.
1178 hwc->config_base |= M_TC_EN_ALL;
1181 * FIXME: cpu_data[event->cpu].vpe_id reports 0
1184 hwc->config_base |= M_PERFCTL_VPEID(event->cpu);
1185 hwc->config_base |= M_TC_EN_VPE;
1188 hwc->config_base |= M_TC_EN_ALL;
1191 static void check_and_calc_range(struct perf_event *event,
1192 const struct mips_perf_event *pev)
1197 static int __hw_perf_event_init(struct perf_event *event)
1199 struct perf_event_attr *attr = &event->attr;
1200 struct hw_perf_event *hwc = &event->hw;
1201 const struct mips_perf_event *pev;
1204 /* Returning MIPS event descriptor for generic perf event. */
1205 if (PERF_TYPE_HARDWARE == event->attr.type) {
1206 if (event->attr.config >= PERF_COUNT_HW_MAX)
1208 pev = mipspmu_map_general_event(event->attr.config);
1209 } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
1210 pev = mipspmu_map_cache_event(event->attr.config);
1211 } else if (PERF_TYPE_RAW == event->attr.type) {
1212 /* We are working on the global raw event. */
1213 mutex_lock(&raw_event_mutex);
1214 pev = mipspmu.map_raw_event(event->attr.config);
1216 /* The event type is not (yet) supported. */
1221 if (PERF_TYPE_RAW == event->attr.type)
1222 mutex_unlock(&raw_event_mutex);
1223 return PTR_ERR(pev);
1227 * We allow max flexibility on how each individual counter shared
1228 * by the single CPU operates (the mode exclusion and the range).
1230 hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE;
1232 /* Calculate range bits and validate it. */
1233 if (num_possible_cpus() > 1)
1234 check_and_calc_range(event, pev);
1236 hwc->event_base = mipspmu_perf_event_encode(pev);
1237 if (PERF_TYPE_RAW == event->attr.type)
1238 mutex_unlock(&raw_event_mutex);
1240 if (!attr->exclude_user)
1241 hwc->config_base |= M_PERFCTL_USER;
1242 if (!attr->exclude_kernel) {
1243 hwc->config_base |= M_PERFCTL_KERNEL;
1244 /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */
1245 hwc->config_base |= M_PERFCTL_EXL;
1247 if (!attr->exclude_hv)
1248 hwc->config_base |= M_PERFCTL_SUPERVISOR;
1250 hwc->config_base &= M_PERFCTL_CONFIG_MASK;
1252 * The event can belong to another cpu. We do not assign a local
1253 * counter for it for now.
1258 if (!hwc->sample_period) {
1259 hwc->sample_period = mipspmu.max_period;
1260 hwc->last_period = hwc->sample_period;
1261 local64_set(&hwc->period_left, hwc->sample_period);
1265 if (event->group_leader != event)
1266 err = validate_group(event);
1268 event->destroy = hw_perf_event_destroy;
1271 event->destroy(event);
1276 static void pause_local_counters(void)
1278 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1279 int ctr = mipspmu.num_counters;
1280 unsigned long flags;
1282 local_irq_save(flags);
1285 cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr);
1286 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] &
1287 ~M_PERFCTL_COUNT_EVENT_WHENEVER);
1289 local_irq_restore(flags);
1292 static void resume_local_counters(void)
1294 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1295 int ctr = mipspmu.num_counters;
1299 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]);
1303 static int mipsxx_pmu_handle_shared_irq(void)
1305 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1306 struct perf_sample_data data;
1307 unsigned int counters = mipspmu.num_counters;
1309 int handled = IRQ_NONE;
1310 struct pt_regs *regs;
1312 if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
1315 * First we pause the local counters, so that when we are locked
1316 * here, the counters are all paused. When it gets locked due to
1317 * perf_disable(), the timer interrupt handler will be delayed.
1319 * See also mipsxx_pmu_start().
1321 pause_local_counters();
1322 #ifdef CONFIG_MIPS_MT_SMP
1323 read_lock(&pmuint_rwlock);
1326 regs = get_irq_regs();
1328 perf_sample_data_init(&data, 0, 0);
1331 #define HANDLE_COUNTER(n) \
1333 if (test_bit(n, cpuc->used_mask)) { \
1334 counter = mipspmu.read_counter(n); \
1335 if (counter & mipspmu.overflow) { \
1336 handle_associated_event(cpuc, n, &data, regs); \
1337 handled = IRQ_HANDLED; \
1347 * Do all the work for the pending perf events. We can do this
1348 * in here because the performance counter interrupt is a regular
1349 * interrupt, not NMI.
1351 if (handled == IRQ_HANDLED)
1354 #ifdef CONFIG_MIPS_MT_SMP
1355 read_unlock(&pmuint_rwlock);
1357 resume_local_counters();
1361 static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
1363 return mipsxx_pmu_handle_shared_irq();
1367 #define IS_BOTH_COUNTERS_24K_EVENT(b) \
1368 ((b) == 0 || (b) == 1 || (b) == 11)
1371 #define IS_BOTH_COUNTERS_34K_EVENT(b) \
1372 ((b) == 0 || (b) == 1 || (b) == 11)
1373 #ifdef CONFIG_MIPS_MT_SMP
1374 #define IS_RANGE_P_34K_EVENT(r, b) \
1375 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
1376 (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 || \
1377 (r) == 176 || ((b) >= 50 && (b) <= 55) || \
1378 ((b) >= 64 && (b) <= 67))
1379 #define IS_RANGE_V_34K_EVENT(r) ((r) == 47)
1383 #define IS_BOTH_COUNTERS_74K_EVENT(b) \
1384 ((b) == 0 || (b) == 1)
1387 #define IS_BOTH_COUNTERS_1004K_EVENT(b) \
1388 ((b) == 0 || (b) == 1 || (b) == 11)
1389 #ifdef CONFIG_MIPS_MT_SMP
1390 #define IS_RANGE_P_1004K_EVENT(r, b) \
1391 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
1392 (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 || \
1393 (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) || \
1394 (r) == 188 || (b) == 61 || (b) == 62 || \
1395 ((b) >= 64 && (b) <= 67))
1396 #define IS_RANGE_V_1004K_EVENT(r) ((r) == 47)
1400 * User can use 0-255 raw events, where 0-127 for the events of even
1401 * counters, and 128-255 for odd counters. Note that bit 7 is used to
1402 * indicate the parity. So, for example, when user wants to take the
1403 * Event Num of 15 for odd counters (by referring to the user manual),
1404 * then 128 needs to be added to 15 as the input for the event config,
1405 * i.e., 143 (0x8F) to be used.
1407 static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1409 unsigned int raw_id = config & 0xff;
1410 unsigned int base_id = raw_id & 0x7f;
1412 raw_event.event_id = base_id;
1414 switch (current_cpu_type()) {
1416 if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
1417 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1419 raw_event.cntr_mask =
1420 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1421 #ifdef CONFIG_MIPS_MT_SMP
1423 * This is actually doing nothing. Non-multithreading
1424 * CPUs will not check and calculate the range.
1426 raw_event.range = P;
1430 if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
1431 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1433 raw_event.cntr_mask =
1434 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1435 #ifdef CONFIG_MIPS_MT_SMP
1436 if (IS_RANGE_P_34K_EVENT(raw_id, base_id))
1437 raw_event.range = P;
1438 else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id)))
1439 raw_event.range = V;
1441 raw_event.range = T;
1445 if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
1446 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1448 raw_event.cntr_mask =
1449 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1450 #ifdef CONFIG_MIPS_MT_SMP
1451 raw_event.range = P;
1455 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
1456 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1458 raw_event.cntr_mask =
1459 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1460 #ifdef CONFIG_MIPS_MT_SMP
1461 if (IS_RANGE_P_1004K_EVENT(raw_id, base_id))
1462 raw_event.range = P;
1463 else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id)))
1464 raw_event.range = V;
1466 raw_event.range = T;
1474 static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config)
1476 unsigned int raw_id = config & 0xff;
1477 unsigned int base_id = raw_id & 0x7f;
1480 raw_event.cntr_mask = CNTR_ALL;
1481 raw_event.event_id = base_id;
1483 if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
1485 return ERR_PTR(-EOPNOTSUPP);
1488 return ERR_PTR(-EOPNOTSUPP);
1499 return ERR_PTR(-EOPNOTSUPP);
1508 init_hw_perf_events(void)
1513 pr_info("Performance counters: ");
1515 counters = n_counters();
1516 if (counters == 0) {
1517 pr_cont("No available PMU.\n");
1521 #ifdef CONFIG_MIPS_MT_SMP
1522 cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
1523 if (!cpu_has_mipsmt_pertccounters)
1524 counters = counters_total_to_per_cpu(counters);
1527 #ifdef MSC01E_INT_BASE
1530 * Using platform specific interrupt controller defines.
1532 irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
1535 if ((cp0_perfcount_irq >= 0) &&
1536 (cp0_compare_irq != cp0_perfcount_irq))
1537 irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
1540 #ifdef MSC01E_INT_BASE
1544 mipspmu.map_raw_event = mipsxx_pmu_map_raw_event;
1546 switch (current_cpu_type()) {
1548 mipspmu.name = "mips/24K";
1549 mipspmu.general_event_map = &mipsxxcore_event_map;
1550 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1553 mipspmu.name = "mips/34K";
1554 mipspmu.general_event_map = &mipsxxcore_event_map;
1555 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1558 mipspmu.name = "mips/74K";
1559 mipspmu.general_event_map = &mipsxx74Kcore_event_map;
1560 mipspmu.cache_event_map = &mipsxx74Kcore_cache_map;
1563 mipspmu.name = "mips/1004K";
1564 mipspmu.general_event_map = &mipsxxcore_event_map;
1565 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1567 case CPU_CAVIUM_OCTEON:
1568 case CPU_CAVIUM_OCTEON_PLUS:
1569 case CPU_CAVIUM_OCTEON2:
1570 mipspmu.name = "octeon";
1571 mipspmu.general_event_map = &octeon_event_map;
1572 mipspmu.cache_event_map = &octeon_cache_map;
1573 mipspmu.map_raw_event = octeon_pmu_map_raw_event;
1576 pr_cont("Either hardware does not support performance "
1577 "counters, or not yet implemented.\n");
1581 mipspmu.num_counters = counters;
1584 if (read_c0_perfctrl0() & M_PERFCTL_WIDE) {
1585 mipspmu.max_period = (1ULL << 63) - 1;
1586 mipspmu.valid_count = (1ULL << 63) - 1;
1587 mipspmu.overflow = 1ULL << 63;
1588 mipspmu.read_counter = mipsxx_pmu_read_counter_64;
1589 mipspmu.write_counter = mipsxx_pmu_write_counter_64;
1592 mipspmu.max_period = (1ULL << 31) - 1;
1593 mipspmu.valid_count = (1ULL << 31) - 1;
1594 mipspmu.overflow = 1ULL << 31;
1595 mipspmu.read_counter = mipsxx_pmu_read_counter;
1596 mipspmu.write_counter = mipsxx_pmu_write_counter;
1600 on_each_cpu(reset_counters, (void *)(long)counters, 1);
1602 pr_cont("%s PMU enabled, %d %d-bit counters available to each "
1603 "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq,
1604 irq < 0 ? " (share with timer interrupt)" : "");
1606 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1610 early_initcall(init_hw_perf_events);