2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 * Copyright (C) 2002, 2007 Maciej W. Rozycki
11 #include <linux/init.h>
14 #include <asm/asmmacro.h>
15 #include <asm/cacheops.h>
16 #include <asm/irqflags.h>
17 #include <asm/regdef.h>
18 #include <asm/fpregdef.h>
19 #include <asm/mipsregs.h>
20 #include <asm/stackframe.h>
23 #include <asm/thread_info.h>
25 #define PANIC_PIC(msg) \
38 NESTED(except_vec0_generic, 0, sp)
39 PANIC_PIC("Exception vector 0 called")
40 END(except_vec0_generic)
42 NESTED(except_vec1_generic, 0, sp)
43 PANIC_PIC("Exception vector 1 called")
44 END(except_vec1_generic)
47 * General exception vector for all other CPUs.
49 * Be careful when changing this, it has to be at most 128 bytes
50 * to fit into space reserved for the exception handler.
52 NESTED(except_vec3_generic, 0, sp)
55 #if R5432_CP0_INTERRUPT_WAR
63 PTR_L k0, exception_handlers(k1)
66 END(except_vec3_generic)
69 * General exception handler for CPUs with virtual coherency exception.
71 * Be careful when changing this, it has to be at most 256 (as a special
72 * exception) bytes to fit into space reserved for the exception handler.
74 NESTED(except_vec3_r4000, 0, sp)
84 beq k1, k0, handle_vced
86 beq k1, k0, handle_vcei
91 PTR_L k0, exception_handlers(k1)
95 * Big shit, we now may have two dirty primary cache lines for the same
96 * physical address. We can safely invalidate the line pointed to by
97 * c0_badvaddr because after return from this exception handler the
98 * load / store will be re-executed.
101 MFC0 k0, CP0_BADVADDR
102 li k1, -4 # Is this ...
103 and k0, k1 # ... really needed?
105 cache Index_Store_Tag_D, (k0)
106 cache Hit_Writeback_Inv_SD, (k0)
107 #ifdef CONFIG_PROC_FS
108 PTR_LA k0, vced_count
116 MFC0 k0, CP0_BADVADDR
117 cache Hit_Writeback_Inv_SD, (k0) # also cleans pi
118 #ifdef CONFIG_PROC_FS
119 PTR_LA k0, vcei_count
126 END(except_vec3_r4000)
130 .align 5 /* 32 byte rollback region */
134 /* start of rollback region */
135 LONG_L t0, TI_FLAGS($28)
137 andi t0, _TIF_NEED_RESCHED
144 /* end of rollback region (the region size must be power of two) */
150 .macro BUILD_ROLLBACK_PROLOGUE handler
151 FEXPORT(rollback_\handler)
156 ori k0, 0x1f /* 32 byte rollback region */
165 BUILD_ROLLBACK_PROLOGUE handle_int
166 NESTED(handle_int, PT_SIZE, sp)
167 #ifdef CONFIG_TRACE_IRQFLAGS
169 * Check to see if the interrupted code has just disabled
170 * interrupts and ignore this interrupt for now if so.
172 * local_irq_disable() disables interrupts and then calls
173 * trace_hardirqs_off() to track the state. If an interrupt is taken
174 * after interrupts are disabled but before the state is updated
175 * it will appear to restore_all that it is incorrectly returning with
176 * interrupts disabled
181 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
202 LONG_L s0, TI_REGS($28)
203 LONG_S sp, TI_REGS($28)
204 PTR_LA ra, ret_from_irq
211 * Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
212 * This is a dedicated interrupt exception vector which reduces the
213 * interrupt processing overhead. The jump instruction will be replaced
214 * at the initialization time.
216 * Be careful when changing this, it has to be at most 128 bytes
217 * to fit into space reserved for the exception handler.
219 NESTED(except_vec4, 0, sp)
220 1: j 1b /* Dummy, will be replaced */
224 * EJTAG debug exception handler.
225 * The EJTAG debug exception entry point is 0xbfc00480, which
226 * normally is in the boot PROM, so the boot PROM must do a
227 * unconditional jump to this vector.
229 NESTED(except_vec_ejtag_debug, 0, sp)
230 j ejtag_debug_handler
231 END(except_vec_ejtag_debug)
236 * Vectored interrupt handler.
237 * This prototype is copied to ebase + n*IntCtl.VS and patched
238 * to invoke the handler
240 BUILD_ROLLBACK_PROLOGUE except_vec_vi
241 NESTED(except_vec_vi, 0, sp)
246 #ifdef CONFIG_MIPS_MT_SMTC
248 * To keep from blindly blocking *all* interrupts
249 * during service by SMTC kernel, we also want to
250 * pass the IM value to be cleared.
252 FEXPORT(except_vec_vi_mori)
254 #endif /* CONFIG_MIPS_MT_SMTC */
255 FEXPORT(except_vec_vi_lui)
256 lui v0, 0 /* Patched */
257 j except_vec_vi_handler
258 FEXPORT(except_vec_vi_ori)
259 ori v0, 0 /* Patched */
262 EXPORT(except_vec_vi_end)
265 * Common Vectored Interrupt code
266 * Complete the register saves and invoke the handler which is passed in $v0
268 NESTED(except_vec_vi_handler, 0, sp)
271 #ifdef CONFIG_MIPS_MT_SMTC
273 * SMTC has an interesting problem that interrupts are level-triggered,
274 * and the CLI macro will clear EXL, potentially causing a duplicate
275 * interrupt service invocation. So we need to clear the associated
276 * IM bit of Status prior to doing CLI, and restore it after the
277 * service routine has been invoked - we must assume that the
278 * service routine will have cleared the state, and any active
279 * level represents a new or otherwised unserviced event...
283 #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
284 mfc0 t2, CP0_TCCONTEXT
286 mtc0 t2, CP0_TCCONTEXT
287 #endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
291 #endif /* CONFIG_MIPS_MT_SMTC */
293 #ifdef CONFIG_TRACE_IRQFLAGS
295 #ifdef CONFIG_MIPS_MT_SMTC
299 #ifdef CONFIG_MIPS_MT_SMTC
305 LONG_L s0, TI_REGS($28)
306 LONG_S sp, TI_REGS($28)
307 PTR_LA ra, ret_from_irq
309 END(except_vec_vi_handler)
312 * EJTAG debug exception handler.
314 NESTED(ejtag_debug_handler, PT_SIZE, sp)
320 sll k0, k0, 30 # Check for SDBBP.
321 bgez k0, ejtag_return
323 PTR_LA k0, ejtag_debug_buffer
327 jal ejtag_exception_handler
329 PTR_LA k0, ejtag_debug_buffer
337 END(ejtag_debug_handler)
340 * This buffer is reserved for the use of the EJTAG debug
344 EXPORT(ejtag_debug_buffer)
351 * NMI debug exception handler for MIPS reference boards.
352 * The NMI debug exception entry point is 0xbfc00000, which
353 * normally is in the boot PROM, so the boot PROM must do a
354 * unconditional jump to this vector.
356 NESTED(except_vec_nmi, 0, sp)
362 NESTED(nmi_handler, PT_SIZE, sp)
367 jal nmi_exception_handler
374 .macro __build_clear_none
377 .macro __build_clear_sti
382 .macro __build_clear_cli
387 .macro __build_clear_fpe
389 /* gas fails to assemble cfc1 for some archs (octeon).*/ \
400 .macro __build_clear_ade
401 MFC0 t0, CP0_BADVADDR
402 PTR_S t0, PT_BVADDR(sp)
406 .macro __BUILD_silent exception
409 /* Gas tries to parse the PRINT argument as a string containing
410 string escapes and emits bogus warnings if it believes to
411 recognize an unknown escape code. So make the arguments
412 start with an n and gas will believe \n is ok ... */
413 .macro __BUILD_verbose nexception
414 LONG_L a1, PT_EPC(sp)
416 PRINT("Got \nexception at %08lx\012")
419 PRINT("Got \nexception at %016lx\012")
423 .macro __BUILD_count exception
424 LONG_L t0,exception_count_\exception
426 LONG_S t0,exception_count_\exception
427 .comm exception_count\exception, 8, 8
430 .macro __BUILD_HANDLER exception handler clear verbose ext
432 NESTED(handle_\exception, PT_SIZE, sp)
435 FEXPORT(handle_\exception\ext)
438 __BUILD_\verbose \exception
440 PTR_LA ra, ret_from_exception
442 END(handle_\exception)
445 .macro BUILD_HANDLER exception handler clear verbose
446 __BUILD_HANDLER \exception \handler \clear \verbose _int
449 BUILD_HANDLER adel ade ade silent /* #4 */
450 BUILD_HANDLER ades ade ade silent /* #5 */
451 BUILD_HANDLER ibe be cli silent /* #6 */
452 BUILD_HANDLER dbe be cli silent /* #7 */
453 BUILD_HANDLER bp bp sti silent /* #9 */
454 BUILD_HANDLER ri ri sti silent /* #10 */
455 BUILD_HANDLER cpu cpu sti silent /* #11 */
456 BUILD_HANDLER ov ov sti silent /* #12 */
457 BUILD_HANDLER tr tr sti silent /* #13 */
458 BUILD_HANDLER fpe fpe fpe silent /* #15 */
459 BUILD_HANDLER mdmx mdmx sti silent /* #22 */
460 #ifdef CONFIG_HARDWARE_WATCHPOINTS
462 * For watch, interrupts will be enabled after the watch
463 * registers are read.
465 BUILD_HANDLER watch watch cli silent /* #23 */
467 BUILD_HANDLER watch watch sti verbose /* #23 */
469 BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
470 BUILD_HANDLER mt mt sti silent /* #25 */
471 BUILD_HANDLER dsp dsp sti silent /* #26 */
472 BUILD_HANDLER reserved reserved sti verbose /* others */
475 LEAF(handle_ri_rdhwr_vivt)
476 #ifdef CONFIG_MIPS_MT_SMTC
477 PANIC_PIC("handle_ri_rdhwr_vivt called")
482 /* check if TLB contains a entry for EPC */
484 andi k1, 0xff /* ASID_MASK */
486 PTR_SRL k0, PAGE_SHIFT + 1
487 PTR_SLL k0, PAGE_SHIFT + 1
495 bltz k1, handle_ri /* slow path */
498 END(handle_ri_rdhwr_vivt)
500 LEAF(handle_ri_rdhwr)
504 /* 0x7c03e83b: rdhwr v1,$29 */
510 bne k0, k1, handle_ri /* if not ours */
511 /* The insn is rdhwr. No need to check CAUSE.BD here. */
512 get_saved_sp /* k1 := current_thread_info */
515 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
517 xori k1, _THREAD_MASK
518 LONG_L v1, TI_TP_VALUE(k1)
523 #ifndef CONFIG_CPU_DADDI_WORKAROUNDS
524 LONG_ADDIU k0, 4 /* stall on $k0 */
531 /* I hope three instructions between MTC0 and ERET are enough... */
533 xori k1, _THREAD_MASK
534 LONG_L v1, TI_TP_VALUE(k1)
543 /* A temporary overflow handler used by check_daddi(). */
547 BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */