2 * Format of an instruction in memory.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 2000 by Ralf Baechle
9 * Copyright (C) 2006 by Thiemo Seufer
10 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
11 * Copyright (C) 2014 Imagination Technologies Ltd.
13 #ifndef _UAPI_ASM_INST_H
14 #define _UAPI_ASM_INST_H
16 #include <asm/bitfield.h>
19 * Major opcodes; before MIPS IV cop1x was called cop3.
22 spec_op, bcond_op, j_op, jal_op,
23 beq_op, bne_op, blez_op, bgtz_op,
24 addi_op, addiu_op, slti_op, sltiu_op,
25 andi_op, ori_op, xori_op, lui_op,
26 cop0_op, cop1_op, cop2_op, cop1x_op,
27 beql_op, bnel_op, blezl_op, bgtzl_op,
28 daddi_op, daddiu_op, ldl_op, ldr_op,
29 spec2_op, jalx_op, mdmx_op, spec3_op,
30 lb_op, lh_op, lwl_op, lw_op,
31 lbu_op, lhu_op, lwr_op, lwu_op,
32 sb_op, sh_op, swl_op, sw_op,
33 sdl_op, sdr_op, swr_op, cache_op,
34 ll_op, lwc1_op, lwc2_op, pref_op,
35 lld_op, ldc1_op, ldc2_op, ld_op,
36 sc_op, swc1_op, swc2_op, major_3b_op,
37 scd_op, sdc1_op, sdc2_op, sd_op
41 * func field of spec opcode.
44 sll_op, movc_op, srl_op, sra_op,
45 sllv_op, pmon_op, srlv_op, srav_op,
46 jr_op, jalr_op, movz_op, movn_op,
47 syscall_op, break_op, spim_op, sync_op,
48 mfhi_op, mthi_op, mflo_op, mtlo_op,
49 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
50 mult_op, multu_op, div_op, divu_op,
51 dmult_op, dmultu_op, ddiv_op, ddivu_op,
52 add_op, addu_op, sub_op, subu_op,
53 and_op, or_op, xor_op, nor_op,
54 spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
55 dadd_op, daddu_op, dsub_op, dsubu_op,
56 tge_op, tgeu_op, tlt_op, tltu_op,
57 teq_op, spec5_unused_op, tne_op, spec6_unused_op,
58 dsll_op, spec7_unused_op, dsrl_op, dsra_op,
59 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
63 * func field of spec2 opcode.
66 madd_op, maddu_op, mul_op, spec2_3_unused_op,
67 msub_op, msubu_op, /* more unused ops */
68 clz_op = 0x20, clo_op,
69 dclz_op = 0x24, dclo_op,
74 * func field of spec3 opcode.
77 ext_op, dextm_op, dextu_op, dext_op,
78 ins_op, dinsm_op, dinsu_op, dins_op,
79 yield_op = 0x09, lx_op = 0x0a,
80 lwle_op = 0x19, lwre_op = 0x1a,
81 cachee_op = 0x1b, sbe_op = 0x1c,
82 she_op = 0x1d, sce_op = 0x1e,
83 swe_op = 0x1f, bshfl_op = 0x20,
84 swle_op = 0x21, swre_op = 0x22,
85 prefe_op = 0x23, dbshfl_op = 0x24,
86 lbue_op = 0x28, lhue_op = 0x29,
87 lbe_op = 0x2c, lhe_op = 0x2d,
88 lle_op = 0x2e, lwe_op = 0x2f,
93 * rt field of bcond opcodes.
96 bltz_op, bgez_op, bltzl_op, bgezl_op,
97 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
98 tgei_op, tgeiu_op, tlti_op, tltiu_op,
99 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
100 bltzal_op, bgezal_op, bltzall_op, bgezall_op,
101 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
102 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
103 bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
107 * rs field of cop opcodes.
110 mfc_op = 0x00, dmfc_op = 0x01,
111 cfc_op = 0x02, mfhc_op = 0x03,
112 mtc_op = 0x04, dmtc_op = 0x05,
113 ctc_op = 0x06, mthc_op = 0x07,
114 bc_op = 0x08, cop_op = 0x10,
119 * rt field of cop.bc_op opcodes
122 bcf_op, bct_op, bcfl_op, bctl_op
126 * func field of cop0 coi opcodes.
129 tlbr_op = 0x01, tlbwi_op = 0x02,
130 tlbwr_op = 0x06, tlbp_op = 0x08,
131 rfe_op = 0x10, eret_op = 0x18,
136 * func field of cop0 com opcodes.
139 tlbr1_op = 0x01, tlbw_op = 0x02,
140 tlbp1_op = 0x08, dctr_op = 0x09,
145 * fmt field of cop1 opcodes.
148 s_fmt, d_fmt, e_fmt, q_fmt,
153 * func field of cop1 instructions using d, s or w format.
156 fadd_op = 0x00, fsub_op = 0x01,
157 fmul_op = 0x02, fdiv_op = 0x03,
158 fsqrt_op = 0x04, fabs_op = 0x05,
159 fmov_op = 0x06, fneg_op = 0x07,
160 froundl_op = 0x08, ftruncl_op = 0x09,
161 fceill_op = 0x0a, ffloorl_op = 0x0b,
162 fround_op = 0x0c, ftrunc_op = 0x0d,
163 fceil_op = 0x0e, ffloor_op = 0x0f,
164 fmovc_op = 0x11, fmovz_op = 0x12,
165 fmovn_op = 0x13, frecip_op = 0x15,
166 frsqrt_op = 0x16, fcvts_op = 0x20,
167 fcvtd_op = 0x21, fcvte_op = 0x22,
168 fcvtw_op = 0x24, fcvtl_op = 0x25,
173 * func field of cop1x opcodes (MIPS IV).
176 lwxc1_op = 0x00, ldxc1_op = 0x01,
177 swxc1_op = 0x08, sdxc1_op = 0x09,
178 pfetch_op = 0x0f, madd_s_op = 0x20,
179 madd_d_op = 0x21, madd_e_op = 0x22,
180 msub_s_op = 0x28, msub_d_op = 0x29,
181 msub_e_op = 0x2a, nmadd_s_op = 0x30,
182 nmadd_d_op = 0x31, nmadd_e_op = 0x32,
183 nmsub_s_op = 0x38, nmsub_d_op = 0x39,
188 * func field for mad opcodes (MIPS IV).
191 madd_fp_op = 0x08, msub_fp_op = 0x0a,
192 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
196 * func field for special3 lx opcodes (Cavium Octeon).
209 * (microMIPS) Major opcodes.
212 mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
213 mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
214 mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
215 mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
216 mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
217 mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op,
218 mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
219 mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
220 mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
221 mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
222 mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
223 mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
224 mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
225 mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
226 mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
227 mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
231 * (microMIPS) POOL32I minor opcodes.
233 enum mm_32i_minor_op {
234 mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
235 mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
236 mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
237 mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
238 mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
239 mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
240 mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
241 mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
242 mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
246 * (microMIPS) POOL32A minor opcodes.
248 enum mm_32a_minor_op {
252 mm_pool32axf_op = 0x03c,
257 mm_addu32_op = 0x150,
258 mm_subu32_op = 0x1d0,
265 * (microMIPS) POOL32B functions.
284 * (microMIPS) POOL32C functions.
295 * (microMIPS) POOL32AXF minor opcodes.
297 enum mm_32axf_minor_op {
303 mm_jalrhb_op = 0x07c,
307 mm_jalrshb_op = 0x17c,
309 mm_syscall_op = 0x22d,
315 * (microMIPS) POOL32F minor opcodes.
317 enum mm_32f_minor_op {
339 * (microMIPS) POOL32F secondary minor opcodes.
341 enum mm_32f_10_minor_op {
351 mm_lwxc1_func = 0x048,
352 mm_swxc1_func = 0x088,
353 mm_ldxc1_func = 0x0c8,
354 mm_sdxc1_func = 0x108,
358 * (microMIPS) POOL32F secondary minor opcodes.
360 enum mm_32f_40_minor_op {
366 * (microMIPS) POOL32F secondary minor opcodes.
368 enum mm_32f_60_minor_op {
376 * (microMIPS) POOL32F secondary minor opcodes.
378 enum mm_32f_70_minor_op {
384 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
386 enum mm_32f_73_minor_op {
391 mm_ffloorl_op = 0x0c,
396 mm_ffloorw_op = 0x2c,
408 mm_ftruncl_op = 0x8c,
412 mm_ftruncw_op = 0xac,
415 mm_froundl_op = 0xcc,
418 mm_froundw_op = 0xec,
423 * (microMIPS) POOL16C minor opcodes.
425 enum mm_16c_minor_op {
431 mm_jalrs16_op = 0x0f,
432 mm_jraddiusp_op = 0x18,
436 * (microMIPS) POOL16D minor opcodes.
438 enum mm_16d_minor_op {
447 MIPS16e_jal_op = 003,
453 MIPS16e_lwsp_op = 022,
455 MIPS16e_lbu_op = 024,
456 MIPS16e_lhu_op = 025,
457 MIPS16e_lwpc_op = 026,
458 MIPS16e_lwu_op = 027,
461 MIPS16e_swsp_op = 032,
464 MIPS16e_extend_op = 036,
465 MIPS16e_i64_op = 037,
468 enum MIPS16e_i64_func {
476 enum MIPS16e_rr_func {
480 enum MIPS6e_i8_func {
481 MIPS16e_swrasp_func = 02,
485 * (microMIPS & MIPS16e) NOP instruction.
487 #define MM_NOP16 0x0c00
490 __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
491 __BITFIELD_FIELD(unsigned int target : 26,
495 struct i_format { /* signed immediate format */
496 __BITFIELD_FIELD(unsigned int opcode : 6,
497 __BITFIELD_FIELD(unsigned int rs : 5,
498 __BITFIELD_FIELD(unsigned int rt : 5,
499 __BITFIELD_FIELD(signed int simmediate : 16,
503 struct u_format { /* unsigned immediate format */
504 __BITFIELD_FIELD(unsigned int opcode : 6,
505 __BITFIELD_FIELD(unsigned int rs : 5,
506 __BITFIELD_FIELD(unsigned int rt : 5,
507 __BITFIELD_FIELD(unsigned int uimmediate : 16,
511 struct c_format { /* Cache (>= R6000) format */
512 __BITFIELD_FIELD(unsigned int opcode : 6,
513 __BITFIELD_FIELD(unsigned int rs : 5,
514 __BITFIELD_FIELD(unsigned int c_op : 3,
515 __BITFIELD_FIELD(unsigned int cache : 2,
516 __BITFIELD_FIELD(unsigned int simmediate : 16,
520 struct r_format { /* Register format */
521 __BITFIELD_FIELD(unsigned int opcode : 6,
522 __BITFIELD_FIELD(unsigned int rs : 5,
523 __BITFIELD_FIELD(unsigned int rt : 5,
524 __BITFIELD_FIELD(unsigned int rd : 5,
525 __BITFIELD_FIELD(unsigned int re : 5,
526 __BITFIELD_FIELD(unsigned int func : 6,
530 struct p_format { /* Performance counter format (R10000) */
531 __BITFIELD_FIELD(unsigned int opcode : 6,
532 __BITFIELD_FIELD(unsigned int rs : 5,
533 __BITFIELD_FIELD(unsigned int rt : 5,
534 __BITFIELD_FIELD(unsigned int rd : 5,
535 __BITFIELD_FIELD(unsigned int re : 5,
536 __BITFIELD_FIELD(unsigned int func : 6,
540 struct f_format { /* FPU register format */
541 __BITFIELD_FIELD(unsigned int opcode : 6,
542 __BITFIELD_FIELD(unsigned int : 1,
543 __BITFIELD_FIELD(unsigned int fmt : 4,
544 __BITFIELD_FIELD(unsigned int rt : 5,
545 __BITFIELD_FIELD(unsigned int rd : 5,
546 __BITFIELD_FIELD(unsigned int re : 5,
547 __BITFIELD_FIELD(unsigned int func : 6,
551 struct ma_format { /* FPU multiply and add format (MIPS IV) */
552 __BITFIELD_FIELD(unsigned int opcode : 6,
553 __BITFIELD_FIELD(unsigned int fr : 5,
554 __BITFIELD_FIELD(unsigned int ft : 5,
555 __BITFIELD_FIELD(unsigned int fs : 5,
556 __BITFIELD_FIELD(unsigned int fd : 5,
557 __BITFIELD_FIELD(unsigned int func : 4,
558 __BITFIELD_FIELD(unsigned int fmt : 2,
562 struct b_format { /* BREAK and SYSCALL */
563 __BITFIELD_FIELD(unsigned int opcode : 6,
564 __BITFIELD_FIELD(unsigned int code : 20,
565 __BITFIELD_FIELD(unsigned int func : 6,
569 struct ps_format { /* MIPS-3D / paired single format */
570 __BITFIELD_FIELD(unsigned int opcode : 6,
571 __BITFIELD_FIELD(unsigned int rs : 5,
572 __BITFIELD_FIELD(unsigned int ft : 5,
573 __BITFIELD_FIELD(unsigned int fs : 5,
574 __BITFIELD_FIELD(unsigned int fd : 5,
575 __BITFIELD_FIELD(unsigned int func : 6,
579 struct v_format { /* MDMX vector format */
580 __BITFIELD_FIELD(unsigned int opcode : 6,
581 __BITFIELD_FIELD(unsigned int sel : 4,
582 __BITFIELD_FIELD(unsigned int fmt : 1,
583 __BITFIELD_FIELD(unsigned int vt : 5,
584 __BITFIELD_FIELD(unsigned int vs : 5,
585 __BITFIELD_FIELD(unsigned int vd : 5,
586 __BITFIELD_FIELD(unsigned int func : 6,
590 struct spec3_format { /* SPEC3 */
591 __BITFIELD_FIELD(unsigned int opcode:6,
592 __BITFIELD_FIELD(unsigned int rs:5,
593 __BITFIELD_FIELD(unsigned int rt:5,
594 __BITFIELD_FIELD(signed int simmediate:9,
595 __BITFIELD_FIELD(unsigned int func:7,
600 * microMIPS instruction formats (32-bit length)
603 * Parenthesis denote whether the format is a microMIPS instruction or
604 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
606 struct fb_format { /* FPU branch format (MIPS32) */
607 __BITFIELD_FIELD(unsigned int opcode : 6,
608 __BITFIELD_FIELD(unsigned int bc : 5,
609 __BITFIELD_FIELD(unsigned int cc : 3,
610 __BITFIELD_FIELD(unsigned int flag : 2,
611 __BITFIELD_FIELD(signed int simmediate : 16,
615 struct fp0_format { /* FPU multiply and add format (MIPS32) */
616 __BITFIELD_FIELD(unsigned int opcode : 6,
617 __BITFIELD_FIELD(unsigned int fmt : 5,
618 __BITFIELD_FIELD(unsigned int ft : 5,
619 __BITFIELD_FIELD(unsigned int fs : 5,
620 __BITFIELD_FIELD(unsigned int fd : 5,
621 __BITFIELD_FIELD(unsigned int func : 6,
625 struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */
626 __BITFIELD_FIELD(unsigned int opcode : 6,
627 __BITFIELD_FIELD(unsigned int ft : 5,
628 __BITFIELD_FIELD(unsigned int fs : 5,
629 __BITFIELD_FIELD(unsigned int fd : 5,
630 __BITFIELD_FIELD(unsigned int fmt : 3,
631 __BITFIELD_FIELD(unsigned int op : 2,
632 __BITFIELD_FIELD(unsigned int func : 6,
636 struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */
637 __BITFIELD_FIELD(unsigned int opcode : 6,
638 __BITFIELD_FIELD(unsigned int op : 5,
639 __BITFIELD_FIELD(unsigned int rt : 5,
640 __BITFIELD_FIELD(unsigned int fs : 5,
641 __BITFIELD_FIELD(unsigned int fd : 5,
642 __BITFIELD_FIELD(unsigned int func : 6,
646 struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */
647 __BITFIELD_FIELD(unsigned int opcode : 6,
648 __BITFIELD_FIELD(unsigned int rt : 5,
649 __BITFIELD_FIELD(unsigned int fs : 5,
650 __BITFIELD_FIELD(unsigned int fmt : 2,
651 __BITFIELD_FIELD(unsigned int op : 8,
652 __BITFIELD_FIELD(unsigned int func : 6,
656 struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */
657 __BITFIELD_FIELD(unsigned int opcode : 6,
658 __BITFIELD_FIELD(unsigned int fd : 5,
659 __BITFIELD_FIELD(unsigned int fs : 5,
660 __BITFIELD_FIELD(unsigned int cc : 3,
661 __BITFIELD_FIELD(unsigned int zero : 2,
662 __BITFIELD_FIELD(unsigned int fmt : 2,
663 __BITFIELD_FIELD(unsigned int op : 3,
664 __BITFIELD_FIELD(unsigned int func : 6,
668 struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */
669 __BITFIELD_FIELD(unsigned int opcode : 6,
670 __BITFIELD_FIELD(unsigned int rt : 5,
671 __BITFIELD_FIELD(unsigned int fs : 5,
672 __BITFIELD_FIELD(unsigned int fmt : 3,
673 __BITFIELD_FIELD(unsigned int op : 7,
674 __BITFIELD_FIELD(unsigned int func : 6,
678 struct mm_fp4_format { /* FPU c.cond format (microMIPS) */
679 __BITFIELD_FIELD(unsigned int opcode : 6,
680 __BITFIELD_FIELD(unsigned int rt : 5,
681 __BITFIELD_FIELD(unsigned int fs : 5,
682 __BITFIELD_FIELD(unsigned int cc : 3,
683 __BITFIELD_FIELD(unsigned int fmt : 3,
684 __BITFIELD_FIELD(unsigned int cond : 4,
685 __BITFIELD_FIELD(unsigned int func : 6,
689 struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */
690 __BITFIELD_FIELD(unsigned int opcode : 6,
691 __BITFIELD_FIELD(unsigned int index : 5,
692 __BITFIELD_FIELD(unsigned int base : 5,
693 __BITFIELD_FIELD(unsigned int fd : 5,
694 __BITFIELD_FIELD(unsigned int op : 5,
695 __BITFIELD_FIELD(unsigned int func : 6,
699 struct fp6_format { /* FPU madd and msub format (MIPS IV) */
700 __BITFIELD_FIELD(unsigned int opcode : 6,
701 __BITFIELD_FIELD(unsigned int fr : 5,
702 __BITFIELD_FIELD(unsigned int ft : 5,
703 __BITFIELD_FIELD(unsigned int fs : 5,
704 __BITFIELD_FIELD(unsigned int fd : 5,
705 __BITFIELD_FIELD(unsigned int func : 6,
709 struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */
710 __BITFIELD_FIELD(unsigned int opcode : 6,
711 __BITFIELD_FIELD(unsigned int ft : 5,
712 __BITFIELD_FIELD(unsigned int fs : 5,
713 __BITFIELD_FIELD(unsigned int fd : 5,
714 __BITFIELD_FIELD(unsigned int fr : 5,
715 __BITFIELD_FIELD(unsigned int func : 6,
719 struct mm_i_format { /* Immediate format (microMIPS) */
720 __BITFIELD_FIELD(unsigned int opcode : 6,
721 __BITFIELD_FIELD(unsigned int rt : 5,
722 __BITFIELD_FIELD(unsigned int rs : 5,
723 __BITFIELD_FIELD(signed int simmediate : 16,
727 struct mm_m_format { /* Multi-word load/store format (microMIPS) */
728 __BITFIELD_FIELD(unsigned int opcode : 6,
729 __BITFIELD_FIELD(unsigned int rd : 5,
730 __BITFIELD_FIELD(unsigned int base : 5,
731 __BITFIELD_FIELD(unsigned int func : 4,
732 __BITFIELD_FIELD(signed int simmediate : 12,
736 struct mm_x_format { /* Scaled indexed load format (microMIPS) */
737 __BITFIELD_FIELD(unsigned int opcode : 6,
738 __BITFIELD_FIELD(unsigned int index : 5,
739 __BITFIELD_FIELD(unsigned int base : 5,
740 __BITFIELD_FIELD(unsigned int rd : 5,
741 __BITFIELD_FIELD(unsigned int func : 11,
746 * microMIPS instruction formats (16-bit length)
748 struct mm_b0_format { /* Unconditional branch format (microMIPS) */
749 __BITFIELD_FIELD(unsigned int opcode : 6,
750 __BITFIELD_FIELD(signed int simmediate : 10,
751 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
755 struct mm_b1_format { /* Conditional branch format (microMIPS) */
756 __BITFIELD_FIELD(unsigned int opcode : 6,
757 __BITFIELD_FIELD(unsigned int rs : 3,
758 __BITFIELD_FIELD(signed int simmediate : 7,
759 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
763 struct mm16_m_format { /* Multi-word load/store format */
764 __BITFIELD_FIELD(unsigned int opcode : 6,
765 __BITFIELD_FIELD(unsigned int func : 4,
766 __BITFIELD_FIELD(unsigned int rlist : 2,
767 __BITFIELD_FIELD(unsigned int imm : 4,
768 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
772 struct mm16_rb_format { /* Signed immediate format */
773 __BITFIELD_FIELD(unsigned int opcode : 6,
774 __BITFIELD_FIELD(unsigned int rt : 3,
775 __BITFIELD_FIELD(unsigned int base : 3,
776 __BITFIELD_FIELD(signed int simmediate : 4,
777 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
781 struct mm16_r3_format { /* Load from global pointer format */
782 __BITFIELD_FIELD(unsigned int opcode : 6,
783 __BITFIELD_FIELD(unsigned int rt : 3,
784 __BITFIELD_FIELD(signed int simmediate : 7,
785 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
789 struct mm16_r5_format { /* Load/store from stack pointer format */
790 __BITFIELD_FIELD(unsigned int opcode : 6,
791 __BITFIELD_FIELD(unsigned int rt : 5,
792 __BITFIELD_FIELD(signed int simmediate : 5,
793 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
798 * MIPS16e instruction formats (16-bit length)
801 __BITFIELD_FIELD(unsigned int opcode : 5,
802 __BITFIELD_FIELD(unsigned int rx : 3,
803 __BITFIELD_FIELD(unsigned int nd : 1,
804 __BITFIELD_FIELD(unsigned int l : 1,
805 __BITFIELD_FIELD(unsigned int ra : 1,
806 __BITFIELD_FIELD(unsigned int func : 5,
811 __BITFIELD_FIELD(unsigned int opcode : 5,
812 __BITFIELD_FIELD(unsigned int x : 1,
813 __BITFIELD_FIELD(unsigned int imm20_16 : 5,
814 __BITFIELD_FIELD(signed int imm25_21 : 5,
819 __BITFIELD_FIELD(unsigned int opcode : 5,
820 __BITFIELD_FIELD(unsigned int func : 3,
821 __BITFIELD_FIELD(unsigned int imm : 8,
826 __BITFIELD_FIELD(unsigned int opcode : 5,
827 __BITFIELD_FIELD(unsigned int func : 3,
828 __BITFIELD_FIELD(unsigned int ry : 3,
829 __BITFIELD_FIELD(unsigned int imm : 5,
834 __BITFIELD_FIELD(unsigned int opcode : 5,
835 __BITFIELD_FIELD(unsigned int rx : 3,
836 __BITFIELD_FIELD(unsigned int imm : 8,
841 __BITFIELD_FIELD(unsigned int opcode : 5,
842 __BITFIELD_FIELD(unsigned int rx : 3,
843 __BITFIELD_FIELD(unsigned int ry : 3,
844 __BITFIELD_FIELD(unsigned int imm : 5,
849 __BITFIELD_FIELD(unsigned int opcode : 5,
850 __BITFIELD_FIELD(unsigned int func : 3,
851 __BITFIELD_FIELD(unsigned int imm : 8,
855 union mips_instruction {
857 unsigned short halfword[2];
858 unsigned char byte[4];
859 struct j_format j_format;
860 struct i_format i_format;
861 struct u_format u_format;
862 struct c_format c_format;
863 struct r_format r_format;
864 struct p_format p_format;
865 struct f_format f_format;
866 struct ma_format ma_format;
867 struct b_format b_format;
868 struct ps_format ps_format;
869 struct v_format v_format;
870 struct spec3_format spec3_format;
871 struct fb_format fb_format;
872 struct fp0_format fp0_format;
873 struct mm_fp0_format mm_fp0_format;
874 struct fp1_format fp1_format;
875 struct mm_fp1_format mm_fp1_format;
876 struct mm_fp2_format mm_fp2_format;
877 struct mm_fp3_format mm_fp3_format;
878 struct mm_fp4_format mm_fp4_format;
879 struct mm_fp5_format mm_fp5_format;
880 struct fp6_format fp6_format;
881 struct mm_fp6_format mm_fp6_format;
882 struct mm_i_format mm_i_format;
883 struct mm_m_format mm_m_format;
884 struct mm_x_format mm_x_format;
885 struct mm_b0_format mm_b0_format;
886 struct mm_b1_format mm_b1_format;
887 struct mm16_m_format mm16_m_format ;
888 struct mm16_rb_format mm16_rb_format;
889 struct mm16_r3_format mm16_r3_format;
890 struct mm16_r5_format mm16_r5_format;
893 union mips16e_instruction {
894 unsigned int full : 16;
898 struct m16e_ri64 ri64;
904 #endif /* _UAPI_ASM_INST_H */