arch/mips/dec/setup.c

   1 /*
   2  * System-specific setup, especially interrupts.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1998 Harald Koerfgen
   9  * Copyright (C) 2000, 2001, 2002, 2003, 2005  Maciej W. Rozycki
  10  */
  11 #include <linux/console.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/ioport.h>
  15 #include <linux/module.h>
  16 #include <linux/param.h>
  17 #include <linux/sched.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/types.h>
  20 #include <linux/pm.h>
  21
  22 #include <asm/bootinfo.h>
  23 #include <asm/cpu.h>
  24 #include <asm/cpu-features.h>
  25 #include <asm/irq.h>
  26 #include <asm/irq_cpu.h>
  27 #include <asm/mipsregs.h>
  28 #include <asm/reboot.h>
  29 #include <asm/time.h>
  30 #include <asm/traps.h>
  31 #include <asm/wbflush.h>
  32
  33 #include <asm/dec/interrupts.h>
  34 #include <asm/dec/ioasic.h>
  35 #include <asm/dec/ioasic_addrs.h>
  36 #include <asm/dec/ioasic_ints.h>
  37 #include <asm/dec/kn01.h>
  38 #include <asm/dec/kn02.h>
  39 #include <asm/dec/kn02ba.h>
  40 #include <asm/dec/kn02ca.h>
  41 #include <asm/dec/kn03.h>
  42 #include <asm/dec/kn230.h>
  43 #include <asm/dec/system.h>
  44
  45
  46 extern void dec_machine_restart(char *command);
  47 extern void dec_machine_halt(void);
  48 extern void dec_machine_power_off(void);
  49 extern irqreturn_t dec_intr_halt(int irq, void *dev_id);
  50
  51 unsigned long dec_kn_slot_base, dec_kn_slot_size;
  52
  53 EXPORT_SYMBOL(dec_kn_slot_base);
  54 EXPORT_SYMBOL(dec_kn_slot_size);
  55
  56 int dec_tc_bus;
  57
  58 DEFINE_SPINLOCK(ioasic_ssr_lock);
  59
  60 volatile u32 *ioasic_base;
  61
  62 EXPORT_SYMBOL(ioasic_base);
  63
  64 /*
  65  * IRQ routing and priority tables.  Priorites are set as follows:
  66  *
  67  *              KN01    KN230   KN02    KN02-BA KN02-CA KN03
  68  *
  69  * MEMORY       CPU     CPU     CPU     ASIC    CPU     CPU
  70  * RTC          CPU     CPU     CPU     ASIC    CPU     CPU
  71  * DMA          -       -       -       ASIC    ASIC    ASIC
  72  * SERIAL0      CPU     CPU     CSR     ASIC    ASIC    ASIC
  73  * SERIAL1      -       -       -       ASIC    -       ASIC
  74  * SCSI         CPU     CPU     CSR     ASIC    ASIC    ASIC
  75  * ETHERNET     CPU     *       CSR     ASIC    ASIC    ASIC
  76  * other        -       -       -       ASIC    -       -
  77  * TC2          -       -       CSR     CPU     ASIC    ASIC
  78  * TC1          -       -       CSR     CPU     ASIC    ASIC
  79  * TC0          -       -       CSR     CPU     ASIC    ASIC
  80  * other        -       CPU     -       CPU     ASIC    ASIC
  81  * other        -       -       -       -       CPU     CPU
  82  *
  83  * * -- shared with SCSI
  84  */
  85
  86 int dec_interrupt[DEC_NR_INTS] = {
  87         [0 ... DEC_NR_INTS - 1] = -1
  88 };
  89
  90 EXPORT_SYMBOL(dec_interrupt);
  91
  92 int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
  93         { { .i = ~0 }, { .p = dec_intr_unimplemented } },
  94 };
  95 int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
  96         { { .i = ~0 }, { .p = asic_intr_unimplemented } },
  97 };
  98 int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
  99
 100 static struct irqaction ioirq = {
 101         .handler = no_action,
 102         .name = "cascade",
 103 };
 104 static struct irqaction fpuirq = {
 105         .handler = no_action,
 106         .name = "fpu",
 107 };
 108
 109 static struct irqaction busirq = {
 110         .flags = IRQF_DISABLED,
 111         .name = "bus error",
 112 };
 113
 114 static struct irqaction haltirq = {
 115         .handler = dec_intr_halt,
 116         .name = "halt",
 117 };
 118
 119
 120 /*
 121  * Bus error (DBE/IBE exceptions and bus interrupts) handling setup.
 122  */
 123 static void __init dec_be_init(void)
 124 {
 125         switch (mips_machtype) {
 126         case MACH_DS23100:      /* DS2100/DS3100 Pmin/Pmax */
 127                 board_be_handler = dec_kn01_be_handler;
 128                 busirq.handler = dec_kn01_be_interrupt;
 129                 busirq.flags |= IRQF_SHARED;
 130                 dec_kn01_be_init();
 131                 break;
 132         case MACH_DS5000_1XX:   /* DS5000/1xx 3min */
 133         case MACH_DS5000_XX:    /* DS5000/xx Maxine */
 134                 board_be_handler = dec_kn02xa_be_handler;
 135                 busirq.handler = dec_kn02xa_be_interrupt;
 136                 dec_kn02xa_be_init();
 137                 break;
 138         case MACH_DS5000_200:   /* DS5000/200 3max */
 139         case MACH_DS5000_2X0:   /* DS5000/240 3max+ */
 140         case MACH_DS5900:       /* DS5900 bigmax */
 141                 board_be_handler = dec_ecc_be_handler;
 142                 busirq.handler = dec_ecc_be_interrupt;
 143                 dec_ecc_be_init();
 144                 break;
 145         }
 146 }
 147
 148 void __init plat_mem_setup(void)
 149 {
 150         board_be_init = dec_be_init;
 151
 152         wbflush_setup();
 153
 154         _machine_restart = dec_machine_restart;
 155         _machine_halt = dec_machine_halt;
 156         pm_power_off = dec_machine_power_off;
 157
 158         ioport_resource.start = ~0UL;
 159         ioport_resource.end = 0UL;
 160 }
 161
 162 /*
 163  * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
 164  * or DS3100 (aka Pmax).
 165  */
 166 static int kn01_interrupt[DEC_NR_INTS] __initdata = {
 167         [DEC_IRQ_CASCADE]       = -1,
 168         [DEC_IRQ_AB_RECV]       = -1,
 169         [DEC_IRQ_AB_XMIT]       = -1,
 170         [DEC_IRQ_DZ11]          = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11),
 171         [DEC_IRQ_ASC]           = -1,
 172         [DEC_IRQ_FLOPPY]        = -1,
 173         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 174         [DEC_IRQ_HALT]          = -1,
 175         [DEC_IRQ_ISDN]          = -1,
 176         [DEC_IRQ_LANCE]         = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),
 177         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS),
 178         [DEC_IRQ_PSU]           = -1,
 179         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),
 180         [DEC_IRQ_SCC0]          = -1,
 181         [DEC_IRQ_SCC1]          = -1,
 182         [DEC_IRQ_SII]           = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII),
 183         [DEC_IRQ_TC0]           = -1,
 184         [DEC_IRQ_TC1]           = -1,
 185         [DEC_IRQ_TC2]           = -1,
 186         [DEC_IRQ_TIMER]         = -1,
 187         [DEC_IRQ_VIDEO]         = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO),
 188         [DEC_IRQ_ASC_MERR]      = -1,
 189         [DEC_IRQ_ASC_ERR]       = -1,
 190         [DEC_IRQ_ASC_DMA]       = -1,
 191         [DEC_IRQ_FLOPPY_ERR]    = -1,
 192         [DEC_IRQ_ISDN_ERR]      = -1,
 193         [DEC_IRQ_ISDN_RXDMA]    = -1,
 194         [DEC_IRQ_ISDN_TXDMA]    = -1,
 195         [DEC_IRQ_LANCE_MERR]    = -1,
 196         [DEC_IRQ_SCC0A_RXERR]   = -1,
 197         [DEC_IRQ_SCC0A_RXDMA]   = -1,
 198         [DEC_IRQ_SCC0A_TXERR]   = -1,
 199         [DEC_IRQ_SCC0A_TXDMA]   = -1,
 200         [DEC_IRQ_AB_RXERR]      = -1,
 201         [DEC_IRQ_AB_RXDMA]      = -1,
 202         [DEC_IRQ_AB_TXERR]      = -1,
 203         [DEC_IRQ_AB_TXDMA]      = -1,
 204         [DEC_IRQ_SCC1A_RXERR]   = -1,
 205         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 206         [DEC_IRQ_SCC1A_TXERR]   = -1,
 207         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 208 };
 209
 210 static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
 211         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },
 212                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } },
 213         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
 214                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
 215         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
 216                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
 217         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
 218                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
 219         { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
 220                 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
 221         { { .i = DEC_CPU_IRQ_ALL },
 222                 { .p = cpu_all_int } },
 223 };
 224
 225 static void __init dec_init_kn01(void)
 226 {
 227         /* IRQ routing. */
 228         memcpy(&dec_interrupt, &kn01_interrupt,
 229                 sizeof(kn01_interrupt));
 230
 231         /* CPU IRQ priorities. */
 232         memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
 233                 sizeof(kn01_cpu_mask_nr_tbl));
 234
 235         mips_cpu_irq_init();
 236
 237 }                               /* dec_init_kn01 */
 238
 239
 240 /*
 241  * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate.
 242  */
 243 static int kn230_interrupt[DEC_NR_INTS] __initdata = {
 244         [DEC_IRQ_CASCADE]       = -1,
 245         [DEC_IRQ_AB_RECV]       = -1,
 246         [DEC_IRQ_AB_XMIT]       = -1,
 247         [DEC_IRQ_DZ11]          = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11),
 248         [DEC_IRQ_ASC]           = -1,
 249         [DEC_IRQ_FLOPPY]        = -1,
 250         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 251         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),
 252         [DEC_IRQ_ISDN]          = -1,
 253         [DEC_IRQ_LANCE]         = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),
 254         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS),
 255         [DEC_IRQ_PSU]           = -1,
 256         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),
 257         [DEC_IRQ_SCC0]          = -1,
 258         [DEC_IRQ_SCC1]          = -1,
 259         [DEC_IRQ_SII]           = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII),
 260         [DEC_IRQ_TC0]           = -1,
 261         [DEC_IRQ_TC1]           = -1,
 262         [DEC_IRQ_TC2]           = -1,
 263         [DEC_IRQ_TIMER]         = -1,
 264         [DEC_IRQ_VIDEO]         = -1,
 265         [DEC_IRQ_ASC_MERR]      = -1,
 266         [DEC_IRQ_ASC_ERR]       = -1,
 267         [DEC_IRQ_ASC_DMA]       = -1,
 268         [DEC_IRQ_FLOPPY_ERR]    = -1,
 269         [DEC_IRQ_ISDN_ERR]      = -1,
 270         [DEC_IRQ_ISDN_RXDMA]    = -1,
 271         [DEC_IRQ_ISDN_TXDMA]    = -1,
 272         [DEC_IRQ_LANCE_MERR]    = -1,
 273         [DEC_IRQ_SCC0A_RXERR]   = -1,
 274         [DEC_IRQ_SCC0A_RXDMA]   = -1,
 275         [DEC_IRQ_SCC0A_TXERR]   = -1,
 276         [DEC_IRQ_SCC0A_TXDMA]   = -1,
 277         [DEC_IRQ_AB_RXERR]      = -1,
 278         [DEC_IRQ_AB_RXDMA]      = -1,
 279         [DEC_IRQ_AB_TXERR]      = -1,
 280         [DEC_IRQ_AB_TXDMA]      = -1,
 281         [DEC_IRQ_SCC1A_RXERR]   = -1,
 282         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 283         [DEC_IRQ_SCC1A_TXERR]   = -1,
 284         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 285 };
 286
 287 static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
 288         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },
 289                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } },
 290         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
 291                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
 292         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
 293                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
 294         { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
 295                 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
 296         { { .i = DEC_CPU_IRQ_ALL },
 297                 { .p = cpu_all_int } },
 298 };
 299
 300 static void __init dec_init_kn230(void)
 301 {
 302         /* IRQ routing. */
 303         memcpy(&dec_interrupt, &kn230_interrupt,
 304                 sizeof(kn230_interrupt));
 305
 306         /* CPU IRQ priorities. */
 307         memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
 308                 sizeof(kn230_cpu_mask_nr_tbl));
 309
 310         mips_cpu_irq_init();
 311
 312 }                               /* dec_init_kn230 */
 313
 314
 315 /*
 316  * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max.
 317  */
 318 static int kn02_interrupt[DEC_NR_INTS] __initdata = {
 319         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE),
 320         [DEC_IRQ_AB_RECV]       = -1,
 321         [DEC_IRQ_AB_XMIT]       = -1,
 322         [DEC_IRQ_DZ11]          = KN02_IRQ_NR(KN02_CSR_INR_DZ11),
 323         [DEC_IRQ_ASC]           = KN02_IRQ_NR(KN02_CSR_INR_ASC),
 324         [DEC_IRQ_FLOPPY]        = -1,
 325         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 326         [DEC_IRQ_HALT]          = -1,
 327         [DEC_IRQ_ISDN]          = -1,
 328         [DEC_IRQ_LANCE]         = KN02_IRQ_NR(KN02_CSR_INR_LANCE),
 329         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS),
 330         [DEC_IRQ_PSU]           = -1,
 331         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),
 332         [DEC_IRQ_SCC0]          = -1,
 333         [DEC_IRQ_SCC1]          = -1,
 334         [DEC_IRQ_SII]           = -1,
 335         [DEC_IRQ_TC0]           = KN02_IRQ_NR(KN02_CSR_INR_TC0),
 336         [DEC_IRQ_TC1]           = KN02_IRQ_NR(KN02_CSR_INR_TC1),
 337         [DEC_IRQ_TC2]           = KN02_IRQ_NR(KN02_CSR_INR_TC2),
 338         [DEC_IRQ_TIMER]         = -1,
 339         [DEC_IRQ_VIDEO]         = -1,
 340         [DEC_IRQ_ASC_MERR]      = -1,
 341         [DEC_IRQ_ASC_ERR]       = -1,
 342         [DEC_IRQ_ASC_DMA]       = -1,
 343         [DEC_IRQ_FLOPPY_ERR]    = -1,
 344         [DEC_IRQ_ISDN_ERR]      = -1,
 345         [DEC_IRQ_ISDN_RXDMA]    = -1,
 346         [DEC_IRQ_ISDN_TXDMA]    = -1,
 347         [DEC_IRQ_LANCE_MERR]    = -1,
 348         [DEC_IRQ_SCC0A_RXERR]   = -1,
 349         [DEC_IRQ_SCC0A_RXDMA]   = -1,
 350         [DEC_IRQ_SCC0A_TXERR]   = -1,
 351         [DEC_IRQ_SCC0A_TXDMA]   = -1,
 352         [DEC_IRQ_AB_RXERR]      = -1,
 353         [DEC_IRQ_AB_RXDMA]      = -1,
 354         [DEC_IRQ_AB_TXERR]      = -1,
 355         [DEC_IRQ_AB_TXDMA]      = -1,
 356         [DEC_IRQ_SCC1A_RXERR]   = -1,
 357         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 358         [DEC_IRQ_SCC1A_TXERR]   = -1,
 359         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 360 };
 361
 362 static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = {
 363         { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },
 364                 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } },
 365         { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
 366                 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
 367         { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
 368                 { .p = kn02_io_int } },
 369         { { .i = DEC_CPU_IRQ_ALL },
 370                 { .p = cpu_all_int } },
 371 };
 372
 373 static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
 374         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
 375                 { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
 376         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
 377                 { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
 378         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
 379                 { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
 380         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
 381                 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
 382         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
 383                 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
 384         { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
 385                 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
 386         { { .i = KN02_IRQ_ALL },
 387                 { .p = kn02_all_int } },
 388 };
 389
 390 static void __init dec_init_kn02(void)
 391 {
 392         /* IRQ routing. */
 393         memcpy(&dec_interrupt, &kn02_interrupt,
 394                 sizeof(kn02_interrupt));
 395
 396         /* CPU IRQ priorities. */
 397         memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl,
 398                 sizeof(kn02_cpu_mask_nr_tbl));
 399
 400         /* KN02 CSR IRQ priorities. */
 401         memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
 402                 sizeof(kn02_asic_mask_nr_tbl));
 403
 404         mips_cpu_irq_init();
 405         init_kn02_irqs(KN02_IRQ_BASE);
 406
 407 }                               /* dec_init_kn02 */
 408
 409
 410 /*
 411  * Machine-specific initialisation for KN02-BA, aka DS5000/1xx
 412  * (xx = 20, 25, 33), aka 3min.  Also applies to KN04(-BA), aka
 413  * DS5000/150, aka 4min.
 414  */
 415 static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
 416         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE),
 417         [DEC_IRQ_AB_RECV]       = -1,
 418         [DEC_IRQ_AB_XMIT]       = -1,
 419         [DEC_IRQ_DZ11]          = -1,
 420         [DEC_IRQ_ASC]           = IO_IRQ_NR(KN02BA_IO_INR_ASC),
 421         [DEC_IRQ_FLOPPY]        = -1,
 422         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 423         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),
 424         [DEC_IRQ_ISDN]          = -1,
 425         [DEC_IRQ_LANCE]         = IO_IRQ_NR(KN02BA_IO_INR_LANCE),
 426         [DEC_IRQ_BUS]           = IO_IRQ_NR(KN02BA_IO_INR_BUS),
 427         [DEC_IRQ_PSU]           = IO_IRQ_NR(KN02BA_IO_INR_PSU),
 428         [DEC_IRQ_RTC]           = IO_IRQ_NR(KN02BA_IO_INR_RTC),
 429         [DEC_IRQ_SCC0]          = IO_IRQ_NR(KN02BA_IO_INR_SCC0),
 430         [DEC_IRQ_SCC1]          = IO_IRQ_NR(KN02BA_IO_INR_SCC1),
 431         [DEC_IRQ_SII]           = -1,
 432         [DEC_IRQ_TC0]           = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0),
 433         [DEC_IRQ_TC1]           = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1),
 434         [DEC_IRQ_TC2]           = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2),
 435         [DEC_IRQ_TIMER]         = -1,
 436         [DEC_IRQ_VIDEO]         = -1,
 437         [DEC_IRQ_ASC_MERR]      = IO_IRQ_NR(IO_INR_ASC_MERR),
 438         [DEC_IRQ_ASC_ERR]       = IO_IRQ_NR(IO_INR_ASC_ERR),
 439         [DEC_IRQ_ASC_DMA]       = IO_IRQ_NR(IO_INR_ASC_DMA),
 440         [DEC_IRQ_FLOPPY_ERR]    = -1,
 441         [DEC_IRQ_ISDN_ERR]      = -1,
 442         [DEC_IRQ_ISDN_RXDMA]    = -1,
 443         [DEC_IRQ_ISDN_TXDMA]    = -1,
 444         [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
 445         [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
 446         [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
 447         [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
 448         [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
 449         [DEC_IRQ_AB_RXERR]      = -1,
 450         [DEC_IRQ_AB_RXDMA]      = -1,
 451         [DEC_IRQ_AB_TXERR]      = -1,
 452         [DEC_IRQ_AB_TXDMA]      = -1,
 453         [DEC_IRQ_SCC1A_RXERR]   = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
 454         [DEC_IRQ_SCC1A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
 455         [DEC_IRQ_SCC1A_TXERR]   = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
 456         [DEC_IRQ_SCC1A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
 457 };
 458
 459 static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = {
 460         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
 461                 { .p = kn02xa_io_int } },
 462         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
 463                 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
 464         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
 465                 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
 466         { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
 467                 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
 468         { { .i = DEC_CPU_IRQ_ALL },
 469                 { .p = cpu_all_int } },
 470 };
 471
 472 static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
 473         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) },
 474                 { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } },
 475         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
 476                 { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
 477         { { .i = IO_IRQ_DMA },
 478                 { .p = asic_dma_int } },
 479         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
 480                 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
 481         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
 482                 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
 483         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
 484                 { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
 485         { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
 486                 { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
 487         { { .i = IO_IRQ_ALL },
 488                 { .p = asic_all_int } },
 489 };
 490
 491 static void __init dec_init_kn02ba(void)
 492 {
 493         /* IRQ routing. */
 494         memcpy(&dec_interrupt, &kn02ba_interrupt,
 495                 sizeof(kn02ba_interrupt));
 496
 497         /* CPU IRQ priorities. */
 498         memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl,
 499                 sizeof(kn02ba_cpu_mask_nr_tbl));
 500
 501         /* I/O ASIC IRQ priorities. */
 502         memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
 503                 sizeof(kn02ba_asic_mask_nr_tbl));
 504
 505         mips_cpu_irq_init();
 506         init_ioasic_irqs(IO_IRQ_BASE);
 507
 508 }                               /* dec_init_kn02ba */
 509
 510
 511 /*
 512  * Machine-specific initialisation for KN02-CA, aka DS5000/xx,
 513  * (xx = 20, 25, 33), aka MAXine.  Also applies to KN04(-CA), aka
 514  * DS5000/50, aka 4MAXine.
 515  */
 516 static int kn02ca_interrupt[DEC_NR_INTS] __initdata = {
 517         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE),
 518         [DEC_IRQ_AB_RECV]       = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV),
 519         [DEC_IRQ_AB_XMIT]       = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT),
 520         [DEC_IRQ_DZ11]          = -1,
 521         [DEC_IRQ_ASC]           = IO_IRQ_NR(KN02CA_IO_INR_ASC),
 522         [DEC_IRQ_FLOPPY]        = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY),
 523         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 524         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),
 525         [DEC_IRQ_ISDN]          = IO_IRQ_NR(KN02CA_IO_INR_ISDN),
 526         [DEC_IRQ_LANCE]         = IO_IRQ_NR(KN02CA_IO_INR_LANCE),
 527         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS),
 528         [DEC_IRQ_PSU]           = -1,
 529         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),
 530         [DEC_IRQ_SCC0]          = IO_IRQ_NR(KN02CA_IO_INR_SCC0),
 531         [DEC_IRQ_SCC1]          = -1,
 532         [DEC_IRQ_SII]           = -1,
 533         [DEC_IRQ_TC0]           = IO_IRQ_NR(KN02CA_IO_INR_TC0),
 534         [DEC_IRQ_TC1]           = IO_IRQ_NR(KN02CA_IO_INR_TC1),
 535         [DEC_IRQ_TC2]           = -1,
 536         [DEC_IRQ_TIMER]         = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER),
 537         [DEC_IRQ_VIDEO]         = IO_IRQ_NR(KN02CA_IO_INR_VIDEO),
 538         [DEC_IRQ_ASC_MERR]      = IO_IRQ_NR(IO_INR_ASC_MERR),
 539         [DEC_IRQ_ASC_ERR]       = IO_IRQ_NR(IO_INR_ASC_ERR),
 540         [DEC_IRQ_ASC_DMA]       = IO_IRQ_NR(IO_INR_ASC_DMA),
 541         [DEC_IRQ_FLOPPY_ERR]    = IO_IRQ_NR(IO_INR_FLOPPY_ERR),
 542         [DEC_IRQ_ISDN_ERR]      = IO_IRQ_NR(IO_INR_ISDN_ERR),
 543         [DEC_IRQ_ISDN_RXDMA]    = IO_IRQ_NR(IO_INR_ISDN_RXDMA),
 544         [DEC_IRQ_ISDN_TXDMA]    = IO_IRQ_NR(IO_INR_ISDN_TXDMA),
 545         [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
 546         [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
 547         [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
 548         [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
 549         [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
 550         [DEC_IRQ_AB_RXERR]      = IO_IRQ_NR(IO_INR_AB_RXERR),
 551         [DEC_IRQ_AB_RXDMA]      = IO_IRQ_NR(IO_INR_AB_RXDMA),
 552         [DEC_IRQ_AB_TXERR]      = IO_IRQ_NR(IO_INR_AB_TXERR),
 553         [DEC_IRQ_AB_TXDMA]      = IO_IRQ_NR(IO_INR_AB_TXDMA),
 554         [DEC_IRQ_SCC1A_RXERR]   = -1,
 555         [DEC_IRQ_SCC1A_RXDMA]   = -1,
 556         [DEC_IRQ_SCC1A_TXERR]   = -1,
 557         [DEC_IRQ_SCC1A_TXDMA]   = -1,
 558 };
 559
 560 static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = {
 561         { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },
 562                 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } },
 563         { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
 564                 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
 565         { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
 566                 { .p = kn02xa_io_int } },
 567         { { .i = DEC_CPU_IRQ_ALL },
 568                 { .p = cpu_all_int } },
 569 };
 570
 571 static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
 572         { { .i = IO_IRQ_DMA },
 573                 { .p = asic_dma_int } },
 574         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
 575                 { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
 576         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
 577                 { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
 578         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
 579                 { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
 580         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
 581                 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
 582         { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
 583                 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
 584         { { .i = IO_IRQ_ALL },
 585                 { .p = asic_all_int } },
 586 };
 587
 588 static void __init dec_init_kn02ca(void)
 589 {
 590         /* IRQ routing. */
 591         memcpy(&dec_interrupt, &kn02ca_interrupt,
 592                 sizeof(kn02ca_interrupt));
 593
 594         /* CPU IRQ priorities. */
 595         memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl,
 596                 sizeof(kn02ca_cpu_mask_nr_tbl));
 597
 598         /* I/O ASIC IRQ priorities. */
 599         memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
 600                 sizeof(kn02ca_asic_mask_nr_tbl));
 601
 602         mips_cpu_irq_init();
 603         init_ioasic_irqs(IO_IRQ_BASE);
 604
 605 }                               /* dec_init_kn02ca */
 606
 607
 608 /*
 609  * Machine-specific initialisation for KN03, aka DS5000/240,
 610  * aka 3max+ and DS5900, aka BIGmax.  Also applies to KN05, aka
 611  * DS5000/260, aka 4max+ and DS5900/260.
 612  */
 613 static int kn03_interrupt[DEC_NR_INTS] __initdata = {
 614         [DEC_IRQ_CASCADE]       = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),
 615         [DEC_IRQ_AB_RECV]       = -1,
 616         [DEC_IRQ_AB_XMIT]       = -1,
 617         [DEC_IRQ_DZ11]          = -1,
 618         [DEC_IRQ_ASC]           = IO_IRQ_NR(KN03_IO_INR_ASC),
 619         [DEC_IRQ_FLOPPY]        = -1,
 620         [DEC_IRQ_FPU]           = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
 621         [DEC_IRQ_HALT]          = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),
 622         [DEC_IRQ_ISDN]          = -1,
 623         [DEC_IRQ_LANCE]         = IO_IRQ_NR(KN03_IO_INR_LANCE),
 624         [DEC_IRQ_BUS]           = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS),
 625         [DEC_IRQ_PSU]           = IO_IRQ_NR(KN03_IO_INR_PSU),
 626         [DEC_IRQ_RTC]           = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),
 627         [DEC_IRQ_SCC0]          = IO_IRQ_NR(KN03_IO_INR_SCC0),
 628         [DEC_IRQ_SCC1]          = IO_IRQ_NR(KN03_IO_INR_SCC1),
 629         [DEC_IRQ_SII]           = -1,
 630         [DEC_IRQ_TC0]           = IO_IRQ_NR(KN03_IO_INR_TC0),
 631         [DEC_IRQ_TC1]           = IO_IRQ_NR(KN03_IO_INR_TC1),
 632         [DEC_IRQ_TC2]           = IO_IRQ_NR(KN03_IO_INR_TC2),
 633         [DEC_IRQ_TIMER]         = -1,
 634         [DEC_IRQ_VIDEO]         = -1,
 635         [DEC_IRQ_ASC_MERR]      = IO_IRQ_NR(IO_INR_ASC_MERR),
 636         [DEC_IRQ_ASC_ERR]       = IO_IRQ_NR(IO_INR_ASC_ERR),
 637         [DEC_IRQ_ASC_DMA]       = IO_IRQ_NR(IO_INR_ASC_DMA),
 638         [DEC_IRQ_FLOPPY_ERR]    = -1,
 639         [DEC_IRQ_ISDN_ERR]      = -1,
 640         [DEC_IRQ_ISDN_RXDMA]    = -1,
 641         [DEC_IRQ_ISDN_TXDMA]    = -1,
 642         [DEC_IRQ_LANCE_MERR]    = IO_IRQ_NR(IO_INR_LANCE_MERR),
 643         [DEC_IRQ_SCC0A_RXERR]   = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
 644         [DEC_IRQ_SCC0A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
 645         [DEC_IRQ_SCC0A_TXERR]   = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
 646         [DEC_IRQ_SCC0A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
 647         [DEC_IRQ_AB_RXERR]      = -1,
 648         [DEC_IRQ_AB_RXDMA]      = -1,
 649         [DEC_IRQ_AB_TXERR]      = -1,
 650         [DEC_IRQ_AB_TXDMA]      = -1,
 651         [DEC_IRQ_SCC1A_RXERR]   = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
 652         [DEC_IRQ_SCC1A_RXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
 653         [DEC_IRQ_SCC1A_TXERR]   = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
 654         [DEC_IRQ_SCC1A_TXDMA]   = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
 655 };
 656
 657 static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = {
 658         { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },
 659                 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } },
 660         { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
 661                 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
 662         { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },
 663                 { .p = kn03_io_int } },
 664         { { .i = DEC_CPU_IRQ_ALL },
 665                 { .p = cpu_all_int } },
 666 };
 667
 668 static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
 669         { { .i = IO_IRQ_DMA },
 670                 { .p = asic_dma_int } },
 671         { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) },
 672                 { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } },
 673         { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) },
 674                 { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } },
 675         { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) },
 676                 { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } },
 677         { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) },
 678                 { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } },
 679         { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) },
 680                 { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } },
 681         { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) },
 682                 { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } },
 683         { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) },
 684                 { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } },
 685         { { .i = IO_IRQ_ALL },
 686                 { .p = asic_all_int } },
 687 };
 688
 689 static void __init dec_init_kn03(void)
 690 {
 691         /* IRQ routing. */
 692         memcpy(&dec_interrupt, &kn03_interrupt,
 693                 sizeof(kn03_interrupt));
 694
 695         /* CPU IRQ priorities. */
 696         memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl,
 697                 sizeof(kn03_cpu_mask_nr_tbl));
 698
 699         /* I/O ASIC IRQ priorities. */
 700         memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
 701                 sizeof(kn03_asic_mask_nr_tbl));
 702
 703         mips_cpu_irq_init();
 704         init_ioasic_irqs(IO_IRQ_BASE);
 705
 706 }                               /* dec_init_kn03 */
 707
 708
 709 void __init arch_init_irq(void)
 710 {
 711         switch (mips_machtype) {
 712         case MACH_DS23100:      /* DS2100/DS3100 Pmin/Pmax */
 713                 dec_init_kn01();
 714                 break;
 715         case MACH_DS5100:       /* DS5100 MIPSmate */
 716                 dec_init_kn230();
 717                 break;
 718         case MACH_DS5000_200:   /* DS5000/200 3max */
 719                 dec_init_kn02();
 720                 break;
 721         case MACH_DS5000_1XX:   /* DS5000/1xx 3min */
 722                 dec_init_kn02ba();
 723                 break;
 724         case MACH_DS5000_2X0:   /* DS5000/240 3max+ */
 725         case MACH_DS5900:       /* DS5900 bigmax */
 726                 dec_init_kn03();
 727                 break;
 728         case MACH_DS5000_XX:    /* Personal DS5000/xx */
 729                 dec_init_kn02ca();
 730                 break;
 731         case MACH_DS5800:       /* DS5800 Isis */
 732                 panic("Don't know how to set this up!");
 733                 break;
 734         case MACH_DS5400:       /* DS5400 MIPSfair */
 735                 panic("Don't know how to set this up!");
 736                 break;
 737         case MACH_DS5500:       /* DS5500 MIPSfair-2 */
 738                 panic("Don't know how to set this up!");
 739                 break;
 740         }
 741
 742         /* Free the FPU interrupt if the exception is present. */
 743         if (!cpu_has_nofpuex) {
 744                 cpu_fpu_mask = 0;
 745                 dec_interrupt[DEC_IRQ_FPU] = -1;
 746         }
 747
 748         /* Register board interrupts: FPU and cascade. */
 749         if (dec_interrupt[DEC_IRQ_FPU] >= 0)
 750                 setup_irq(dec_interrupt[DEC_IRQ_FPU], &fpuirq);
 751         if (dec_interrupt[DEC_IRQ_CASCADE] >= 0)
 752                 setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq);
 753
 754         /* Register the bus error interrupt. */
 755         if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler)
 756                 setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq);
 757
 758         /* Register the HALT interrupt. */
 759         if (dec_interrupt[DEC_IRQ_HALT] >= 0)
 760                 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
 761 }
 762
 763 asmlinkage unsigned int dec_irq_dispatch(unsigned int irq)
 764 {
 765         do_IRQ(irq);
 766         return 0;
 767 }